Hi,
On Sun, 7 Apr 2019 at 16:32, Ondřej Jirman wrote:
>
> On Sun, Apr 07, 2019 at 03:36:21PM +0200, Clément Péron wrote:
> > Hi,
> >
> > On Sat, 6 Apr 2019 at 01:45, megous via linux-sunxi
> > wrote:
> > >
> > > From: Ondrej Jirman
> > >
Hi,
On Sat, 6 Apr 2019 at 01:45, megous via linux-sunxi
wrote:
>
> From: Ondrej Jirman
>
> Orange Pi 3 has AP6256 WiFi/BT module. WiFi part of the module is
> called bcm43356 and can be used with the brcmfmac driver. The module
> is powered by the two always on regulators (not AXP805).
>
> WiFi
Hi,
On Sat, 6 Apr 2019 at 01:45, megous via linux-sunxi
wrote:
>
> From: Ondrej Jirman
>
> This series implements support for Xunlong Orange Pi 3 board.
OrangePi 3 Lite2 and One Plus boards support has already been merged.
The support is not complete but you should rebase your patches on top
From: Neil Armstrong
The Amlogic ARM Mali Midgard requires reset controls to power on and
software reset the GPU, adds these as optional in the bindings.
Signed-off-by: Neil Armstrong
Reviewed-by: Rob Herring
Signed-off-by: Kevin Hilman
---
.../devicetree/bindings/gpu/arm,mali-midgard.txt
has required by Rob Herring.
See: https://patchwork.kernel.org/patch/10699829/
The GPU opp table is taken from Jernej Škrabec's patch
on LibreELEC.tv.
Thanks,
Clement
Clément Péron (7):
dt-bindings: gpu: add bus clock for Mali Midgard GPUs
dt-bindings: gpu: mali-midgard: Add h6 mali gpu
Enable and add supply to the Mali GPU node on the
Pine H64 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
b/arch/arm64/boot/dts/allwinner
Enable and add supply to the Mali GPU node on the
Orange Pi 3 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
b/arch/arm64/boot/dts
Hi,
On Thu, 11 Apr 2019 at 09:28, Maxime Ripard wrote:
>
> On Thu, Apr 11, 2019 at 01:25:39AM +0200, Clément Péron wrote:
> > Add the mali gpu node to the H6 device-tree.
> >
> > Signed-off-by: Clément Péron
> > ---
> > arch/arm64/bo
Some SoCs adds a bus clock gate to the Mali Midgard GPU.
Add the binding for the bus clock.
Signed-off-by: Icenowy Zheng
Signed-off-by: Clément Péron
---
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation
Enable and add supply to the Mali GPU node on the
Orange Pi One Plus and Lite2 boards.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
b/arch
Enable and add supply to the Mali GPU node on the
Beelink GS1 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/arch/arm64/boot/dts
This add the H6 mali compatible in the dt-bindings to later support
specific implementation.
Signed-off-by: Clément Péron
---
.../devicetree/bindings/gpu/arm,mali-midgard.txt | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings
Add the mali gpu node to the H6 device-tree.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 80
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index
Enable and add supply to the Mali GPU node on the
Beelink GS1 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/arch/arm64/boot/dts
Hi,
On Thu, 11 Apr 2019 at 17:05, Jernej Škrabec wrote:
>
> Dne četrtek, 11. april 2019 ob 12:57:16 CEST je Clément Péron napisal(a):
> > Add the mali gpu node to the H6 device-tree.
> >
> > Signed-off-by: Clément Péron
> > ---
> > arch/arm64/bo
Hi,
On Thu, 11 Apr 2019 at 14:30, Maxime Ripard wrote:
>
> On Thu, Apr 11, 2019 at 12:57:14PM +0200, Clément Péron wrote:
> > Some SoCs adds a bus clock gate to the Mali Midgard GPU.
> >
> > Add the binding for the bus clock.
> >
> > Signed-off-by: Icenowy Zhe
Hi,
On Thu, 11 Apr 2019 at 09:27, Maxime Ripard wrote:
>
> On Thu, Apr 11, 2019 at 01:25:38AM +0200, Clément Péron wrote:
> > This add the H6 mali compatible in the dt-bindings to later support
> > specific implementation.
> >
> > Signed-off-by: Clément Péro
Enable and add supply to the Mali GPU node on the
Orange Pi 3 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
b/arch/arm64/boot/dts
Add the mali gpu node to the H6 device-tree.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index
the
order has required by Rob Herring.
See: https://patchwork.kernel.org/patch/10699829/
The GPU opp table was taken from Jernej Škrabec's patch
on LibreELEC.tv.
Thanks,
Clement
Changes in v2 (Thanks to Maxime Ripard):
- Drop GPU OPP Table
- Add clocks and clock-names in required
Clément Péron (7
Enable and add supply to the Mali GPU node on the
Orange Pi One Plus and Lite2 boards.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
b/arch
From: Neil Armstrong
The Amlogic ARM Mali Midgard requires reset controls to power on and
software reset the GPU, adds these as optional in the bindings.
Signed-off-by: Neil Armstrong
Reviewed-by: Rob Herring
Signed-off-by: Kevin Hilman
---
.../devicetree/bindings/gpu/arm,mali-midgard.txt
Hi,
On Thu, 11 Apr 2019 at 17:01, Jernej Škrabec wrote:
>
> Hi!
>
> Dne četrtek, 11. april 2019 ob 14:32:23 CEST je Maxime Ripard napisal(a):
> > On Thu, Apr 11, 2019 at 12:57:12PM +0200, Clément Péron wrote:
> > > Hi,
> > >
> > > The Allwinner H6 h
This add the H6 mali compatible in the dt-bindings to later support
specific implementation.
Signed-off-by: Clément Péron
---
.../devicetree/bindings/gpu/arm,mali-midgard.txt | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings
Some SoCs adds a bus clock gate to the Mali Midgard GPU.
Add the binding for the bus clock.
Signed-off-by: Icenowy Zheng
Signed-off-by: Clément Péron
---
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation
Enable and add supply to the Mali GPU node on the
Pine H64 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
b/arch/arm64/boot/dts/allwinner
This add the H6 mali compatible in the dt-bindings to later support
specific implementation.
Signed-off-by: Clément Péron
Reviewed-by: Rob Herring
---
.../devicetree/bindings/gpu/arm,mali-midgard.txt | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git
Allwinner H6 has an ARM Mali-T720 MP2 which required a bus_clock.
Add an optional bus_clock at the init of the panfrost driver.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_device.c | 25 +-
drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
2 files
From: Icenowy Zheng
Some SoCs adds a bus clock gate to the Mali Midgard GPU.
Add the binding for the bus clock.
Signed-off-by: Icenowy Zheng
Signed-off-by: Clément Péron
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++
1 file changed, 6
Enable and add supply to the Mali GPU node on all the
H6 boards.
Regarding the datasheet the maximum time for supply to reach
its voltage is 32ms.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 6 ++
arch/arm64/boot/dts/allwinner/sun50i-h6
in required
Clément Péron (5):
drm: panfrost: add optional bus_clock
iommu: io-pgtable: fix sanity check for non 48-bit mali iommu
dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible
arm64: dts: allwinner: Add ARM Mali GPU node for H6
arm64: dts: allwinner: Add mali GPU supply
Add the mali gpu node to the H6 device-tree.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index
Allwinner H6 SoC has a Mali T720MP2 with a 33-bit iommu which
trig the sanity check during the alloc of the pgtable.
Change the sanity check to allow non 48-bit configuration.
Suggested-by: Robin Murphy
Signed-off-by: Clément Péron
---
drivers/iommu/io-pgtable-arm.c | 2 +-
1 file changed, 1
Hi Rob,
On Fri, 17 May 2019 at 22:07, Rob Herring wrote:
>
> On Fri, May 17, 2019 at 1:47 PM Clément Péron wrote:
> >
> > Allwinner H6 has an ARM Mali-T720 MP2 which required a bus_clock.
> >
> > Add an optional bus_clock at the init of the panfrost driver.
> &
Hi Rob,
On Wed, 22 May 2019 at 21:27, Rob Herring wrote:
>
> On Tue, May 21, 2019 at 11:11 AM Clément Péron wrote:
> >
> > Hi,
> >
> > The Allwinner H6 has a Mali-T720 MP2 which should be supported by
> > the new panfrost driver. This series fix two issu
Hi Tomeu,
On Tue, 4 Jun 2019 at 09:09, Tomeu Vizoso wrote:
>
> On Mon, 3 Jun 2019 at 19:24, Clément Péron wrote:
> >
> > Hi,
> >
> >
> > On Fri, 31 May 2019 at 14:13, Neil Armstrong
> > wrote:
> > >
> > > On 31/05/2019 14:09, To
Hi,
I have rebase my kernel on latest 5.2-rc2, and my panfrost driver is
no more probing.
The issue is coming from f3617b449d0bcf3b5d80a97f51498dcf7463cf7e
drm/panfrost: Select devfreq
Currently, there is some logic for the driver to work without devfreq.
However, the driver
Hi Maxime, Joerg,
On Wed, 22 May 2019 at 21:27, Rob Herring wrote:
>
> On Tue, May 21, 2019 at 11:11 AM Clément Péron wrote:
> >
> > Hi,
> >
> > The Allwinner H6 has a Mali-T720 MP2 which should be supported by
> > the new panfrost driver. This series fix
Hi,
On Fri, 31 May 2019 at 14:13, Neil Armstrong wrote:
>
> On 31/05/2019 14:09, Tomeu Vizoso wrote:
> > On Fri, 31 May 2019 at 14:03, Neil Armstrong
> > wrote:
> >>
> >> Hi Tomeu,
> >>
> >> On 31/05/2019 13:59, Tomeu Vizoso wrote:
&g
Hi,
On Tue, 14 May 2019 at 17:17, Clément Péron wrote:
>
> Hi,
>
> On Tue, 14 May 2019 at 12:29, Neil Armstrong wrote:
> >
> > Hi,
> >
> > On 13/05/2019 17:14, Daniel Vetter wrote:
> > > On Sun, May 12, 2019 at 07:46:00PM +0200, peron.c..
Hi,
On Tue, 14 May 2019 at 12:29, Neil Armstrong wrote:
>
> Hi,
>
> On 13/05/2019 17:14, Daniel Vetter wrote:
> > On Sun, May 12, 2019 at 07:46:00PM +0200, peron.c...@gmail.com wrote:
> >> From: Clément Péron
> >>
> >> Hi,
> >>
> >>
Hi,
On Sat, 18 May 2019 at 00:17, Rob Herring wrote:
>
> On Fri, May 17, 2019 at 5:08 PM Clément Péron wrote:
> >
> > Hi Rob,
> >
> > On Fri, 17 May 2019 at 22:07, Rob Herring wrote:
> > >
> > > On Fri, May 17, 2019 at 1:47 PM Clément Péron
Allwinner H6 has an ARM Mali-T720 MP2 which required a bus_clock.
Add an optional bus_clock at the init of the panfrost driver.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_device.c | 22 ++
drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
2 files
From: Icenowy Zheng
Some SoCs adds a bus clock gate to the Mali Midgard GPU.
Add the binding for the bus clock.
Signed-off-by: Icenowy Zheng
Signed-off-by: Clément Péron
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++
1 file changed, 6
Table
- Add clocks and clock-names in required
Clément Péron (5):
drm: panfrost: add optional bus_clock
iommu: io-pgtable: fix sanity check for non 48-bit mali iommu
dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible
arm64: dts: allwinner: Add ARM Mali GPU node for H6
arm64: dts
This add the H6 mali compatible in the dt-bindings to later support
specific implementation.
Signed-off-by: Clément Péron
Reviewed-by: Rob Herring
---
.../devicetree/bindings/gpu/arm,mali-midgard.txt | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git
Add the mali gpu node to the H6 device-tree.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index
Enable and add supply to the Mali GPU node on all the
H6 boards.
Regarding the datasheet the maximum time for supply to reach
its voltage is 32ms.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 6 ++
arch/arm64/boot/dts/allwinner/sun50i-h6
Allwinner H6 SoC has a Mali T720MP2 with a 33-bit iommu which
trig the sanity check during the alloc of the pgtable.
Change the sanity check to allow non 48-bit configuration.
Suggested-by: Robin Murphy
Signed-off-by: Clément Péron
---
drivers/iommu/io-pgtable-arm.c | 2 +-
1 file changed, 1
Hi Robin,
On Tue, 14 May 2019 at 23:57, Robin Murphy wrote:
>
> On 2019-05-14 10:22 pm, Clément Péron wrote:
> > Hi,
> >
> > On Tue, 14 May 2019 at 17:17, Clément Péron wrote:
> >>
> >> Hi,
> >>
> >> On Tue, 14 May 2019 at 12:29, Neil
Hi Jagan, Chen-Yu,
On Tue, 14 May 2019 at 12:18, Chen-Yu Tsai wrote:
>
> On Mon, May 13, 2019 at 2:28 AM Jagan Teki wrote:
> >
> > On Sun, May 12, 2019 at 11:16 PM wrote:
> > >
> > > From: Clément Péron
> > >
> > > Enable and add s
Panfrost driver is shouting an error if the regulator init
return an -EPROBE_DEFFER. This is a not a real error and
it doesn't require to be display.
Check if the error is not an EPROBE_DEFFER before displaying it.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_device.c | 6
Hi Mark,
On Tue, 14 Apr 2020 at 20:55, Mark Brown wrote:
>
> On Tue, Apr 14, 2020 at 08:20:23PM +0200, Clément Péron wrote:
> > Hi Liam and Mark,
>
> You might want to flag stuff like this in the subject line, I very
> nearly deleted this without opening it since most of th
Hi Liam and Mark,
On Tue, 14 Apr 2020 at 15:10, Steven Price wrote:
>
> Hi Clément,
>
> On 13/04/2020 18:28, Clément Péron wrote:
> > Hi Steven,
> >
> > On Mon, 13 Apr 2020 at 18:35, Clément Péron wrote:
> >>
> >> Hi Steven,
> >&g
Hi Robin,
On Fri, 17 Apr 2020 at 13:10, Robin Murphy wrote:
>
> On 2020-04-16 2:42 pm, Steven Price wrote:
> [...]
> > Perhaps a better approach would be for Panfrost to hand over the struct
> > regulator objects it has already got to the OPP framework. I.e. open
> > code
In case of failure we need to remove OPP table.
Use Linux classic error handling with goto usage.
Reviewed-by: Steven Price
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git
Hi Steven,
On Mon, 13 Apr 2020 at 15:18, Steven Price wrote:
>
> On 11/04/2020 21:06, Clément Péron wrote:
> > OPP table can defined both frequency and voltage.
> >
> > Register the mali regulator if it exist.
> >
> > Signed-off-by: Clément Péron
&g
Hi,
On Mon, 13 Apr 2020 at 16:18, Clément Péron wrote:
>
> Hi Steven,
>
> On Mon, 13 Apr 2020 at 15:18, Steven Price wrote:
> >
> > On 11/04/2020 21:06, Clément Péron wrote:
> > > OPP table can defined both frequency and voltage.
> > >
>
Hi Panfrost and OPP Maintainers,
On Sat, 11 Apr 2020 at 22:06, Clément Péron wrote:
>
> OPP table can defined both frequency and voltage.
>
> Register the mali regulator if it exist.
After this patch, Panfrost update properly both voltage and frequency.
But the GPU is still not p
Hi Steven,
On Mon, 13 Apr 2020 at 18:35, Clément Péron wrote:
>
> Hi Steven,
>
> On Mon, 13 Apr 2020 at 17:55, Steven Price wrote:
> >
> > On 13/04/2020 15:31, Clément Péron wrote:
> > > Hi,
> > >
> > > On Mon, 13 Apr 2020 at 1
OPP table can defined both frequency and voltage.
Register mali regulators to OPP driver.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 34 ++---
drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
2 files changed, 31 insertions(+), 4 deletions
Hi Steven,
On Mon, 13 Apr 2020 at 17:55, Steven Price wrote:
>
> On 13/04/2020 15:31, Clément Péron wrote:
> > Hi,
> >
> > On Mon, 13 Apr 2020 at 16:18, Clément Péron wrote:
> >>
> >> Hi Steven,
> >>
> >> On Mon, 13 Apr 2020 at
Hi,
On Fri, 17 Apr 2020 at 14:33, Clément Péron wrote:
>
> Hi Robin,
>
> On Fri, 17 Apr 2020 at 13:10, Robin Murphy wrote:
> >
> > On 2020-04-16 2:42 pm, Steven Price wrote:
> > [...]
> > > Perhaps a better approach would be for Panfrost to hand over th
In case of failure we need to remove OPP table.
Use Linux classic error handling with goto usage.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/panfrost
OPP table can defined both frequency and voltage.
Register the mali regulator if it exist.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 34 ++---
drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
2 files changed, 31 insertions(+), 4 deletions
Add a simple cooling map for the GPU.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 22
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index
Some OPP tables specify voltage for each frequency. Devfreq can
handle these regulators but they should be get only 1 time to avoid
issue and know who is in charge.
If OPP table is probe don't init regulator.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 19
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 3f7ceeb1a767..14257f7476b8 100644
-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 80
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index b26f735201c7..85f43a4b651f 100644
--- a/arch/arm64/
Introduce a boolean to know if opp table has been added.
With this, we can call panfrost_devfreq_fini() in case of error
and release what has been initialised.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 25 -
drivers/gpu/drm/panfrost
Introduce a proper panfrost_devfreq to deal with devfreq variables.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 76 -
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 20 +-
drivers/gpu/drm/panfrost/panfrost_device.h | 11 +--
drivers/gpu
Devfreq cooling device framework is used in Panfrost
to throttle GPU in order to regulate its temperature.
Enable this driver for ARM64 SoC.
Signed-off-by: Clément Péron
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch
Some SoCs have several clocks defined and the OPP core
needs to know the exact name of the clk to use.
Set the clock name to "core".
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 13 +
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 1
Don't include not required headers and sort them.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
Instead of expecting an error from dev_pm_opp_of_add_table()
do a simple device_property_present() check.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/panfrost
On Sat, 9 May 2020 at 18:28, Clément Péron wrote:
>
> Hi Steven,
>
> On Thu, 7 May 2020 at 16:30, Steven Price wrote:
> >
> > On 02/05/2020 23:07, Clément Péron wrote:
> > > Hi Steven,
> > >
> > > On Tue, 14 Apr 2020 at 15:10, Steven Price wrot
Convert busy_count to a simple int protected by spinlock.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 43 +++--
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 10 -
2 files changed, 41 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu
We will later introduce regulators managed by OPP.
Only alloc regulators when it's needed. This also help use
to release the regulators only when they are allocated.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_device.c | 14 +-
drivers/gpu/drm/panfrost
This use devfreq variable that will be lock with spinlock in future
patches. We should either introduce a function to access this one
but as devfreq is optional let's just remove it.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_job.c | 4
1 file changed, 4 deletions
status: SLAVE FAULT
[ 329.411521] exception type 0xC2: TRANSLATION_FAULT_LEVEL2
[ 329.411521] access type 0x3: WRITE
[ 329.411521] source id 0xAA00
Thanks for your reviews, help on this serie,
Clement
Clément Péron (15):
drm/panfrost: avoid static declaration
drm/panfrost: clean headers
() and devfreq_fini() here.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_device.c | 37 ++
drivers/gpu/drm/panfrost/panfrost_drv.c| 15 ++---
2 files changed, 25 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/panfrost
Hi Steven,
On Thu, 7 May 2020 at 16:30, Steven Price wrote:
>
> On 02/05/2020 23:07, Clément Péron wrote:
> > Hi Steven,
> >
> > On Tue, 14 Apr 2020 at 15:10, Steven Price wrote:
> >>
> >> Hi Clément,
> >>
> >> On 13/04/2020 18:28
This declaration can be avoided so change it.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 38 ++---
1 file changed, 18 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost
Hi Steven,
On Tue, 14 Apr 2020 at 15:10, Steven Price wrote:
>
> Hi Clément,
>
> On 13/04/2020 18:28, Clément Péron wrote:
> > Hi Steven,
> >
> Getting a backtrace from the two occurrences, I see one added from:
>
>(debugfs_create_dir) fro
Hi Tomeu,
On Wed, 7 Oct 2020 at 10:58, Tomeu Vizoso wrote:
>
> Hi Clément,
>
> Have just noticed that my Pine H64 board hangs when I try to set the
> performance governor for the GPU devfreq.
>
> Is this a known bug?
Yes it is.
I try to summarize everything in this message:
Hi Maxime,
On Tue, 25 Aug 2020 at 15:35, Maxime Ripard wrote:
>
> Hi Clement,
>
> On Mon, Aug 03, 2020 at 09:54:05AM +0200, Clément Péron wrote:
> > Hi Maxime and All,
> >
> > On Sat, 4 Jul 2020 at 16:56, Clément Péron wrote:
> > >
> > > Hi
Hi Steven,
On Thu, 28 May 2020 at 15:22, Steven Price wrote:
>
> On 10/05/2020 17:55, Clément Péron wrote:
> > Instead of expecting an error from dev_pm_opp_of_add_table()
> > do a simple device_property_present() check.
> >
> > Signed-off-by: Clément Péron
>
Hi Steven,
On Thu, 28 May 2020 at 15:23, Steven Price wrote:
>
> On 10/05/2020 17:55, Clément Péron wrote:
> > Some OPP tables specify voltage for each frequency. Devfreq can
> > handle these regulators but they should be get only 1 time to avoid
> > issue a
Hi Steven,
On Thu, 28 May 2020 at 15:23, Steven Price wrote:
>
> On 10/05/2020 17:55, Clément Péron wrote:
> > Some SoCs have several clocks defined and the OPP core
> > needs to know the exact name of the clk to use.
> >
> > Set the clock name to "core&quo
Hi Steven
On Thu, 28 May 2020 at 15:22, Steven Price wrote:
>
> On 10/05/2020 17:55, Clément Péron wrote:
> > Later we will introduce devfreq probing regulator if they
> > are present. As regulator should be probe only one time we
> > need to get this
Hi Robin,
On Fri, 29 May 2020 at 14:20, Robin Murphy wrote:
>
> On 2020-05-10 17:55, Clément Péron wrote:
> > Convert busy_count to a simple int protected by spinlock.
>
> A little more reasoning might be nice.
I have follow the modification requested for lima devfreq and clea
Hi Rob,
On Fri, 7 Aug 2020 at 18:13, Rob Herring wrote:
>
> On Fri, Jul 10, 2020 at 3:54 AM Clément Péron wrote:
> >
> > Hi,
> >
> > This serie cleans and adds regulator support to Panfrost devfreq.
> > This is mostly based on comment for the freshly introduc
On Fri, 7 Aug 2020 at 18:28, Clément Péron wrote:
>
> Hi Rob,
>
> On Fri, 7 Aug 2020 at 18:13, Rob Herring wrote:
> >
> > On Fri, Jul 10, 2020 at 3:54 AM Clément Péron wrote:
> > >
> > > Hi,
> > >
> > > This serie cleans and adds regul
Hi Maxime and All,
On Sat, 4 Jul 2020 at 16:56, Clément Péron wrote:
>
> Hi Maxime,
>
> On Sat, 4 Jul 2020 at 14:13, Maxime Ripard wrote:
> >
> > Hi,
> >
> > On Sat, Jul 04, 2020 at 12:25:34PM +0200, Clément Péron wrote:
> > > Add an O
Devfreq cooling device framework is used in Panfrost
to throttle GPU in order to regulate its temperature.
Enable this driver for ARM64 SoC.
Signed-off-by: Clément Péron
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch
Hi,
On Sat, 4 Jul 2020 at 12:25, Clément Péron wrote:
>
> Signed-off-by: Clément Péron
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
&g
Don't include not required headers and sort them.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm
Convert busy_count to a simple int protected by spinlock.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 43 +++--
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 9 -
2 files changed, 40 insertions(+), 12 deletions
This use devfreq variable that will be lock with spinlock in future
patches. We should either introduce a function to access this one
but as devfreq is optional let's just remove it.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_job.c | 4
1
Introduce a proper panfrost_devfreq to deal with devfreq variables.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 76 -
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 20 +-
drivers/gpu/drm/panfrost
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