[PATCH 4/9] drm/msm: use contiguous vram for MSM_BO_SCANOUT when possible

2018-11-15 Thread Jonathan Marek
Makes it possible to have MMU for GPU but not display. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/msm_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index d97f6ecb0531..6657453a3a58 100644

[PATCH 6/9] drm/msm/adreno: add a2xx

2018-11-15 Thread Jonathan Marek
derived from the a3xx driver and tested on the following hardware: imx51-zii-rdu1 (a200 with 128kb gmem) imx53-qsrb (a200) msm8060-tenderloin (a220) Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 445

[PATCH 3/9] drm/msm/mdp4: add lcdc-align-lsb flag to control lane alignment

2018-11-15 Thread Jonathan Marek
Controls which of the 8 lanes are used for 6 bit color. Signed-off-by: Jonathan Marek --- .../gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 22 --- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c b/drivers/gpu/drm

Re: [PATCH 5/9] drm/msm: add headless gpu device (for imx5)

2018-11-15 Thread Jonathan marek
:24:12PM -0500, Jonathan Marek wrote: Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/Kconfig | 4 ++-- drivers/gpu/drm/msm/msm_debugfs.c | 2 +- drivers/gpu/drm/msm/msm_drv.c | 15 +++ include/linux/qcom_scm.h | 3 +++ 4 files changed, 17 insertions

[PATCH 9/9] drm/msm: set priv->kms to NULL before uninit

2018-11-15 Thread Jonathan Marek
otherwise, priv->kms is non-NULL and msm_drm_uninit will cause a panic. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/msm_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index bda23011494d..94b0593f6090 100

[PATCH 7/9] drm/msm: implement a2xx mmu

2018-11-15 Thread Jonathan Marek
A2XX has its own very simple MMU. Added a msm_use_mmu() function because we can't rely on iommu_present to decide to use MMU or not. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/Makefile | 3 +- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 57 +-- drivers/gpu

[PATCH 5/9] drm/msm: add headless gpu device (for imx5)

2018-11-15 Thread Jonathan Marek
Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/Kconfig | 4 ++-- drivers/gpu/drm/msm/msm_debugfs.c | 2 +- drivers/gpu/drm/msm/msm_drv.c | 15 +++ include/linux/qcom_scm.h | 3 +++ 4 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers

[PATCH 2/9] drm/msm/mdp4: allocate blank_cursor_no with MSM_BO_SCANOUT flag

2018-11-15 Thread Jonathan Marek
For allocation in contiguous memory when the GPU has MMU but not mdp4. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4

[PATCH 1/9] drm/msm/mdp4: only use lut_clk on mdp4.2+

2018-11-15 Thread Jonathan Marek
Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 22 +- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c index ae25d763cd8c..8f765f284d11 100644

[PATCH 8/9] drm/msm/mdp5: add config for msm8917

2018-11-15 Thread Jonathan Marek
Add the mdp5_cfg_hw entry for MDP5 version v1.15 found on msm8917. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 86 1 file changed, 86 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5

Re: [PATCH] qcom-scm: Include header

2019-01-01 Thread Jonathan marek
FYI, I already had a patch fixing this error (it is in linux-next: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/log/include/linux/qcom_scm.h). This one is probably better though. On 12/28/2018 02:31 PM, Bjorn Andersson wrote: On Wed 26 Dec 04:06 PST 2018, Fabio Estevam

Re: [Freedreno] [PATCH v2 5/9] drm/msm: add headless gpu device (for imx5)

2018-11-29 Thread Jonathan marek
On 11/26/2018 10:48 AM, Jordan Crouse wrote: On Wed, Nov 21, 2018 at 08:52:31PM -0500, Jonathan Marek wrote: This patch allows using drm/msm without qcom display hardware. This is especially useful for iMX5 hardware, which has a a2xx GPU but uses the imx-drm driver for display. Signed-off

[PATCH v3 2/4] drm/msm: add headless gpu device for imx5

2018-12-04 Thread Jonathan Marek
This patch allows using drm/msm without qcom display hardware. It adds a amd,imageon compatible, which is used instead of qcom,adreno, but does not require a top level msm node. Signed-off-by: Jonathan Marek --- v3: reworked to work with only a amd,imageon node drivers/gpu/drm/msm/Kconfig

[PATCH v3 3/4] drm/msm: implement a2xx mmu

2018-12-04 Thread Jonathan Marek
A2XX has its own very simple MMU. Added a msm_use_mmu() function because we can't rely on iommu_present to decide to use MMU or not. Signed-off-by: Jonathan Marek --- v3: rebased on msm-next-staging and moved is_a2xx initialization earlier drivers/gpu/drm/msm/Makefile | 3

[PATCH v3 1/4] drm/msm/mdp4: add lcdc-align-lsb flag to control lane alignment

2018-12-04 Thread Jonathan Marek
This allows controlling which of the 8 lanes are used for 6 bit color. Signed-off-by: Jonathan Marek --- v3: removed empty line and added documentation .../devicetree/bindings/display/msm/mdp4.txt | 2 ++ .../gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 21 --- 2 files changed

[PATCH v4 3/5] drm/msm: implement a2xx mmu

2018-12-05 Thread Jonathan Marek
A2XX has its own very simple MMU. Added a msm_use_mmu() function because we can't rely on iommu_present to decide to use MMU or not. Signed-off-by: Jonathan Marek --- v3: rebased on msm-next-staging and moved is_a2xx initialization earlier drivers/gpu/drm/msm/Makefile | 3

[PATCH v4 1/5] drm/msm/mdp4: add lcdc-align-lsb flag to control lane alignment

2018-12-05 Thread Jonathan Marek
This allows controlling which of the 8 lanes are used for 6 bit color. Signed-off-by: Jonathan Marek --- v3: removed empty line and added documentation .../devicetree/bindings/display/msm/mdp4.txt | 2 ++ .../gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 21 --- 2 files changed

[PATCH v4 2/5] drm/msm: add headless gpu device for imx5

2018-12-05 Thread Jonathan Marek
This patch allows using drm/msm without qcom display hardware. It adds a amd,imageon compatible, which is used instead of qcom,adreno, but does not require a top level msm node. Signed-off-by: Jonathan Marek --- v3: reworked to work with only a amd,imageon node drivers/gpu/drm/msm/Kconfig

[PATCH v4 5/5] dt-bindings: display: msm/gpu: document amd, imageon compatible

2018-12-05 Thread Jonathan Marek
Document the new amd,imageon compatible, used for non-qcom hardware that uses the drm/msm driver (iMX5). Signed-off-by: Jonathan Marek --- Documentation/devicetree/bindings/display/msm/gpu.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree

[PATCH v2 2/9] drm/msm/mdp4: allocate blank_cursor_no with MSM_BO_SCANOUT flag

2018-11-22 Thread Jonathan Marek
For allocation in contiguous memory when the GPU has MMU but not mdp4. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4

[PATCH v2 6/9] drm/msm/adreno: add a2xx

2018-11-22 Thread Jonathan Marek
derived from the a3xx driver and tested on the following hardware: imx51-zii-rdu1 (a200 with 128kb gmem) imx53-qsrb (a200) msm8060-tenderloin (a220) Signed-off-by: Jonathan Marek Reviewed-by: Jordan Crouse --- v2: -fail when MMU is not present (instead of just a warning, matches a3xx) -removed

[PATCH v2 7/9] drm/msm: implement a2xx mmu

2018-11-22 Thread Jonathan Marek
A2XX has its own very simple MMU. Added a msm_use_mmu() function because we can't rely on iommu_present to decide to use MMU or not. Signed-off-by: Jonathan Marek --- v2: -tlb flush from cpu every time the page table is updated -keep missing MMU error path, in case MMU init fails -small

[PATCH v2 4/9] drm/msm: use contiguous vram for MSM_BO_SCANOUT when possible

2018-11-22 Thread Jonathan Marek
Makes it possible to have MMU for GPU but not display. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/msm_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index d97f6ecb0531..6657453a3a58 100644

[PATCH v2 3/9] drm/msm/mdp4: add lcdc-align-lsb flag to control lane alignment

2018-11-22 Thread Jonathan Marek
Controls which of the 8 lanes are used for 6 bit color. Signed-off-by: Jonathan Marek --- .../gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 22 --- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c b/drivers/gpu/drm

[PATCH v2 1/9] drm/msm/mdp4: only use lut_clk on mdp4.2+

2018-11-22 Thread Jonathan Marek
Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 22 +- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c index ae25d763cd8c..8f765f284d11 100644

[PATCH v2 5/9] drm/msm: add headless gpu device (for imx5)

2018-11-22 Thread Jonathan Marek
This patch allows using drm/msm without qcom display hardware. This is especially useful for iMX5 hardware, which has a a2xx GPU but uses the imx-drm driver for display. Signed-off-by: Jonathan Marek --- v2: added commit message and removed unnecessary comment drivers/gpu/drm/msm/Kconfig

[PATCH v2 8/9] drm/msm/mdp5: add config for msm8917

2018-11-22 Thread Jonathan Marek
Add the mdp5_cfg_hw entry for MDP5 version v1.15 found on msm8917. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 86 1 file changed, 86 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5

[PATCH v2 9/9] drm/msm: set priv->kms to NULL before uninit

2018-11-22 Thread Jonathan Marek
otherwise, priv->kms is non-NULL and msm_drm_uninit will cause a panic. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/msm_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 5d7304b5f399..fd5769e4c42a 100

Re: [RFC PATCH v1 09/15] drm/msm/gpu: Move address space setup to the GPU targets

2019-03-03 Thread Jonathan Marek
There is an error in the a2xx part of this patch: 0xfff in adreno_gpu.c became 0xff in a2xx_gpu.c On 3/1/19 2:38 PM, Jordan Crouse wrote: Move the address space steup code out of the generic msm GPU code to to the individual GPU targets. This allows us to do target specific setup such as

Re: Adreno crash on i.MX53 running 5.3-rc6

2019-09-04 Thread Jonathan Marek
Hi, I tried this and it works with patches 4+5 from Rob's series and changing gpummu to use sg_phys(sg) instead of sg->dma_address (dma_address isn't set now that dma_map_sg isn't used). Jonathan On 9/3/19 11:22 AM, Rob Clark wrote: On Mon, Sep 2, 2019 at 11:03 AM Fabio Estevam wrote:

Re: [PATCH 33/33] drm/panel-simple: Fix dotclock for LG ACX467AKM-7

2020-03-03 Thread Jonathan Marek
, 2020 at 10:36:54PM -0500, Jonathan Marek wrote: Another thing: did you verify that the panel still runs at 60hz (and not dropping frames to 30hz)? IIRC that was the behavior with lower clock. Yes, the panel is running at 60 HZ according to the Xorg log with Ville's patch applied: modeset(0

Re: [PATCH 33/33] drm/panel-simple: Fix dotclock for LG ACX467AKM-7

2020-03-03 Thread Jonathan Marek
you have it force-enabled) since the results are all 26-27 (X works a bit differently and gets double the framerate somehow?) On 3/3/20 9:53 PM, Brian Masney wrote: On Tue, Mar 03, 2020 at 09:27:50PM -0500, Jonathan Marek wrote: modetest should be printing "freq: 60.0Hz", so

Re: [PATCH 33/33] drm/panel-simple: Fix dotclock for LG ACX467AKM-7

2020-03-05 Thread Jonathan Marek
The msm DSI driver does predate the addition of those fields and doesn't use them at all. Seems like it would be a bit of a hack too, since the frequency we want to use is not the "real limits of the hardware".. On 3/4/20 4:10 AM, Linus Walleij wrote: On Mon, Mar 2, 2020 at 9:49 P

Re: [PATCH 33/33] drm/panel-simple: Fix dotclock for LG ACX467AKM-7

2020-03-03 Thread Jonathan Marek
PM, Brian Masney wrote: On Tue, Mar 03, 2020 at 08:04:05AM -0500, Jonathan Marek wrote: What Xorg prints doesn't mean anything. I don't think there will be errors in dmesg, you need to run something that does pageflips as fast as possible and see that the refresh rate is still 60. (modetest with -v,

Re: [PATCH 33/33] drm/panel-simple: Fix dotclock for LG ACX467AKM-7

2020-03-03 Thread Jonathan Marek
On 3/2/20 10:13 PM, Brian Masney wrote: On Mon, Mar 02, 2020 at 03:48:22PM -0500, Jonathan Marek wrote: Hi, This is a command mode panel and the the msm/mdp5 driver uses the vrefresh field for the actual refresh rate, while the dotclock field is used for the DSI clocks. The dotclock needed

Re: [PATCH 33/33] drm/panel-simple: Fix dotclock for LG ACX467AKM-7

2020-03-03 Thread Jonathan Marek
/2/20 3:34 PM, Ville Syrjala wrote: From: Ville Syrjälä The currently listed dotclock disagrees with the currently listed vrefresh rate. Change the dotclock to match the vrefresh. Someone tell me which (if either) of the dotclock or vreresh is correct? Cc: Jonathan Marek Cc: Brian Masney Cc

Re: [PATCH 33/33] drm/panel-simple: Fix dotclock for LG ACX467AKM-7

2020-03-03 Thread Jonathan Marek
Another thing: did you verify that the panel still runs at 60hz (and not dropping frames to 30hz)? IIRC that was the behavior with lower clock. On 3/2/20 10:28 PM, Jonathan Marek wrote: On 3/2/20 10:13 PM, Brian Masney wrote: On Mon, Mar 02, 2020 at 03:48:22PM -0500, Jonathan Marek wrote

[PATCH 4/9] drm/msm/a6xx: HFI v2 for A640 and A650

2020-04-21 Thread Jonathan Marek
Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 68 --- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 7 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 117 -- drivers/gpu/drm/msm/adreno

[PATCH 6/9] drm/msm/a6xx: add support for A650 gmu rscc registers

2020-04-21 Thread Jonathan Marek
Some of the RSCC registers on A650 are in a separate region. Note this also changes the address of these registers: RSCC_TCS1_DRV0_STATUS RSCC_TCS2_DRV0_STATUS RSCC_TCS3_DRV0_STATUS Based on the values in msm-4.14 and msm-4.19 kernels. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm

[PATCH 3/9] drm/msm/a6xx: allow allocating GMU memory with a fixed address

2020-04-21 Thread Jonathan Marek
Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 748cd379065f..c6ecb3189ec5 100644 --- a/drivers/gpu/drm

Re: [PATCH 2/9] Revert "drm/msm/a6xx: Use the DMA API for GMU memory objects"

2020-04-21 Thread Jonathan Marek
On 4/20/20 3:51 PM, Bjorn Andersson wrote: On Mon 20 Apr 07:03 PDT 2020, Jonathan Marek wrote: This reverts commit a5fb8b918920c6f7706a8b5b8ea535a7f077a7f6. Why? It removes something I need for the next patches in the series, however I'm open to suggestions on a better solution (Jordan

[PATCH 8/9] drm/msm/a6xx: enable GMU log

2020-04-21 Thread Jonathan Marek
This is required for a650 to work. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 16 drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 4 3 files changed, 21 insertions(+) diff --git a/drivers

[PATCH 7/9] drm/msm/a6xx: gmu_pdc register values for A640 and A650

2020-04-21 Thread Jonathan Marek
Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 3e51939eb867..b583bf6e293b 100644

[PATCH 9/9] drm/msm/a6xx: update a6xx_hw_init for A640 and A650

2020-04-21 Thread Jonathan Marek
Adreno 640 and 650 GPUs need some registers set differently. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 14 +++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 56 ++- 2 files changed, 61 insertions(+), 9 deletions(-) diff --git a/drivers/gpu

[PATCH 5/9] drm/msm/a6xx: A640/A650 GMU firmware path

2020-04-21 Thread Jonathan Marek
Newer GPUs have different gmu firmware path. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 136 +++--- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 11 ++ drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 6 + 3 files changed, 138 insertions(+), 15

[PATCH 2/9] Revert "drm/msm/a6xx: Use the DMA API for GMU memory objects"

2020-04-21 Thread Jonathan Marek
This reverts commit a5fb8b918920c6f7706a8b5b8ea535a7f077a7f6. --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 115 +++--- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 6 +- 2 files changed, 107 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c

[PATCH 1/9] drm/msm/adreno: add A640/A650 to gpulist

2020-04-21 Thread Jonathan Marek
Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/adreno_device.c | 24 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c| 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h| 10 + 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm

[PATCH v2 7/9] drm/msm/a6xx: update pdc/rscc GMU registers for A640/A650

2020-04-22 Thread Jonathan Marek
-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 90 ++- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 10 +++ drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 38 +- 3 files changed, 85 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/msm

[PATCH v2 4/9] drm/msm/a6xx: add A640/A650 to gpulist

2020-04-22 Thread Jonathan Marek
Add Adreno 640 and 650 GPU info to the gpulist. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/adreno_device.c | 24 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c| 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h| 10 + 3 files changed, 35 insertions

[PATCH v2 1/9] drm/msm: add msm_gem_get_and_pin_iova_range

2020-04-22 Thread Jonathan Marek
This function allows pinning iova to a specific page range (for a6xx GMU). Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/msm_drv.h | 6 +- drivers/gpu/drm/msm/msm_gem.c | 28 +--- drivers/gpu/drm/msm/msm_gem_vma.c | 6 -- 3 files changed, 30

[PATCH v2 9/9] drm/msm/a6xx: update a6xx_hw_init for A640 and A650

2020-04-22 Thread Jonathan Marek
Adreno 640 and 650 GPUs need some registers set differently. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 14 +++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 56 ++- 2 files changed, 61 insertions(+), 9 deletions(-) diff --git a/drivers/gpu

[PATCH v2 5/9] drm/msm/a6xx: HFI v2 for A640 and A650

2020-04-22 Thread Jonathan Marek
Add HFI v2 code paths required by Adreno 640 and 650 GPUs. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 66 --- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 7 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 117

[PATCH v2 6/9] drm/msm/a6xx: A640/A650 GMU firmware path

2020-04-22 Thread Jonathan Marek
Newer GPUs have different GMU firmware path. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 135 +++--- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 11 ++ drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 6 + 3 files changed, 136 insertions(+), 16

[PATCH v2 2/9] drm/msm: add internal MSM_BO_MAP_PRIV flag

2020-04-22 Thread Jonathan Marek
This flag sets IOMMU_PRIV, which is required for some a6xx GMU objects. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/msm_gem.c | 3 +++ drivers/gpu/drm/msm/msm_gem.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c

Re: [PATCH 4/9] drm/msm/a6xx: HFI v2 for A640 and A650

2020-04-22 Thread Jonathan Marek
On 4/21/20 12:30 PM, Jordan Crouse wrote: On Mon, Apr 20, 2020 at 10:03:08AM -0400, Jonathan Marek wrote: Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 68 --- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 7 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c

[PATCH v2 8/9] drm/msm/a6xx: enable GMU log

2020-04-22 Thread Jonathan Marek
This is required for a650 to work. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +++ drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 4 3 files changed, 20 insertions(+) diff --git a/drivers/gpu

[PATCH v2 3/9] drm/msm/a6xx: use msm_gem for GMU memory objects

2020-04-22 Thread Jonathan Marek
This gives more fine-grained control over how memory is allocated over the DMA api. In particular, it allows using an address range or pinning to a fixed address. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 115 ++ drivers/gpu/drm/msm/adreno

[PATCH v3 6/9] drm/msm/a6xx: A640/A650 GMU firmware path

2020-04-23 Thread Jonathan Marek
Newer GPUs have different GMU firmware path. v3: updated a6xx_gmu_fw_load based on feedback, including gmu_write_bulk, and removed extra whitespace change Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 138 +++--- drivers/gpu/drm/msm/adreno

[PATCH v3 1/9] drm/msm: add msm_gem_get_and_pin_iova_range

2020-04-23 Thread Jonathan Marek
This function allows pinning iova to a specific page range (for a6xx GMU). Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/msm_drv.h | 6 +- drivers/gpu/drm/msm/msm_gem.c | 28 +--- drivers/gpu/drm/msm/msm_gem_vma.c | 6 -- 3 files changed, 30

[PATCH v3 7/9] drm/msm/a6xx: update pdc/rscc GMU registers for A640/A650

2020-04-23 Thread Jonathan Marek
: replaced adreno_is_a650 around ->rscc with checks for "rscc" resource Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 90 ++- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 10 +++ drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 38 +- 3

[PATCH v3 8/9] drm/msm/a6xx: enable GMU log

2020-04-23 Thread Jonathan Marek
This is required for a650 to work. Signed-off-by: Jonathan Marek Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +++ drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 4 3 files changed, 20 insertions

[PATCH v3 0/9] Add support for A640 and A650

2020-04-23 Thread Jonathan Marek
A650" Changes in V3: Updated patches 6 and 7 (see commit logs for details) Jonathan Marek (9): drm/msm: add msm_gem_get_and_pin_iova_range drm/msm: add internal MSM_BO_MAP_PRIV flag drm/msm/a6xx: use msm_gem for GMU memory objects drm/msm/a6xx: add A640/A650 to gpulist drm/msm/a

[PATCH v3 5/9] drm/msm/a6xx: HFI v2 for A640 and A650

2020-04-23 Thread Jonathan Marek
Add HFI v2 code paths required by Adreno 640 and 650 GPUs. Signed-off-by: Jonathan Marek Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 66 --- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 7 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +- drivers/gpu/drm

[PATCH v3 2/9] drm/msm: add internal MSM_BO_MAP_PRIV flag

2020-04-23 Thread Jonathan Marek
This flag sets IOMMU_PRIV, which is required for some a6xx GMU objects. Signed-off-by: Jonathan Marek Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_gem.c | 3 +++ drivers/gpu/drm/msm/msm_gem.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gem.c b

[PATCH v3 4/9] drm/msm/a6xx: add A640/A650 to gpulist

2020-04-23 Thread Jonathan Marek
Add Adreno 640 and 650 GPU info to the gpulist. Signed-off-by: Jonathan Marek Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/adreno_device.c | 24 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c| 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h| 10 + 3

[PATCH v3 9/9] drm/msm/a6xx: update a6xx_hw_init for A640 and A650

2020-04-23 Thread Jonathan Marek
Adreno 640 and 650 GPUs need some registers set differently. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 14 +++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 56 ++- 2 files changed, 61 insertions(+), 9 deletions(-) diff --git a/drivers/gpu

[PATCH v3 3/9] drm/msm/a6xx: use msm_gem for GMU memory objects

2020-04-23 Thread Jonathan Marek
This gives more fine-grained control over how memory is allocated over the DMA api. In particular, it allows using an address range or pinning to a fixed address. Signed-off-by: Jonathan Marek Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 115

[PATCH] drm/msm/a6xx: don't try to set GPU frequency when GMU is suspended

2020-05-19 Thread Jonathan Marek
This fixes changing the frequency in sysfs while suspended, for example when doing something like this: cat devfreq/3d0.gpu/max_freq > devfreq/3d0.gpu/min_freq Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 11 +-- 1 file changed, 9 insertions(+)

[PATCH v2] drm/msm/a6xx: skip HFI set freq if GMU is powered down

2020-05-23 Thread Jonathan Marek
Also skip the newly added HFI set freq path if the GMU is powered down, which was missing because of patches crossing paths. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu

[PATCH 6/8] drm/msm/dpu: intf timing path for displayport

2020-05-26 Thread Jonathan Marek
Calculate the correct timings for displayport, from downstream driver. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 20 +++- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers

[PATCH 5/8] drm/msm/dpu: set missing flush bits for INTF_2 and INTF_3

2020-05-26 Thread Jonathan Marek
This fixes flushing of INTF_2 and INTF_3 on SM8150 and SM8250 hardware. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 20 ++-- 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers

[PATCH 4/8] drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845

2020-05-26 Thread Jonathan Marek
: 73bfb790ac786ca55fa2786a06f59 ("msm:disp:dpu1: setup display datapath for SC7180 target") Signed-off-by: Jonathan Marek --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 20 +++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 13 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_int

[PATCH 1/8] drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250

2020-05-26 Thread Jonathan Marek
All DPU versions starting from 4.0 use the sdm845 version, so check for that instead of checking each version individually. This chooses the right function for sm8150 and sm8250. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 5 ++--- 1 file changed, 2 insertions

[PATCH 8/8] drm/msm/dpu: add SM8250 to hw catalog

2020-05-26 Thread Jonathan Marek
This brings up basic video mode functionality for SM8250 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes is also untested. Signed-off-by: Jonathan Marek --- .../gpu/drm/msm/disp/dpu1

[PATCH 2/8] drm/msm/dpu: update UBWC config for sm8150 and sm8250

2020-05-26 Thread Jonathan Marek
at is used in the upstream driver. Also simplifies the overly complicated change that was introduced in e4f9bbe9f8beab9a1ce4 to work around dpu_hw_reset_ubwc being broken. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 -- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog

[PATCH] drm/msm/a6xx: set ubwc config for A640 and A650

2020-05-26 Thread Jonathan Marek
This is required for A640 and A650 to be able to share UBWC-compressed images with other HW such as display, which expect this configuration. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 ++- 1 file changed, 32 insertions(+), 6 deletions

[PATCH 7/8] drm/msm/dpu: add SM8150 to hw catalog

2020-05-26 Thread Jonathan Marek
This brings up basic video mode functionality for SM8150 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes is also untested. Signed-off-by: Jonathan Marek --- .../gpu/drm/msm/disp/dpu1

[PATCH 0/8] Initial SM8150 and SM8250 DPU bringup

2020-05-26 Thread Jonathan Marek
currently broken for SC7180). Jonathan Marek (8): drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250 drm/msm/dpu: update UBWC config for sm8150 and sm8250 drm/msm/dpu: move some sspp caps to dpu_caps drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845 drm/msm/dpu: set missing

[PATCH 3/8] drm/msm/dpu: move some sspp caps to dpu_caps

2020-05-26 Thread Jonathan Marek
also sets max_hdeci_exp/max_vdeci_exp to 0 for sc7180, as decimation is not supported on the newest DPU versions. (note that decimation is not implemented, so this changes nothing) Signed-off-by: Jonathan Marek --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 14 +-- .../gpu/drm/msm

Re: [PATCH 7/8] drm/msm/dpu: add SM8150 to hw catalog

2020-06-13 Thread Jonathan Marek
On 6/11/20 10:37 AM, Dmitry Baryshkov wrote: On 26/05/2020 06:22, Jonathan Marek wrote: This brings up basic video mode functionality for SM8150 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes

[PATCH 1/2] drm/msm/a6xx: hwcg tables in gpulist

2020-06-30 Thread Jonathan Marek
This will allow supporting different hwcg tables for a6xx. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 129 ++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 111 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.h| 7 ++ 3 files

[PATCH 0/2] drm/msm/a6xx: add A640/A650 hwcg

2020-06-30 Thread Jonathan Marek
in adreno_device.c) Jonathan Marek (2): drm/msm/a6xx: hwcg tables in gpulist drm/msm/a6xx: add A640/A650 hwcg drivers/gpu/drm/msm/adreno/a6xx.xml.h | 8 + drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 140 ++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 219 + drivers

[PATCH] drm/msm/a6xx: fix crashstate capture for A650

2020-06-30 Thread Jonathan Marek
A650 has a separate RSCC region, so dump RSCC registers separately, reading them from the RSCC base. Without this change a GPU hang will cause a system reset if CONFIG_DEV_COREDUMP is enabled. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 5 + drivers/gpu

[PATCH 2/2] drm/msm/a6xx: add A640/A650 hwcg

2020-06-30 Thread Jonathan Marek
Initialize hardware clock-gating registers on A640 and A650 GPUs. At least for A650, this solves some performance issues. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 8 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 ++- drivers/gpu/drm/msm/adreno

[PATCH v2] drm/msm: handle for EPROBE_DEFER for of_icc_get

2020-07-10 Thread Jonathan Marek
cause INIT_LIST_HEAD won't have been called on the list yet when going through the defer error path. Changes in v2: * Changed to not only check for EPROBE_DEFER Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 ++--- drivers/gpu/drm/msm/msm_gpu.c

Re: [PATCH v4 3/7] drm: msm: a6xx: set gpu freq through hfi

2020-07-10 Thread Jonathan Marek
On 7/9/20 4:00 PM, Akhil P Oommen wrote: Newer targets support changing gpu frequency through HFI. So use that wherever supported instead of the legacy method. It was already using HFI on newer targets. Don't break it in one commit then fix it in the next. Signed-off-by: Akhil P Oommen

[PATCH v2 3/8] drm/msm/dpu: move some sspp caps to dpu_caps

2020-07-14 Thread Jonathan Marek
also sets max_hdeci_exp/max_vdeci_exp to 0 for sc7180, as decimation is not supported on the newest DPU versions. (note that decimation is not implemented, so this changes nothing) Signed-off-by: Jonathan Marek --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 14 +-- .../gpu/drm/msm

[PATCH v4 0/3] drm/msm: handle for EPROBE_DEFER for of_icc_get

2020-07-14 Thread Jonathan Marek
init has been called, the icc path init needs to be after msm_gpu_init for the error path to work. v2: changed to not only check for EPROBE_DEFER v3: move icc path init after msm_gpu_init to avoid deleting a WARN_ON v4: added two patches to fix issues with probe deferring later in v3 Jonathan Marek

[PATCH v2 1/8] drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250

2020-07-14 Thread Jonathan Marek
All DPU versions starting from 4.0 use the sdm845 version, so check for that instead of checking each version individually. This chooses the right function for sm8150 and sm8250. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 5 ++--- 1 file changed, 2 insertions

[PATCH v2 1/2] drm/msm/a6xx: hwcg tables in gpulist

2020-07-14 Thread Jonathan Marek
This will allow supporting different hwcg tables for a6xx. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 25 ++ drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + drivers/gpu/drm/msm/adreno/adreno_gpu.h| 8 +++ 3 files changed, 20

[PATCH v2 6/8] drm/msm/dpu: intf timing path for displayport

2020-07-14 Thread Jonathan Marek
Calculate the correct timings for displayport, from downstream driver. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 20 +++- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers

[PATCH v2 5/8] drm/msm/dpu: set missing flush bits for INTF_2 and INTF_3

2020-07-14 Thread Jonathan Marek
This fixes flushing of INTF_2 and INTF_3 on SM8150 and SM8250 hardware. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 20 ++-- 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers

[PATCH v2 4/8] drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845

2020-07-14 Thread Jonathan Marek
: 73bfb790ac786ca55fa2786a06f59 ("msm:disp:dpu1: setup display datapath for SC7180 target") Signed-off-by: Jonathan Marek --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 20 +++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 13 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_int

[PATCH v2 2/2] drm/msm/a6xx: add A640/A650 hwcg

2020-07-14 Thread Jonathan Marek
Initialize hardware clock-gating registers on A640 and A650 GPUs. At least for A650, this solves some performance issues. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 8 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 117 - drivers/gpu

[PATCH v2 0/8] Initial SM8150 and SM8250 DPU bringup

2020-07-14 Thread Jonathan Marek
These patches bring up SM8150 and SM8250 with basic functionality. Tested with displayport output (single mixer, video mode case). v2: rebased Jonathan Marek (8): drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250 drm/msm/dpu: update UBWC config for sm8150 and sm8250 drm/msm

[PATCH v3] drm/msm: handle for EPROBE_DEFER for of_icc_get

2020-07-14 Thread Jonathan Marek
init has been called, the icc path init needs to be after msm_gpu_init for the error path to work. v2: changed to not only check for EPROBE_DEFER v3: move icc path init after msm_gpu_init to avoid deleting a WARN_ON Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adre

[PATCH v2 7/8] drm/msm/dpu: add SM8150 to hw catalog

2020-07-14 Thread Jonathan Marek
This brings up basic video mode functionality for SM8150 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes is also untested. Signed-off-by: Jonathan Marek --- .../gpu/drm/msm/disp/dpu1

[PATCH v2 2/8] drm/msm/dpu: update UBWC config for sm8150 and sm8250

2020-07-14 Thread Jonathan Marek
at is used in the upstream driver. Also simplifies the overly complicated change that was introduced in e4f9bbe9f8beab9a1ce4 to work around dpu_hw_reset_ubwc being broken. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8 -- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog

[PATCH v2 8/8] drm/msm/dpu: add SM8250 to hw catalog

2020-07-14 Thread Jonathan Marek
This brings up basic video mode functionality for SM8250 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes is also untested. Signed-off-by: Jonathan Marek --- .../gpu/drm/msm/disp/dpu1

[PATCH v4 2/3] drm/msm: reset devfreq freq_table/max_state before devfreq_add_device

2020-07-14 Thread Jonathan Marek
These never get set back to 0 when probing fails, so an attempt to probe again results in broken behavior. Fix the problem by setting thse to zero before they are used. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/msm_gpu.c | 4 1 file changed, 4 insertions(+) diff --git

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