Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_atomic.c | 3 +-
drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
drivers/gpu
come Y plane [12:4]
followed by 2x2 subsampled Cr:Cb plane [12:4:12:4]
Add P016 definition, semi-planar yuv format where each component
is 16 bits. First come Y plane followed by 2x2 subsampled Cr:Cb
plane [16:16]
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers
Enabling of P010, P012 and P016 formats. These formats will
extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 24 +-
drivers/gpu/drm/i915/intel_sprite.c | 39
Add needed plane control flag definitions for P010, P012 and
P016 formats.
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915
On 28.08.2018 13:53, Stanislav Lisovskiy wrote:
v5: This is YUV444 packed format same as AYUV, but without alpha,
as supported by i915.
v6: Removed unneeded initializer for new XYUV format.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/drm_fourcc.c | 1 +
On 21.08.2018 17:26, Sharma, Swati2 wrote:
On 16-Aug-18 6:25 PM, Juha-Pekka Heikkila wrote:
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm
On 27.08.2018 14:28, Maarten Lankhorst wrote:
Op 16-08-18 om 14:55 schreef Juha-Pekka Heikkila:
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm
is this going on, anything holding it back from getting merged ?
I'm interested in adding/using P010, [1]
Thank you,
Alex Gheorghe
[1] https://lists.freedesktop.org/archives/dri-devel/2018-August/186963.html
On Thu, Aug 30, 2018 at 03:41:11PM +0300, Juha-Pekka Heikkila wrote:
Add P010
Enabling of P010, P012 and P016 formats. These formats will
extend NV12 for larger bit depths.
(Sharma, Swati2) Rename glk format table to follow similar style as on skl.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_display.c | 24 +++-
drivers/gpu/drm
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
(Sharma, Swati2): removed unnecessary checks, changed debug error message
to be more generic.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_atomic.c | 3
Add needed plane control flag definitions for P010, P012 and
P016 formats.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f232178..2c959c8
come Y plane [12:4]
followed by 2x2 subsampled Cr:Cb plane [12:4:12:4]
Add P016 definition, semi-planar yuv format where each component
is 16 bits. First come Y plane followed by 2x2 subsampled Cr:Cb
plane [16:16]
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/drm_fourcc.c | 3
Look good to me. There will be collision with my Pxxx patches if those
ever go upstream but it is issue of that time. I guess these patches
will also wait for IGT support?
Reviewed-by: Juha-Pekka Heikkila
___
dri-devel mailing list
dri-devel@lists.fr
(1 << 21)
#define PLANE_CTL_KEY_ENABLE_DESTINATION(2 << 21)
Reviewed-by: Juha-Pekka Heikkila
___
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
On 11.1.2019 7.30, swati2.sha...@intel.com wrote:
From: Swati Sharma
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies 32bit.
Y210: For each component, valid data
On 12.09.2018 13:32, Swati Sharma wrote:
From: Vidya Srinivas
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies a DWORD.
Just to be clear I wouldn't use 'DWORD' here
(5 << 23)
#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
Reviewed-by: Juha-Pekka Heikkila
__
On 12.09.2018 13:32, Swati Sharma wrote:
From: Vidya Srinivas
In this patch, a list for icl specific pixel formats is created
in which Y210, Y212 and Y216 pixel formats are added along with
legacy pixel formats for primary and sprite plane.
Signed-off-by: Swati Sharma
Signed-off-by: Vidya
On 17.09.2018 11:25, Lisovskiy, Stanislav wrote:
On Fri, 2018-09-14 at 20:05 +0300, Juha-Pekka Heikkilä wrote:
Lisovskiy, Stanislav kirjoitti 14.9.2018 klo 17.30:
On Fri, 2018-09-14 at 16:47 +0300, Ville Syrjälä wrote:
On Fri, Sep 14, 2018 at 01:36:32PM +, Lisovskiy, Stanislav
wrote:
On
Hi Vidya,
on which machines this would help? I see there's many vblanks already
being waited. There's igt_display_commit2 which probably will block and
even if it didn't there's igt_pipe_crc_collect_crc(..) where crc
calculation is started after flip and then get one crc before disabling
crc
On 21.10.2021 17.35, Ville Syrjälä wrote:
On Thu, Oct 21, 2021 at 07:56:24PM +0530, Ramalingam C wrote:
From: Matt Roper
DG2 unifies render compression and media compression into a single
format for the first time. The programming and buffer layout is
supposed to match compression on older
On 12.2.2022 3.17, Nanley Chery wrote:
On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C wrote:
From: Matt Roper
DG2 unifies render compression and media compression into a single
format for the first time. The programming and buffer layout is
supposed to match compression on older gen12
On 12.2.2022 3.19, Nanley Chery wrote:
On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C wrote:
From: Mika Kahola
DG2 clear color render compression uses Tile4 layout. Therefore, we need
to define a new format modifier for uAPI to support clear color rendering.
v2:
Display version is fixed.
On 15.2.2022 17.02, Chery, Nanley G wrote:
-Original Message-
From: Juha-Pekka Heikkila
Sent: Tuesday, February 15, 2022 6:56 AM
To: Nanley Chery ; C, Ramalingam
Cc: intel-gfx ; Chery, Nanley G
; Auld, Matthew ; dri-
devel
Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2
On 15.2.2022 18.44, Chery, Nanley G wrote:
-Original Message-
From: Juha-Pekka Heikkila
Sent: Tuesday, February 15, 2022 8:15 AM
To: Chery, Nanley G ; Nanley Chery
; C, Ramalingam
Cc: intel-gfx ; Auld, Matthew
; dri-devel
Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2
On 15.2.2022 20.24, Chery, Nanley G wrote:
-Original Message-
From: Juha-Pekka Heikkila
Sent: Tuesday, February 15, 2022 9:32 AM
To: Chery, Nanley G ; Nanley Chery
; C, Ramalingam
Cc: intel-gfx ; Auld, Matthew
; dri-devel
Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2
Reviewed-by: Juha-Pekka Heikkila
On 4.4.2022 16.38, Imre Deak wrote:
From: Matt Roper
The render/media engines on DG2 unify render compression and media
compression into a single format for the first time, using the Tile 4
layout for main surfaces. The compression algorithm is different from
I didn't spot anything to nag about. Just hope that warning doesn't
become excessively noisy. These two patches are
Reviewed-by: Juha-Pekka Heikkila
On 4.9.2023 7.16, Ville Syrjala wrote:
From: Ville Syrjälä
The cursor hardware only does sync updates, and thus the hardware
will be scanning
On 24.10.2022 18.58, Ville Syrjälä wrote:
On Mon, Oct 24, 2022 at 08:48:15AM -0700, Rob Clark wrote:
On Mon, Oct 24, 2022 at 5:43 AM wrote:
Hi,
I've discussing the idea for the past year to add an IGT test suite that
all well-behaved KMS drivers must pass.
The main idea behind it comes
Hi Drew,
this is good find. I went looking where the problem is in and saw what
you probably also saw earlier.
I was wondering if diff below would be better fix? I assume this would
end up with einval or erange in your case but code flow otherwise would
stay as is while fixing all future
On 12.1.2023 20.28, Ville Syrjälä wrote:
On Mon, Dec 26, 2022 at 10:53:24PM -0700, Drew Davenport wrote:
The error message suggests that the height of the src rect must be at
least 1. Reject source with height of 0.
Signed-off-by: Drew Davenport
---
I was investigating some divide-by-zero
Add Tile4 type ccs modifiers with aux buffer needed for MTL
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Juha-Pekka Heikkila
---
include/uapi/drm/drm_fourcc.h | 43 +++
1 file changed, 43 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include
Add Tile4 type ccs modifiers with aux buffer needed for MTL
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula
Signed-off-by: Juha-Pekka Heikkila
---
include/uapi/drm/drm_fourcc.h | 43 +++
1 file changed, 43 insertions(+)
diff --git a/include/uapi/drm
Add Tile4 type ccs modifiers with aux buffer needed for MTL
Bspec: 49251, 49252, 49253
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Matt Atwood
---
include/uapi/drm/drm_fourcc.h | 43 +++
1 file changed, 43
Hi Arthur,
I was taking brief look. Generally things look ok. Few comments below.
On 7.2.2024 22.17, Arthur Grillo wrote:
Create a benchmark for the VKMS driver. Use a KMS layout with deliberate
odd sizes to try to avoid alignment accidents and run it for FRAME_COUNT
frames flipping
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