On Mon, 22 Mar 2021 at 09:53, Yang Li wrote:
>
> fixed the following coccicheck:
> ./drivers/gpu/drm/omapdrm/dss/dsi.c:4329:7-27: ERROR: Threaded IRQ with
> no primary handler requested without IRQF_ONESHOT
>
> Make sure threaded IRQs without a primary handler are always request
> with IRQF_ONESHO
Joonyoung Shim
> Cc: Seung-Woo Kim
> Cc: Kyungmin Park
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: Krzysztof Kozlowski
> Cc: dri-devel@lists.freedesktop.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-samsung-...@vger.kernel.org
> Signed-of
t; Cc: Joonyoung Shim
> Cc: Seung-Woo Kim
> Cc: Kyungmin Park
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: Krzysztof Kozlowski
> Cc: Akshu Agarwal
> Cc: Ajay Kumar
> Cc: dri-devel@lists.freedesktop.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-sam
++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
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/intel_gmbus.c:386: warning:
expecting prototype for intel_gmbus_setup(). Prototype was for
gma_intel_setup_gmbus() instead
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/gma500/cdv_intel_lvds.c | 2 +-
drivers/gpu/drm/gma500/intel_gmbus.c| 2 +-
2 files changed, 2 insertions(+), 2 deletions
Remove trailing whitespaces. No functional change.
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/gma500/backlight.c| 4 +--
drivers/gpu/drm/gma500/cdv_intel_dp.c | 50 +--
2 files changed, 26 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm
Correct indentation warning:
ilitek,ili9341.yaml:25:9: [warning] wrong indentation: expected 10 but found
8 (indentation)
Signed-off-by: Krzysztof Kozlowski
---
.../devicetree/bindings/display/panel/ilitek,ili9341.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Use common enum instead of oneOf and correct indentation warning:
realtek,rt1015p.yaml:18:7: [warning] wrong indentation: expected 4 but found
6 (indentation)
Signed-off-by: Krzysztof Kozlowski
---
.../devicetree/bindings/sound/realtek,rt1015p.yaml | 6 +++---
1 file changed, 3
Correct the kerneldoc of fimd_shadow_protect_win() to fix W=1 warnings:
drivers/gpu/drm/exynos/exynos_drm_fimd.c:734: warning:
expecting prototype for shadow_protect_win(). Prototype was for
fimd_shadow_protect_win() instead
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/exynos
arily real case).
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/panel/panel-samsung-ld9040.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-samsung-ld9040.c
b/drivers/gpu/drm/panel/panel-samsung-ld9040.c
index f484147fc3a6..c4b388850a13 100644
--- a/dr
r and regulator) drivers.
Signed-off-by: Krzysztof Kozlowski
Cc: Mark Brown
Cc: Jonathan Cameron
Cc: Jingoo Han
Cc: Lee Jones
Cc: Pavel Machek
Cc: Thierry Reding
Cc: Sebastian Reichel
Cc: Daniel Thompson
---
Dear Lee,
Could you take care about this patch?
Best regards,
Krzysztof
Changes sin
On Thu, 26 Nov 2020 at 18:39, Krzysztof Kozlowski wrote:
>
> On Thu, Nov 26, 2020 at 06:26:05PM +0100, Thierry Reding wrote:
> > On Wed, Nov 04, 2020 at 07:48:53PM +0300, Dmitry Osipenko wrote:
> > > Each memory client has unique hardware ID, add these IDs.
> > &g
On Thu, Nov 26, 2020 at 06:26:05PM +0100, Thierry Reding wrote:
> On Wed, Nov 04, 2020 at 07:48:53PM +0300, Dmitry Osipenko wrote:
> > Each memory client has unique hardware ID, add these IDs.
> >
> > Acked-by: Rob Herring
> > Signed-off-by: Dmitry Osipenko
> > ---
> > include/dt-bindings/memor
; 1 file changed, 67 insertions(+)
>
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
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; 1 file changed, 68 insertions(+)
>
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
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On Thu, Nov 26, 2020 at 06:45:51PM +0100, Krzysztof Kozlowski wrote:
> On Thu, 26 Nov 2020 at 18:39, Krzysztof Kozlowski wrote:
> >
> > On Thu, Nov 26, 2020 at 06:26:05PM +0100, Thierry Reding wrote:
> > > On Wed, Nov 04, 2020 at 07:48:53PM +0300, Dmitry Osipenko wrote:
&g
On Thu, Nov 26, 2020 at 07:02:55PM +0100, Thierry Reding wrote:
> On Thu, Nov 26, 2020 at 06:39:22PM +0100, Krzysztof Kozlowski wrote:
> > On Thu, Nov 26, 2020 at 06:26:05PM +0100, Thierry Reding wrote:
> > > On Wed, Nov 04, 2020 at 07:48:53PM +0300, Dmitry Osipenko wrote:
&
On Mon, Nov 30, 2020 at 05:44:39PM +0900, Chanwoo Choi wrote:
> Hi Dmitry,
>
> The v5.10-rc6 was released from linus git tree.
> Generally, I will send the pull-quest about devfreq to linux-pm.git maintainer
> after releasing the v5.1-rc7 for the integration test on linux-pm.git.
>
> The icc patc
On Mon, Nov 30, 2020 at 11:48:18AM +0200, Georgi Djakov wrote:
> On 23.11.20 2:27, Dmitry Osipenko wrote:
> > Document opp-supported-hw property, which is not strictly necessary to
> > have on Tegra20, but it's very convenient to have because all other SoC
> > core devices will use hardware version
On Mon, Nov 16, 2020 at 07:54:03PM +, Paul Cercueil wrote:
> Hi Krzysztof,
>
> Le lun. 16 nov. 2020 à 18:53, Krzysztof Kozlowski a écrit
> :
> > The Ingenic DRM uses Common Clock Framework thus it cannot be built on
> > platforms without it (e.g. compile test
On Fri, Dec 04, 2020 at 04:54:55PM +0100, Thierry Reding wrote:
> On Tue, Dec 01, 2020 at 01:57:44AM +0300, Dmitry Osipenko wrote:
> > 01.12.2020 00:17, Jon Hunter пишет:
> > > Hi Dmitry,
> > >
> > > On 23/11/2020 00:27, Dmitry Osipenko wrote:
> > >> Add EMC OPP DVFS tables and update board device
interconnect framework
commit: 01a51facb74fb337ff9fe734caa85dd6e246ef48
Best regards,
--
Krzysztof Kozlowski
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On Tue, 3 Nov 2020 at 13:32, Sylwester Nawrocki wrote:
>
> Hi Chanwoo,
>
> On 03.11.2020 11:45, Chanwoo Choi wrote:
> > On 10/30/20 9:51 PM, Sylwester Nawrocki wrote:
> >> This patch adds registration of a child platform device for the exynos
> >> interconnect driver. It is assumed that the interc
lator) drivers.
Signed-off-by: Krzysztof Kozlowski
Cc: Dan Murphy
Acked-by: Dan Murphy
Acked-by: Jonathan Cameron
Acked-by: Sebastian Reichel
---
Dear Lee,
Could you take care about this patch?
Best regards,
Krzysztof
Changes since v2:
1. Fix subject (TP -> TI)
Changes since v1:
1.
nged, 69 insertions(+), 2 deletions(-)
I already acked it and there are no signigicant changes from v7.
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
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On Wed, Nov 04, 2020 at 11:36:53AM +0100, Sylwester Nawrocki wrote:
> Add maintainers entry for the Samsung interconnect drivers, this currently
> includes Exynos SoC generic interconnect driver.
>
> Signed-off-by: Sylwester Nawrocki
> ---
> Changes since v7:
> - new patch.
> ---
> MAINTAINERS
On Wed, Nov 04, 2020 at 11:36:52AM +0100, Sylwester Nawrocki wrote:
> This patch adds a generic interconnect driver for Exynos SoCs in order
> to provide interconnect functionality for each "samsung,exynos-bus"
> compatible device.
>
> The SoC topology is a graph (or more specifically, a tree) and
On Wed, Nov 04, 2020 at 02:22:37PM +0100, Sylwester Nawrocki wrote:
> On 04.11.2020 13:37, Krzysztof Kozlowski wrote:
> > On Wed, Nov 04, 2020 at 11:36:52AM +0100, Sylwester Nawrocki wrote:
>
> >> diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefi
On Wed, Nov 04, 2020 at 07:48:37PM +0300, Dmitry Osipenko wrote:
> We're going to modularize Tegra EMC drivers and some of the EMC-clock
> driver symbols need to be exported, let's export them.
>
> Acked-by: Thierry Reding
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/clk/tegra/clk-tegra20-e
On Wed, Nov 04, 2020 at 07:48:38PM +0300, Dmitry Osipenko wrote:
> The tegra_read_ram_code() is used by EMC drivers and we're going to make
> these driver modular, hence this function needs to be exported.
>
> Acked-by: Thierry Reding
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/soc/tegra/f
On Wed, Nov 04, 2020 at 07:48:39PM +0300, Dmitry Osipenko wrote:
> Drivers that use tegra_sku_info and have COMPILE_TEST are failing to be
> build due to the missing stub for tegra_sku_info, thus add the missing
> stub.
>
> Signed-off-by: Dmitry Osipenko
> ---
> include/soc/tegra/fuse.h | 4
On Wed, Nov 04, 2020 at 07:48:40PM +0300, Dmitry Osipenko wrote:
> There is superfluous zero in the registers base address and registers
> size should be twice bigger.
>
> Acked-by: Rob Herring
> Acked-by: Thierry Reding
> Signed-off-by: Dmitry Osipenko
> ---
> .../bindings/memory-controllers/
On Wed, Nov 04, 2020 at 07:48:41PM +0300, Dmitry Osipenko wrote:
> Tegra20 External Memory Controller talks to DRAM chips and it needs to be
> reprogrammed when memory frequency changes. Tegra Memory Controller sits
> behind EMC and these controllers are tightly coupled. This patch adds the
> new p
On Wed, Nov 04, 2020 at 07:48:42PM +0300, Dmitry Osipenko wrote:
> Memory controller is interconnected with memory clients and with the
> External Memory Controller. Document new interconnect property which
> turns memory controller into interconnect provider.
>
> Acked-by: Rob Herring
> Signed-o
On Wed, Nov 04, 2020 at 07:48:43PM +0300, Dmitry Osipenko wrote:
> External Memory Controller is interconnected with memory controller and
> with external memory. Document new interconnect property which turns EMC
> into interconnect provider.
>
> Acked-by: Rob Herring
> Signed-off-by: Dmitry Osi
On Wed, Nov 04, 2020 at 07:48:45PM +0300, Dmitry Osipenko wrote:
> Memory controller is interconnected with memory clients and with the
> External Memory Controller. Document new interconnect property which
> turns memory controller into interconnect provider.
>
> Acked-by: Rob Herring
> Signed-o
On Wed, Nov 04, 2020 at 07:48:44PM +0300, Dmitry Osipenko wrote:
> The SoC core voltage can't be changed without taking into account the
> clock rate of External Memory Controller. Document OPP table that will
> be used for dynamic voltage frequency scaling, taking into account EMC
> voltage requir
On Wed, Nov 04, 2020 at 07:48:46PM +0300, Dmitry Osipenko wrote:
> External memory controller is interconnected with memory controller and
> with external memory. Document new interconnect property which turns
> External Memory Controller into interconnect provider.
>
> Acked-by: Rob Herring
> Si
On Wed, Nov 04, 2020 at 07:48:47PM +0300, Dmitry Osipenko wrote:
> Document new OPP table and voltage regulator properties which are needed
> for supporting dynamic voltage-frequency scaling of the memory controller.
> Some boards may have a fixed core voltage regulator, hence it's optional
> becau
On Wed, Nov 04, 2020 at 07:48:48PM +0300, Dmitry Osipenko wrote:
> Memory controller is interconnected with memory clients and with the
> External Memory Controller. Document new interconnect property which
> turns memory controller into interconnect provider.
>
> Signed-off-by: Dmitry Osipenko
>
On Wed, Nov 04, 2020 at 07:48:51PM +0300, Dmitry Osipenko wrote:
> Document EMC DFS OPP table and interconnect paths that will be used
> for scaling of system's memory bandwidth based on memory utilization
> statistics. Previously ACTMON was supposed to drive EMC clock rate
> directly, but now it s
On Wed, Nov 04, 2020 at 07:48:49PM +0300, Dmitry Osipenko wrote:
> External memory controller is interconnected with memory controller and
> with external memory. Document new interconnect property which turns
> External Memory Controller into interconnect provider.
>
> Reviewed-by: Rob Herring
>
On Wed, Nov 04, 2020 at 07:48:52PM +0300, Dmitry Osipenko wrote:
> Most of Host1x devices have at least one memory client. These clients
> are directly connected to the memory controller. The new interconnect
> properties represent the memory client's connection to the memory
> controller.
>
> Rev
On Wed, Nov 04, 2020 at 07:48:50PM +0300, Dmitry Osipenko wrote:
> Document new OPP table and voltage regulator properties which are needed
> for supporting dynamic voltage-frequency scaling of the memory controller.
> Some boards may have a fixed core voltage regulator, hence it's optional
> becau
On Wed, Nov 04, 2020 at 07:48:53PM +0300, Dmitry Osipenko wrote:
> Each memory client has unique hardware ID, add these IDs.
>
> Acked-by: Rob Herring
> Signed-off-by: Dmitry Osipenko
> ---
> include/dt-bindings/memory/tegra20-mc.h | 53 +
> 1 file changed, 53 insertions
On Wed, Nov 04, 2020 at 07:48:54PM +0300, Dmitry Osipenko wrote:
> Each memory client has unique hardware ID, add these IDs.
>
> Acked-by: Rob Herring
> Signed-off-by: Dmitry Osipenko
> ---
> include/dt-bindings/memory/tegra30-mc.h | 67 +
> 1 file changed, 67 insertions
On Wed, Nov 04, 2020 at 07:48:55PM +0300, Dmitry Osipenko wrote:
> Each memory client has unique hardware ID, add these IDs.
>
> Reviewed-by: Rob Herring
> Signed-off-by: Dmitry Osipenko
> ---
> include/dt-bindings/memory/tegra124-mc.h | 68
> 1 file changed, 68 inserti
On Wed, Nov 04, 2020 at 07:49:04PM +0300, Dmitry Osipenko wrote:
> Multiple Tegra drivers need to retrieve Memory Controller and there is
> duplication of the retrieval code among the drivers.
>
> Add new devm_tegra_memory_controller_get() helper to remove the code's
> duplication and to fix put_d
On Wed, Nov 04, 2020 at 07:49:05PM +0300, Dmitry Osipenko wrote:
> Use devm_platform_ioremap_resource() helper which makes code a bit
> cleaner.
>
> Acked-by: Thierry Reding
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/tegra124-emc.c | 4 +---
> drivers/memory/tegra/tegra20-emc
On Wed, Nov 04, 2020 at 07:49:06PM +0300, Dmitry Osipenko wrote:
> The platform_get_irq() prints error message telling that interrupt is
> missing, hence there is no need to duplicated that message in the drivers.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/mc.c | 4
On Wed, Nov 04, 2020 at 07:49:07PM +0300, Dmitry Osipenko wrote:
> Add missing PTC memory client latency allowness entry to the Tegra MC
> drivers.
>
> This prevents erroneous clearing of MC_INTSTATUS 0x0 register during
> of the LA programming in tegra_mc_setup_latency_allowance() due to the
> mi
On Wed, Nov 04, 2020 at 07:49:08PM +0300, Dmitry Osipenko wrote:
> Add common SoC-agnostic ICC framework which turns Tegra Memory Controller
> into a memory interconnection provider. This allows us to use interconnect
> API for tuning of memory configurations.
>
> Tested-by: Peter Geis
> Tested-b
On Wed, Nov 04, 2020 at 07:49:09PM +0300, Dmitry Osipenko wrote:
> Add modularization support to the Tegra20 EMC driver, which now can be
> compiled as a loadable kernel module.
>
> Acked-by: Thierry Reding
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/Kconfig | 2 +-
> d
On Wed, Nov 04, 2020 at 07:49:10PM +0300, Dmitry Osipenko wrote:
> EMC driver will become mandatory after turning it into interconnect
> provider because interconnect users, like display controller driver, will
> fail to probe using newer device-trees that have interconnect properties.
> Thus make
On Wed, Nov 04, 2020 at 07:49:11PM +0300, Dmitry Osipenko wrote:
> Now Internal and External Memory Controllers are memory interconnection
> providers. This allows us to use interconnect API for tuning of memory
> configuration. EMC driver now supports OPPs and DVFS.
>
> Signed-off-by: Dmitry Osip
On Wed, Nov 04, 2020 at 07:49:12PM +0300, Dmitry Osipenko wrote:
> Add devfreq support to the Tegra20 EMC driver. Memory utilization
> statistics will be periodically polled from the memory controller and
> appropriate minimum clock rate will be selected by the devfreq governor.
>
> Signed-off-by:
On Wed, Nov 04, 2020 at 11:36:55AM +0100, Sylwester Nawrocki wrote:
> This patch adds the following properties for Exynos4412 interconnect
> bus nodes:
> - interconnects: to declare connections between nodes in order to
>guarantee PM QoS requirements between nodes,
> - #interconnect-cells: re
On Wed, Nov 04, 2020 at 11:36:56AM +0100, Sylwester Nawrocki wrote:
> From: Artur Świgoń
>
> This patch adds an 'interconnects' property to Exynos4412 DTS in order to
> declare the interconnect path used by the mixer. Please note that the
> 'interconnect-names' property is not needed when there i
On Wed, Nov 11, 2020 at 04:14:40AM +0300, Dmitry Osipenko wrote:
> Factor out clk initialization and make it resource-managed. This makes
> easier to follow code and will help to make further changes cleaner.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/tegra30-emc.c | 70
On Wed, Nov 11, 2020 at 09:51:15AM +0100, Krzysztof Kozlowski wrote:
> On Wed, Nov 11, 2020 at 04:14:40AM +0300, Dmitry Osipenko wrote:
> > Factor out clk initialization and make it resource-managed. This makes
> > easier to follow code and will help to make further
On Wed, Nov 11, 2020 at 04:14:41AM +0300, Dmitry Osipenko wrote:
> Add modularization support to the Tegra124 EMC driver, which now can be
> compiled as a loadable kernel module.
>
> Note that EMC clock must be registered at clk-init time, otherwise PLLM
> will be disabled as unused clock at boot
On Wed, Nov 11, 2020 at 12:17:37PM +0300, Dmitry Osipenko wrote:
> 11.11.2020 12:04, Krzysztof Kozlowski пишет:
> >> -obj-$(CONFIG_TEGRA124_EMC)+= clk-tegra124-emc.o
> >> +obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-emc.o
> >> +obj-$(CONF
| 8 ++++
> 1 file changed, 8 insertions(+)
>
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
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On Wed, Nov 11, 2020 at 04:14:31AM +0300, Dmitry Osipenko wrote:
> Correct typo in a stub of devm_tegra_memory_controller_get() to fix a
> non-ARM kernel compile-testing.
>
> Reported-by: Stephen Rothwell
> Signed-off-by: Dmitry Osipenko
> ---
> include/soc/tegra/mc.h | 2 +-
Thanks, applied.
On Wed, Nov 11, 2020 at 04:14:32AM +0300, Dmitry Osipenko wrote:
> The dev_pm_opp_get_opp_table() shouldn't be used by drivers, use
> dev_pm_opp_set_clkname() instead.
>
> Suggested-by: Viresh Kumar
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/tegra20-emc.c | 30 +++
On Wed, Nov 11, 2020 at 04:14:33AM +0300, Dmitry Osipenko wrote:
> Factor out clk initialization and make it resource-managed. This makes
> easier to follow code and will help to make further changes cleaner.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/tegra20-emc.c | 70
On Wed, Nov 11, 2020 at 04:14:34AM +0300, Dmitry Osipenko wrote:
> Add devfreq support to the Tegra20 EMC driver. Memory utilization
> statistics will be periodically polled from the memory controller and
> appropriate minimum clock rate will be selected by the devfreq governor.
>
> Signed-off-by:
On Wed, Nov 11, 2020 at 04:14:35AM +0300, Dmitry Osipenko wrote:
> Remove IRQ number from error message since it doesn't add any useful
> information, especially because this number is virtual.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/tegra20-emc.c | 2 +-
> 1 file changed
On Wed, Nov 11, 2020 at 04:14:36AM +0300, Dmitry Osipenko wrote:
> The latency allowness is calculated based on buffering capabilities of
> memory clients. Add FIFO sizes to the Tegra30 memory clients.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/tegra30.c | 66 +++
On Wed, Nov 11, 2020 at 04:14:37AM +0300, Dmitry Osipenko wrote:
> Add modularization support to the Tegra30 EMC driver, which now can be
> compiled as a loadable kernel module.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/Kconfig | 2 +-
> drivers/memory/tegra/mc.c
On Wed, Nov 11, 2020 at 04:14:38AM +0300, Dmitry Osipenko wrote:
> EMC driver will become mandatory after turning it into interconnect
> provider because interconnect users, like display controller driver, will
> fail to probe using newer device-trees that have interconnect properties.
> Thus make
fined reference to `clk_set_parent'
Reported-by: kernel test robot
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/exynos/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 6417f374b923..951d5f708
.text+0x1600): undefined reference to `clk_get_parent'
/usr/bin/mips-linux-gnu-ld: ingenic-drm-drv.c:(.text+0x16b0): undefined
reference to `clk_get_parent'
Reported-by: kernel test robot
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/ingenic/Kconfig | 1 +
1 file changed, 1 ins
fined reference to `clk_set_parent'
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/imx/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 6231048aa5aa..65f9ef625337 100644
--- a/drivers/gpu/drm/i
On Tue, 17 Nov 2020 at 11:56, Philipp Zabel wrote:
>
> On Mon, 2020-11-16 at 19:14 +0100, Krzysztof Kozlowski wrote:
> > The iMX DRM drivers use Common Clock Framework thus they cannot be built
> > on platforms without it (e.g. compile test on MIPS with RALINK
fined reference to `clk_set_parent'
Signed-off-by: Krzysztof Kozlowski
---
Changes since v1:
1. Put depends in DRM_IMX_LDB option only.
---
drivers/gpu/drm/imx/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 62
l | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 09/03/2022 16:11, Biju Das wrote:
> On Renesas RZ/{G2L,V2L} platforms changing the lanes from 4 to 3 at
> lower frequencies causes display instability. On such platforms, it
> is better to avoid switching lanes from 4 to 3 as it needs different
> set of PLL parameter constraints to make the disp
On 13/03/2022 13:38, Marek Vasut wrote:
> The i.MX8MP contains two syscon registers which are responsible
> for configuring the on-SoC DPI-to-LVDS serializer. Add DT binding
> which represents this serializer as a bridge.
>
> Signed-off-by: Marek Vasut
> Cc: Laurent Pinchart
> Cc: Lucas Stach
>
On 13/03/2022 18:09, Marek Vasut wrote:
> On 3/13/22 16:47, Krzysztof Kozlowski wrote:
>
> Hi,
>
> [...]
>
>>> diff --git a/Documentation/devicetree/bindings/display/bridge/nxp,ldb.yaml
>>> b/Documentation/devicetree/bindings/display/bridge/nxp,ldb.yam
On 14/03/2022 10:00, Rex-BC Chen wrote:
> Add aal binding for MT8183.
>
> Signed-off-by: Rex-BC Chen
> Acked-by: Rob Herring
> ---
> .../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git
> a/Documentation/devicetree/bindings/d
On 16/03/2022 12:51, Rex-BC Chen wrote:
> Add aal binding for MT8183.
>
> Signed-off-by: Rex-BC Chen
> ---
> .../devicetree/bindings/display/mediatek/mediatek,aal.yaml| 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git
> a/Documentation/devicetree/bindings/display/med
On 17/03/2022 06:18, Rex-BC Chen wrote:
> Add aal binding for MT8183.
>
> Signed-off-by: Rex-BC Chen
> ---
> .../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
uot;;
> +compatible = "qcom,qcm2290-mdss";
That's quite unfortunate choice of compatibles. I would assume qcom,mdss
is a generic fallback compatible but it is used in different way - as a
specific compatible for MDP v5. The bindings here are for a newer
device, right?
It's already in the bindings, so not much could be fixed now...
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 25/03/2022 18:14, Guillaume Ranquet wrote:
> From: Markus Schneider-Pargmann
>
> DP_INTF is similar to DPI but does not have the exact same feature set
> or register layouts.
>
> DP_INTF is the sink of the display pipeline that is connected to the
> DisplayPort controller and encoder unit. It
On 25/03/2022 18:14, Guillaume Ranquet wrote:
> This phy controller is embedded in the Display Port Controller on mt8195 SoCs.
>
> Signed-off-by: Guillaume Ranquet
> ---
> .../bindings/phy/mediatek,dp-phy.yaml | 43 +++
> 1 file changed, 43 insertions(+)
> create mode 10
On 25/03/2022 18:14, Guillaume Ranquet wrote:
> From: Markus Schneider-Pargmann
>
> This controller is present on several mediatek hardware. Currently
> mt8195 and mt8395 have this controller without a functional difference,
> so only one compatible field is added.
>
> The controller can have tw
On 25/03/2022 18:43, Guillaume Ranquet wrote:
> On Fri, 25 Mar 2022 18:31, Krzysztof Kozlowski wrote:
>> On 25/03/2022 18:14, Guillaume Ranquet wrote:
>>> From: Markus Schneider-Pargmann
>>>
>>> DP_INTF is similar to DPI but does not have the exact same
On 28/03/2022 19:16, Vinod Koul wrote:
> On 28-03-22, 19:43, Dmitry Baryshkov wrote:
>> On Mon, 28 Mar 2022 at 18:30, Krzysztof Kozlowski
>> wrote:
>>>
>>> The DSI node is not a bus and the children do not have unit addresses.
>>>
>>> Re
The DSI node is not a bus and the children do not have unit addresses.
Reported-by: Vinod Koul
Signed-off-by: Krzysztof Kozlowski
---
.../bindings/display/msm/dsi-controller-main.yaml | 7 ---
1 file changed, 7 deletions(-)
diff --git
a/Documentation/devicetree/bindings/display
On 28/03/2022 17:29, Krzysztof Kozlowski wrote:
> The DSI node is not a bus and the children do not have unit addresses.
Eh, actually MIPI DSI is a serial bus, so address/size cells seem right
and my patch is not correct.
>
> Reported-by: Vinod Koul
> Signed-off-by: Krzyszt
On 28/03/2022 18:43, Dmitry Baryshkov wrote:
> On Mon, 28 Mar 2022 at 18:30, Krzysztof Kozlowski
> wrote:
>>
>> The DSI node is not a bus and the children do not have unit addresses.
>>
>> Reported-by: Vinod Koul
>> Signed-off-by: Krzysztof Kozlowski
>
des should be a separate patch,
>> fix a warnning because of that.
>>
>> v3: split dt-bindings from other changes into a separate patch.
>>
>> v4: fix warnings and errors when running make dt_binding_check
>>
>> Reported-by: Rob Herring
>> Reported-by:
ver to know which chip the DC is contained
>>in, the compatible string of the display controller is updated
>>according to the chip's name.
>>
>> 2) Add display controller device node for ls2k1000 SoC
>>
>> Reported-by: Krzysztof Kozlowski
>> Signed
quot;Thomas Zimmermann"
> , "Roland Scheidegger" , "Zack
> Rusin" , "Christian Gmeiner" ,
> "David Airlie" , "Daniel Vetter" , "Thomas
> Bogendoerfer" , "Dan Carpenter"
> , "Krzysztof Kozlowski" , &qu
On 23/02/2022 16:35, Sui Jingfeng wrote:
>
> On 2022/2/23 21:56, 隋景峰 wrote:
>> Something like this:
>>
>> dt-bindings: display: Add Loongson display controller
>
> Hi,
Thanks for resending in a proper format. I already replied to your
original post, so let me paste it here as well.
>
> We a
On 02/03/2022 02:00, Inki Dae wrote:
> Hi Krzysztof,
>
> 22. 2. 7. 01:51에 Krzysztof Kozlowski 이(가) 쓴 글:
>> On 25/03/2019 08:13, Andrzej Hajda wrote:
>>> GSCALERs in Exynos5433 have local path to DECON and DECON_TV.
>>> They can be used as extra planes wit
On 03/03/2022 17:11, Marek Szyprowski wrote:
> Hi Krzysztof,
>
> On 03.03.2022 17:03, Krzysztof Kozlowski wrote:
>> On 02/03/2022 02:00, Inki Dae wrote:
>>> 22. 2. 7. 01:51에 Krzysztof Kozlowski 이(가) 쓴 글:
>>>> On 25/03/2019 08:13, Andrzej Hajda wrote:
>>
On 04/03/2022 01:03, Joel Stanley wrote:
> Convert the bindings to yaml and add the ast2600 compatible string.
>
> The legacy mfd description was put in place before the gfx bindings
> existed, to document the compatible that is used in the pinctrl
> bindings.
>
> Signed-off-by: Joel Stanley
> -
The MODULE_DEVICE_TABLE already creates proper alias for platform
driver. Having another MODULE_ALIAS causes the alias to be duplicated.
Signed-off-by: Krzysztof Kozlowski
---
drivers/video/fbdev/s3c-fb.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/video/fbdev/s3c-fb.c b/drivers
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