Hi Rob,
On 07/11/2017 11:50 PM, Rob Clark wrote:
> The goal here is to support inheriting a display setup by bootloader,
> although there may also be some non-display related use-cases.
>
> Rough idea is to add a flag for clks and power domains that might
> already be enabled when kernel starts,
On 07/04/2017 11:21 PM, Rob Clark wrote:
> The goal here is to support inheriting a display setup by bootloader,
> although there may also be some non-display related use-cases.
>
> Rough idea is to add a flag for clks and power domains that might
> already be enabled when kernel starts, and
Hey Jordan/Viresh,
On 03/09/2018 09:13 AM, Viresh Kumar wrote:
> On 08-03-18, 13:14, Jordan Crouse wrote:
>> It seems to me that performance_state has a direct relationship with genpd
>> which is good for CPU votes but in this case, we're just passing along raw
>> data
>> to an independent
On 11/2/2018 6:19 PM, Jayant Shekhar wrote:
In case of msm drm bind failure, dpu_mdss_destroy is triggered.
In this function, resources are freed and pm runtime disable is
called, which triggers dpu_mdss_disable. Now in dpu_mdss_disable,
driver tries to access a memory which is already freed.
On 12/29/2018 6:59 AM, Stephen Boyd wrote:
So I am guessing the conclusion is to use a fallback "operating-points-v2"
compatible*only* when we do have opp-hz along with qcom,level (as in the
case with gpu) and not have a fallback compatible in cases when we don't
have opp-hz (as in the case of
On 12/21/2018 2:59 AM, Stephen Boyd wrote:
Quoting Rob Herring (2018-12-19 15:47:25)
On Wed, Dec 19, 2018 at 4:40 PM Doug Anderson wrote:
On Wed, Dec 19, 2018 at 12:40 PM Doug Anderson wrote:
On Wed, Dec 19, 2018 at 12:09 PM Rob Herring wrote:
...but it does have a frequency, doesn't it?
.
Tested-by: Rajendra Nayak
---
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index fd9c893..df8127b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1
On 1/9/2019 10:50 AM, Doug Anderson wrote:
...but in the meantime Rajendra has had to change his bindings, so you
still need to spin this to account for Rajendra's v9 bindings [2].
Specifically you need to make changes like:
- compatible =
On some qualcomm platforms DPU needs to express a perforamnce state
requirement on a power domain depennding on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
---
drivers/gpu/drm/msm
Add the OPP tables for DSI and MDP based on the perf state/clk
requirements, and add the power-domains property to specify the
scalable power domain.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 59
1 file changed, 59 insertions(+)
diff
geni spi needs to express a perforamnce state requirement on CX
depending on the frequency of the clock rates. Use OPP table from
DT to register with OPP framework and use dev_pm_opp_set_rate() to
set the clk/perf state.
Signed-off-by: Rajendra Nayak
Signed-off-by: Stephen Boyd
---
drivers/spi
Some UFS devices need to manage multiple powerdomains. Add support for
it as part of the ufshcd-pltfrm driver.
Signed-off-by: Rajendra Nayak
---
drivers/scsi/ufs/ufshcd-pltfrm.c | 52 +++-
drivers/scsi/ufs/ufshcd.h| 3 ++
2 files changed, 54 insertions(+), 1
qup has a requirement to vote on the performance state of the CX domain
in sdm845 devices. Add OPP tables for these and also add power-domains
property for all qup instances.
Signed-off-by: Rajendra Nayak
Signed-off-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 115
On SDM845 DSI needs to express a perforamnce state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
---
drivers/gpu/drm/msm/dsi/dsi.h | 2
-by: Rajendra Nayak
---
drivers/scsi/ufs/ufshcd.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index ffa9e58680b4..2b260e83874a 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
Add the additional power domain and the OPP table for ufs on sdm845
so the driver can set the appropriate performance state of the
power domain while setting the clock rate.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 20 +++-
1 file changed, 19
geni serial needs to express a perforamnce state requirement on CX
depending on the frequency of the clock rates. Use OPP table from
DT to register with OPP framework and use dev_pm_opp_set_rate() to
set the clk/perf state.
Signed-off-by: Rajendra Nayak
Signed-off-by: Stephen Boyd
---
drivers
-by: Rajendra Nayak
Signed-off-by: Stephen Boyd
---
drivers/opp/core.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index bc9a7762dd4c..d6acc880676e 100644
--- a/drivers/opp/core.c
+++ b/drivers/opp/core.c
@@ -708,18
] https://lkml.org/lkml/2019/1/28/2086
[2] https://lkml.org/lkml/2019/3/8/70
[3] https://lkml.org/lkml/2019/3/20/120
Rajendra Nayak (10):
OPP: Make dev_pm_opp_set_rate() with freq=0 as valid
tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state
spi: spi-geni-qcom: Use OPP API to set clk
a property like 'opp-use-clk' to
tell the table that it should use the clk APIs to round rates instead of
OPP?
Signed-off-by: Stephen Boyd
Signed-off-by: Rajendra Nayak
---
drivers/opp/core.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/opp/core.c b/drivers/opp
On 6/11/2019 4:24 PM, Viresh Kumar wrote:
On 20-03-19, 15:19, Rajendra Nayak wrote:
From: Stephen Boyd
Doing this allows us to call this API with any rate requested and have
it not need to match in the OPP table. Instead, we'll round the rate up
to the nearest OPP that we see so that we can
calling the
API?
Signed-off-by: Stephen Boyd
Signed-off-by: Rajendra Nayak
[ Viresh: Massaged changelog and use temp_opp variable instead ]
Signed-off-by: Viresh Kumar
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum
On 6/17/2019 9:47 AM, Viresh Kumar wrote:
On 17-06-19, 09:37, Rajendra Nayak wrote:
On 6/17/2019 9:20 AM, Viresh Kumar wrote:
On 14-06-19, 10:57, Viresh Kumar wrote:
Hmm, so this patch won't break anything and I am inclined to apply it again :)
Does anyone see any other issues
On 6/14/2019 12:02 PM, Viresh Kumar wrote:
On 20-03-19, 15:19, Rajendra Nayak wrote:
For devices with performance state, we use dev_pm_opp_set_rate()
to set the appropriate clk rate and the performance state.
We do need a way to *remove* the performance state vote when
we idle the device
Now, the request to change the frequency starts from cpufreq
governors, like schedutil when they calls:
__cpufreq_driver_target(policy, 599 MHz, CPUFREQ_RELATION_L);
CPUFREQ_RELATION_L means: lowest frequency at or above target. And so
I would expect the frequency to get set to 600MHz (if we
On 5/21/2019 11:52 AM, Viresh Kumar wrote:
On 20-03-19, 15:19, Rajendra Nayak wrote:
This is a v2 of the RFC posted earlier by Stephen Boyd [1]
As part of v2 I still follow the same approach of dev_pm_opp_set_rate()
API using clk framework to round the frequency passed and making it
accept 0
On 4/17/2020 11:47 PM, Matthias Kaehlcke wrote:
Hi Rajendra,
I have essentially the same comments as for "tty: serial: qcom_geni_serial:
Use OPP API to set clk/perf state"
(https://patchwork.kernel.org/patch/11495209/).
about error handling of 'dev_pm_opp_of_add_table' and misleading struct
On SDM845 DSI needs to express a perforamnce state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Cc: Rob Clark
Cc: Sean Paul
Cc: dri-devel
On some qualcomm platforms DPU needs to express a perforamnce state
requirement on a power domain depennding on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Cc: Rob Clark
Cc: Sean
On some qualcomm platforms DPU needs to express a perforamnce state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Cc: Rob Clark
Cc: Sean Paul
On SDM845 DSI needs to express a perforamnce state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Cc: Rob Clark
Cc: Sean Paul
Cc: dri-devel
On SDM845 DSI needs to express a perforamnce state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Cc: Rob Clark
Cc: Sean Paul
Cc: dri-devel
On some qualcomm platforms DPU needs to express a perforamnce state
requirement on a power domain depennding on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Cc: Rob Clark
Cc: Sean
On 4/29/2020 5:44 AM, Matthias Kaehlcke wrote:
On Tue, Apr 28, 2020 at 07:02:53PM +0530, Rajendra Nayak wrote:
On some qualcomm platforms DPU needs to express a perforamnce state
requirement on a power domain depennding on the clock rates.
Use OPP table from DT to register with OPP framework
On 4/28/2020 10:02 PM, Rob Clark wrote:
On Tue, Apr 28, 2020 at 6:39 AM Rajendra Nayak wrote:
On some qualcomm platforms DPU needs to express a perforamnce state
s/perforamnce/performance/
requirement on a power domain depennding on the clock rates.
s/depennding/depending/
Use OPP
On SDM845 DSI needs to express a perforamnce state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Cc: Rob Clark
Cc: Sean Paul
Cc: dri-devel
On some qualcomm platforms DPU needs to express a performance state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Reviewed-by: Rob Clark
On some qualcomm platforms DPU needs to express a performance state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Reviewed-by: Rob Clark
On SDM845 DSI needs to express a perforamnce state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Cc: Rob Clark
Cc: Sean Paul
Cc: dri-devel
On 8/28/2020 11:37 AM, Viresh Kumar wrote:
dev_pm_opp_of_remove_table() doesn't report any errors when it fails to
find the OPP table with error -ENODEV (i.e. OPP table not present for
the device). And we can call dev_pm_opp_of_remove_table()
unconditionally here.
Its a little tricky to call
On 9/1/2020 2:08 PM, Viresh Kumar wrote:
On 01-09-20, 13:01, Rajendra Nayak wrote:
So FWIU, dpu_unbind() gets called even when dpu_bind() fails for some reason.
Ahh, I see.
I tried to address that earlier [1] which I realized did not land.
I don't think that patch was required, as you
On 10/4/2020 3:56 AM, Kuogee Hsieh wrote:
Set link rate by using OPP set rate api so that CX level will be set
accordingly based on the link rate.
Changes in v2:
-- remove dev from dp_ctrl_put() parameters
-- address review comments
This needs to go below '---' and should not be part of the
On 9/30/2020 1:54 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2020-09-29 10:10:26)
Set link rate by using OPP set rate api so that CX level will be set
accordingly base on the link rate.
s/base/based/
Signed-off-by: Kuogee Hsieh
---
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c
On 8/12/2020 1:09 PM, Rajendra Nayak wrote:
On 8/12/2020 1:05 PM, Amit Pundir wrote:
Hi Rajendra,
On Wed, 12 Aug 2020 at 11:18, Rajendra Nayak wrote:
On 8/12/2020 7:03 AM, John Stultz wrote:
On Tue, Aug 11, 2020 at 4:11 PM John Stultz wrote:
On Wed, Mar 20, 2019 at 2:49 AM Rajendra
On 8/12/2020 1:05 PM, Amit Pundir wrote:
Hi Rajendra,
On Wed, 12 Aug 2020 at 11:18, Rajendra Nayak wrote:
On 8/12/2020 7:03 AM, John Stultz wrote:
On Tue, Aug 11, 2020 at 4:11 PM John Stultz wrote:
On Wed, Mar 20, 2019 at 2:49 AM Rajendra Nayak wrote:
geni serial needs to express
On 8/12/2020 7:03 AM, John Stultz wrote:
On Tue, Aug 11, 2020 at 4:11 PM John Stultz wrote:
On Wed, Mar 20, 2019 at 2:49 AM Rajendra Nayak wrote:
geni serial needs to express a perforamnce state requirement on CX
depending on the frequency of the clock rates. Use OPP table from
DT
On SDM845 DSI needs to express a perforamnce state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
---
drivers/gpu/drm/msm/dsi/dsi.h | 2
.
These patches have no other dependency and will need to be merged in
via the MSM DRM tree.
DT patches will need to land via the msm tree.
[1] https://lkml.org/lkml/2020/6/15/535
Rajendra Nayak (4):
drm/msm/dpu: Use OPP API to set clk/perf state
drm/msm: dsi: Use OPP API to set clk/perf
On some qualcomm platforms DPU needs to express a performance state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Reviewed-by: Rob Clark
Add the OPP tables for DSI and MDP based on the perf state/clk
requirements, and add the power-domains property to specify the
scalable power domain.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 49
1 file changed, 49 insertions
Add the OPP tables for DSI and MDP based on the perf state/clk
requirements, and add the power-domains property to specify the
scalable power domain.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 59
1 file changed, 59 insertions
On some qualcomm platforms DPU needs to express a performance state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Reviewed-by: Rob Clark
to clk_set_rate()
for devices without an OPP table, hence the change works fine
on devices/platforms which only need to set a clock rate.
Signed-off-by: Rajendra Nayak
Reviewed-by: Matthias Kaehlcke
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 27 +--
1 file changed, 25 insertions(+), 2
to be merged in
via the MSM DRM tree.
DT patches will need to land via the msm tree.
Rajendra Nayak (4):
drm/msm/dpu: Use OPP API to set clk/perf state
drm/msm: dsi: Use OPP API to set clk/perf state
arm64: dts: sdm845: Add DSI and MDP OPP tables and power-domains
arm64: dts: sc7180: Add
Add the OPP tables for DSI and MDP based on the perf state/clk
requirements, and add the power-domains property to specify the
scalable power domain.
Signed-off-by: Rajendra Nayak
Reviewed-by: Matthias Kaehlcke
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 59
Add the OPP tables for DSI and MDP based on the perf state/clk
requirements, and add the power-domains property to specify the
scalable power domain.
Signed-off-by: Rajendra Nayak
Reviewed-by: Matthias Kaehlcke
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 49
Add the OPP tables for DSI and MDP based on the perf state/clk
requirements, and add the power-domains property to specify the
scalable power domain.
Signed-off-by: Rajendra Nayak
Reviewed-by: Matthias Kaehlcke
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 59
to clk_set_rate()
for devices without an OPP table, hence the change works fine
on devices/platforms which only need to set a clock rate.
Signed-off-by: Rajendra Nayak
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers
to land via the msm tree.
Rajendra Nayak (4):
drm/msm/dpu: Use OPP API to set clk/perf state
drm/msm: dsi: Use OPP API to set clk/perf state
arm64: dts: sdm845: Add DSI and MDP OPP tables and power-domains
arm64: dts: sc7180: Add DSI and MDP OPP tables and power-domains
arch/arm64/boot/dts/qcom
On some qualcomm platforms DPU needs to express a performance state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Reviewed-by: Rob Clark
Add the OPP tables for DSI and MDP based on the perf state/clk
requirements, and add the power-domains property to specify the
scalable power domain.
Signed-off-by: Rajendra Nayak
Reviewed-by: Matthias Kaehlcke
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 49
On 7/1/2020 9:57 PM, Matthias Kaehlcke wrote:
On Tue, Jun 30, 2020 at 05:26:14PM +0530, Rajendra Nayak wrote:
On SDM845 DSI needs to express a perforamnce state
nit: performance
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP
On SDM845 DSI needs to express a perforamnce state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Cc: Rob Clark
Cc: Sean Paul
Cc: dri-devel
On some qualcomm platforms DPU needs to express a performance state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak
Reviewed-by: Rob Clark
: aa3950767d05 ("drm/msm/dpu: Use OPP API to set clk/perf state")
Signed-off-by: Rajendra Nayak
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_k
exists.
Fixes: f99131fa7a23 ("drm/msm: dsi: Use OPP API to set clk/perf state")
Reported-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
On 7/6/2020 9:40 PM, Matthias Kaehlcke wrote:
On Thu, Jul 02, 2020 at 04:39:09PM +0530, Rajendra Nayak wrote:
On SDM845 and SC7180 DSI needs to express a performance state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
On 7/19/2022 12:49 PM, Stephen Boyd wrote:
Quoting Akhil P Oommen (2022-07-18 23:37:16)
On 7/19/2022 11:19 AM, Stephen Boyd wrote:
Quoting Akhil P Oommen (2022-07-18 21:07:05)
On 7/14/2022 11:10 AM, Akhil P Oommen wrote:
IIUC, qcom gdsc driver doesn't ensure hardware is collapsed since
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