te email
address, but it's kind of hard to tell because you haven't been using
at least the same name in both email addresses.
However, if you're forwarding this patch on behalf of somebody else you
need to add your own Signed-off-by: line.
Reviewed-
6:
> WARNING: use scnprintf or sprintf
>
> Signed-off-by: Xuezhi Zhang
> ---
> drivers/gpu/drm/panel/panel-tpo-td043mtea1.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Thierry Reding
signature.asc
Description: PGP signature
_
On Tue, Apr 06, 2021 at 03:43:56PM +0200, Uwe Kleine-König wrote:
> Hello Thierry,
>
> On Tue, Apr 06, 2021 at 01:16:31PM +0200, Thierry Reding wrote:
> > On Tue, Apr 06, 2021 at 09:30:36AM +0200, Uwe Kleine-König wrote:
> > > Given that lowlevel drivers usually cannot
to allow userspace to rely on this. Again don't backport
> further than where Paul's patch got added.
>
> Cc: sta...@vger.kernel.org # v5.1 +
> Cc: Pekka Paalanen
> Signed-off-by: Daniel Vetter
> Cc: Thierry Reding
> Cc: Jonathan Hunter
> Cc: linux-te...@vger.k
On Fri, Feb 19, 2021 at 04:52:59PM -0500, Lyude Paul wrote:
> As pointed out by the documentation for drm_dp_aux_register(),
> drm_dp_aux_init() should be used in situations where the AUX channel for a
> display driver can potentially be registered before it's respective DRM
> driver. This is the c
On Thu, Apr 15, 2021 at 08:29:14AM -0700, Nathan Chancellor wrote:
> Clang warns:
>
> drivers/gpu/drm/tegra/hub.c:513:11: warning: shift count >= width of
> type [-Wshift-count-overflow]
> base |= BIT(39);
> ^~~
>
> BIT is unsigned long, which is 32-bit
On Thu, Apr 22, 2021 at 03:08:48PM -0700, Doug Anderson wrote:
> Hi,
>
> On Mon, Mar 29, 2021 at 9:25 AM Doug Anderson wrote:
> >
> > Hi,
> >
> > On Thu, Mar 25, 2021 at 5:09 PM Rob Herring wrote:
> > >
> > > On Tue, Mar 16, 2021 at 02:08:19PM -0700, Douglas Anderson wrote:
> > > > The sc7180-tr
On Thu, Apr 22, 2021 at 01:18:09PM -0400, Lyude Paul wrote:
> On Tue, 2021-04-20 at 02:16 +0300, Ville Syrjälä wrote:
> >
> > The init vs. register split is intentional. Registering the thing
> > and allowing userspace access to it before the rest of the driver
> > is ready isn't particularly grea
On Thu, Apr 22, 2021 at 06:33:44PM -0400, Lyude Paul wrote:
> OK - talked with Ville a bit on this and did some of my own research, I
> actually think that moving i2c to drm_dp_aux_init() is the right decision for
> the time being. The reasoning behind this being that as shown by my previous
> work
On Fri, Apr 23, 2021 at 12:11:06AM -0400, Lyude Paul wrote:
> On Thu, 2021-04-22 at 18:33 -0400, Lyude Paul wrote:
> > OK - talked with Ville a bit on this and did some of my own research, I
> > actually think that moving i2c to drm_dp_aux_init() is the right decision
> > for
> > the time being. Th
d-off-by: Lyude Paul
> Fixes: 39c17ae60ea9 ("drm/tegra: Don't register DP AUX channels before
> connectors")
> Cc: Lyude Paul
> Cc: Thierry Reding
> Cc: Jonathan Hunter
> Cc: dri-devel@lists.freedesktop.org
> Cc: linux-te...@vger.kernel.org
> ---
> dr
a210-nvdec.yaml#";
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#";
> +
> +title: Device tree binding for NVIDIA Tegra NVDEC
> +
> +description: |
> + NVDEC is the hardware video decoder present on NVIDIA Tegra210
> + and newer chips. It
On Tue, Aug 10, 2021 at 05:43:26PM +0200, Thierry Reding wrote:
> On Fri, Aug 06, 2021 at 03:34:48PM +0300, Mikko Perttunen wrote:
[...]
> > diff --git
> > a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
> > b/Documentation/devicetree/bindings/gpu/h
On Fri, Aug 06, 2021 at 03:34:50PM +0300, Mikko Perttunen wrote:
> Add support for booting and using NVDEC on Tegra210, Tegra186
> and Tegra194 to the Host1x and TegraDRM drivers. Booting in
> secure mode is not currently supported.
>
> Signed-off-by: Mikko Perttunen
> ---
> v2:
> * Use devm_plat
On Tue, Aug 10, 2021 at 06:50:26PM +0300, Mikko Perttunen wrote:
> On 10.8.2021 18.43, Thierry Reding wrote:
> > On Fri, Aug 06, 2021 at 03:34:48PM +0300, Mikko Perttunen wrote:
> > > Convert the original Host1x bindings to YAML and add new bindings for
> > > NVDEC
; > happens due to insufficient memory bandwidth.
> >
> > Changelog:
> >
> > v18: - Moved total peak bandwidth from CRTC state to plane state and removed
> >dummy plane bandwidth state initialization from T186+ plane hub. This
> >was suggested by Thier
drm/tegra: Implement new UAPI
drm/tegra: Implement syncpoint management UAPI
drm/tegra: Implement syncpoint wait UAPI
drm/tegra: Implement job submission part of new UAPI
drm/tegra: Add job firewall
drm/tegra: Bump driver version
Thierry Reding (3):
g
On Thu, Jun 10, 2021 at 01:12:34PM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> When working with framebuffer modifiers, it can be useful to extract the
> vendor identifier or check a modifier against a given vendor identifier.
> Add one macro that extracts the vendor i
On Tue, Aug 17, 2021 at 02:04:38PM +0200, Ulf Hansson wrote:
> On Tue, 17 Aug 2021 at 03:30, Dmitry Osipenko wrote:
> >
> > Add runtime PM and OPP support to the Host1x driver. It's required for
> > enabling system-wide DVFS and supporting dynamic power management using
> > a generic power domain.
On Tue, Aug 17, 2021 at 05:01:50AM +0300, Dmitry Osipenko wrote:
> Fix troubles introduced by recent commits.
>
> Dmitry Osipenko (3):
> drm/tegra: dc: Remove unused variables
> drm/tegra: uapi: Fix wrong mapping end address in case of disabled
> IOMMU
> gpu/host1x: fence: Make spinlock
On Tue, Aug 17, 2021 at 10:32:01AM +0200, Nikola Pavlica wrote:
> The model and make of the LCD panel of the Vivax TPC-9150 is unknown,
> hence the panel settings that were retrieved with a FEX dump are named
> after the device NOT the actual panel.
>
> The LCD in question is a 50 pin MISO TFT LCD
re.yaml#";
> > > +
> > > +title: Device tree binding for NVIDIA Tegra NVDEC
> > > +
> > > +description: |
> > > + NVDEC is the hardware video decoder present on NVIDIA Tegra210
> > > + and newer chips. It is located on the Host1x bus and t
On Wed, Aug 18, 2021 at 04:44:30AM +0300, Dmitry Osipenko wrote:
> 18.08.2021 04:15, Rob Herring пишет:
> >> + tegra-clocks:
> >> +description: child nodes are the output clocks from the CAR
> >> +type: object
> >> +
> >> +patternProperties:
> >> + "^[a-z]+[0-9]+$":
> >> +
On Tue, Aug 17, 2021 at 04:27:26AM +0300, Dmitry Osipenko wrote:
> Document tegra-clocks sub-node which describes Tegra SoC clocks that
> require a higher voltage of the core power domain in order to operate
> properly on a higher clock rates. Each node contains a phandle to OPP
> table and power
On Tue, Aug 17, 2021 at 04:27:27AM +0300, Dmitry Osipenko wrote:
[...]
> +struct clk *tegra_clk_register(struct clk_hw *hw)
> +{
> + struct platform_device *pdev;
> + struct device *dev = NULL;
> + struct device_node *np;
> + const char *dev_name;
> +
> + np = tegra_clk_get_of_n
On Wed, Aug 18, 2021 at 06:05:11PM +0300, Dmitry Osipenko wrote:
> 18.08.2021 16:59, Thierry Reding пишет:
> > On Tue, Aug 17, 2021 at 04:27:26AM +0300, Dmitry Osipenko wrote:
> >> Document tegra-clocks sub-node which describes Tegra SoC clocks that
> >> require a highe
On Wed, Aug 18, 2021 at 06:05:21PM +0300, Dmitry Osipenko wrote:
> 18.08.2021 17:07, Thierry Reding пишет:
> > On Tue, Aug 17, 2021 at 04:27:27AM +0300, Dmitry Osipenko wrote:
> > [...]
> >> +struct clk *tegra_clk_register(struct clk_hw *hw)
> >> +{
>
On Tue, Aug 17, 2021 at 04:27:39AM +0300, Dmitry Osipenko wrote:
> The PWM on Tegra belongs to the core power domain and we're going to
> enable GENPD support for the core domain. Now PWM must be resumed using
> runtime PM API in order to initialize the PWM power state. The PWM clock
> rate must be
On Thu, Aug 19, 2021 at 04:04:50PM +0200, Ulf Hansson wrote:
> On Thu, 19 Aug 2021 at 15:21, Thierry Reding wrote:
> >
> > On Tue, Aug 17, 2021 at 04:27:39AM +0300, Dmitry Osipenko wrote:
> > > The PWM on Tegra belongs to the core power domain and we're going to
>
On Wed, Aug 18, 2021 at 07:57:04PM +0300, Dmitry Osipenko wrote:
> 18.08.2021 19:39, Thierry Reding пишет:
> >> We don't have a platform device for CaR. I don't see how it's going to
> >> work. We need to create a platform device for each RPM-capable clock
&g
On Wed, Aug 18, 2021 at 08:11:03PM +0300, Dmitry Osipenko wrote:
> 18.08.2021 19:42, Thierry Reding пишет:
> > On Wed, Aug 18, 2021 at 06:05:21PM +0300, Dmitry Osipenko wrote:
> >> 18.08.2021 17:07, Thierry Reding пишет:
> >>> On Tue, Aug 17, 2021 at 04:27:27A
On Tue, Aug 17, 2021 at 04:27:40AM +0300, Dmitry Osipenko wrote:
> The SDHCI on Tegra belongs to the core power domain and we're going to
> enable GENPD support for the core domain. Now SDHCI must be resumed using
> runtime PM API in order to initialize the SDHCI power state. The SDHCI
> clock rate
On Fri, Aug 20, 2021 at 01:37:13AM +0300, Dmitry Osipenko wrote:
> 19.08.2021 20:03, Thierry Reding пишет:
> > On Tue, Aug 17, 2021 at 04:27:40AM +0300, Dmitry Osipenko wrote:
> >> The SDHCI on Tegra belongs to the core power domain and we're going to
> >> enable G
On Fri, Aug 20, 2021 at 01:09:46AM +0300, Dmitry Osipenko wrote:
> 19.08.2021 19:54, Thierry Reding пишет:
> > On Wed, Aug 18, 2021 at 08:11:03PM +0300, Dmitry Osipenko wrote:
> >> 18.08.2021 19:42, Thierry Reding пишет:
> >>> On Wed, Aug 18, 2021 at 06:05:21P
On Sat, Aug 21, 2021 at 08:45:54PM +0300, Dmitry Osipenko wrote:
> 20.08.2021 16:08, Ulf Hansson пишет:
> ...
> >> I suppose if there's really no good way of doing this other than
> >> providing a struct device, then so be it. I think the cleaned up sysfs
> >> shown in the summary above looks much
From: Thierry Reding
Hi all,
this is the userspace part of the kernel patches that were recently
merged into drm-next:
https://patchwork.freedesktop.org/series/92378/
The goal is to provide a userspace implementation of the UAPI exposed by
the kernel and show its usage in some test programs
From: Thierry Reding
Reindent the sources according to the settings found in the newly added
.editorconfig.
Signed-off-by: Thierry Reding
---
tegra/private.h | 18 +-
tegra/tegra.c | 354
tegra/tegra.h | 12 +-
tests/tegra
From: Thierry Reding
Store 64-bit offset values and use libdrm's built-in drm_mmap() function
instead of mmap() to ensure the full 64-bit offset is used.
Signed-off-by: Thierry Reding
---
tegra/private.h | 2 +-
tegra/tegra.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
From: Thierry Reding
The DRM_TEGRA_GEM_{GET,SET}_FLAGS and DRM_TEGRA_GEM_{GET,SET}_TILING
IOCTLs were badly designed and have since been obsoleted by framebuffer
modifiers. Remove these implementations to make it clear their usage is
discouraged.
Signed-off-by: Thierry Reding
---
tegra/tegra
From: Thierry Reding
All of the buffer object allocation functions use the same boilerplate
code. Move that code into a separate function that can be reused.
Signed-off-by: Thierry Reding
---
tegra/tegra.c | 35 ++-
1 file changed, 22 insertions(+), 13
From: Thierry Reding
Most functions in libdrm_tegra take as first parameter the object that
they operate on. Make the device and buffer object creation functions
follow the same scheme.
Signed-off-by: Thierry Reding
---
tegra/tegra.c | 13 +++--
tegra/tegra.h | 10
From: Thierry Reding
These helpers facilitate exporting and importing buffer objects to and
from PRIME file descriptors.
Signed-off-by: Thierry Reding
---
Changes in v3:
- add drm_public annotations
---
tegra/tegra-symbols.txt | 2 ++
tegra/tegra.c | 61
From: Thierry Reding
Allow this simple test to be installed so that it can easily be run on a
target device.
Signed-off-by: Thierry Reding
---
tests/tegra/.gitignore | 2 +-
tests/tegra/meson.build | 7 +--
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/tests/tegra
From: Thierry Reding
Add helpers to export and import buffer objects via flink names.
Signed-off-by: Thierry Reding
---
Changes in v3:
- add drm_public annotations
---
tegra/tegra-symbols.txt | 2 ++
tegra/tegra.c | 50 +
tegra/tegra.h
From: Thierry Reding
This new UABI is a more modern version that works better with both old
and recent chips.
Signed-off-by: Thierry Reding
---
include/drm/tegra_drm.h | 429 +---
1 file changed, 404 insertions(+), 25 deletions(-)
diff --git a/include/drm
From: Thierry Reding
These new functions can be used to create a job on a given channel, add
commands to the job using its push buffer and submit the job.
Signed-off-by: Thierry Reding
---
tegra/job.c | 164
tegra/meson.build | 2
From: Thierry Reding
This test can be used to purposefully trigger a job timeout.
Signed-off-by: Thierry Reding
---
tests/tegra/meson.build | 9 ++
tests/tegra/syncpt-timeout.c | 163 +++
2 files changed, 172 insertions(+)
create mode 100644 tests/tegra
From: Thierry Reding
This test uses the IOCTLs for job submission and fences to fill a sub-
region of the screen to a specific color using gr2d.
Signed-off-by: Thierry Reding
---
tests/tegra/.gitignore | 1 +
tests/tegra/drm-test-tegra.c | 147
From: Thierry Reding
This makes sure that the proper dependencies are created and that the
file is distributed.
Signed-off-by: Thierry Reding
---
tegra/meson.build | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/tegra/meson.build b/tegra/meson.build
index
From: Thierry Reding
This library provides helpers for common functionality needed by test
programs.
Signed-off-by: Thierry Reding
---
tests/tegra/drm-test.c | 248
tests/tegra/drm-test.h | 72
tests/tegra/meson.build | 7 ++
3 files
From: Thierry Reding
Implement a small abstraction interface to allow different versions of
VIC to be used transparently. An implementation will be chosen based on
the VIC version number reported by the DRM_TEGRA_IOCTL_OPEN_CHANNEL
IOCTL.
Signed-off-by: Thierry Reding
---
tests/tegra/host1x.h
From: Thierry Reding
This is a very simple sanity test to check whether or not a syncpt can
be incremented by a host1x client. This uses gr2d on Tegra20 through
Tegra114 and VIC on Tegra124 and later.
Signed-off-by: Thierry Reding
---
tests/tegra/meson.build | 9 +++
tests/tegra/syncpt
From: Thierry Reding
The Video Image Composer (VIC) 3.0 can be found on NVIDIA Tegra124 SoCs.
Signed-off-by: Thierry Reding
---
tegra/private.h | 6 +
tests/tegra/meson.build | 2 +
tests/tegra/vic.c | 8 +-
tests/tegra/vic30.c | 509
From: Thierry Reding
This test will attempt to use the VIC to blit one surface to another
and perform a vertical flip.
Signed-off-by: Thierry Reding
---
tests/tegra/meson.build | 9 ++
tests/tegra/vic-flip.c | 333
2 files changed, 342 insertions
From: Thierry Reding
The Video Image Composer (VIC) 4.2 can be found on NVIDIA Tegra194 SoCs.
It uses a different class (C5B6) that is slightly incompatible with the
class found on earlier generations, although it is backwards compatible
with the class implemented on Tegra186 (B1B6).
Signed-off
From: Thierry Reding
These new functions can be used to allocate and free syncpoints, as well
as wait for a syncpoint threshold to be reached. Jobs can also be waited
on if a syncpoint was attached to them.
Signed-off-by: Thierry Reding
---
tegra/job.c | 23 +
tegra
From: Thierry Reding
These new functions can be used to open a channel to a given engine, map
and unmap buffer objects to that channel, and close the channel.
Signed-off-by: Thierry Reding
---
tegra/channel.c | 195
tegra/meson.build
From: Thierry Reding
This test will attempt to use VIC to clear a surface.
Signed-off-by: Thierry Reding
---
tests/tegra/meson.build | 9 +++
tests/tegra/vic-clear.c | 173
2 files changed, 182 insertions(+)
create mode 100644 tests/tegra/vic
From: Thierry Reding
The Video Image Composer (VIC) 4.0 can be found on NVIDIA Tegra210 SoCs.
It uses a different class (B0B6) that is slightly incompatible with the
class found on earlier generations.
Signed-off-by: Thierry Reding
---
tests/tegra/meson.build | 2 +
tests/tegra/vic.c
From: Thierry Reding
The Video Image Composer (VIC) 4.1 can be found on NVIDIA Tegra186 SoCs.
It uses a different class (B1B6) that is slightly incompatible with the
class found on earlier generations.
Signed-off-by: Thierry Reding
---
tests/tegra/meson.build | 2 +
tests/tegra/vic.c
From: Thierry Reding
This test will attempt to use the VIC to blit from one surface to
another.
Signed-off-by: Thierry Reding
---
tests/tegra/meson.build | 9 ++
tests/tegra/vic-blit.c | 333
2 files changed, 342 insertions(+)
create mode 100644
From: Thierry Reding
Coupling of display controllers used to rely on runtime PM to take the
companion controller out of reset. Commit fd67e9c6ed5a ("drm/tegra: Do
not implement runtime PM") accidentally broke this when runtime PM was
removed.
Restore this functionality by r
From: Thierry Reding
The SOR resets are exclusively shared with the SOR power domain. This
means that exclusive access can only be granted temporarily and in order
for that to work, a rigorous sequence must be observed. To ensure that a
single consumer gets exclusive access to a reset, each
On Mon, Jan 11, 2021 at 02:59:59PM +0200, Mikko Perttunen wrote:
> To avoid false lockdep warnings, give each client lock a different
> lock class, passed from the initialization site by macro.
>
> Signed-off-by: Mikko Perttunen
> ---
> drivers/gpu/host1x/bus.c | 7 ---
> include/linux/host1
On Mon, Jan 11, 2021 at 03:00:00PM +0200, Mikko Perttunen wrote:
> Syncpoints don't need to be associated with any client,
> so remove the property, and expose host1x_syncpt_alloc.
> This will allow allocating syncpoints without prior knowledge
> of the engine that it will be used with.
>
> Signed
On Mon, Jan 11, 2021 at 03:00:01PM +0200, Mikko Perttunen wrote:
> Show the number of pending waiters in the debugfs status file.
> This is useful for testing to verify that waiters do not leak
> or accumulate incorrectly.
>
> Signed-off-by: Mikko Perttunen
> ---
> drivers/gpu/host1x/debug.c | 1
On Mon, Mar 22, 2021 at 07:01:34PM +0300, Dmitry Osipenko wrote:
> 22.03.2021 18:19, Mikko Perttunen пишет:
> > On 22.3.2021 16.48, Dmitry Osipenko wrote:
> >> 22.03.2021 17:46, Thierry Reding пишет:
> >>> On Mon, Jan 11, 2021 at 02:59:59PM +0200, Mikko Perttune
On Wed, Jan 13, 2021 at 12:20:38AM +0200, Mikko Perttunen wrote:
> On 1/13/21 12:07 AM, Dmitry Osipenko wrote:
> > 11.01.2021 16:00, Mikko Perttunen пишет:
> > > -void host1x_intr_put_ref(struct host1x *host, unsigned int id, void *ref)
> > > +void host1x_intr_put_ref(struct host1x *host, unsigned
On Mon, Jan 11, 2021 at 03:00:03PM +0200, Mikko Perttunen wrote:
> Make syncpoint expiration checks always use the same logic used by
> the hardware. This ensures that there are no race conditions that
> could occur because of the hardware triggering a syncpoint interrupt
> and then the driver disa
On Mon, Jan 11, 2021 at 03:00:04PM +0200, Mikko Perttunen wrote:
> Add reference counting for allocated syncpoints to allow keeping
> them allocated while jobs are referencing them. Additionally,
> clean up various places using syncpoint IDs to use host1x_syncpt
> pointers instead.
>
> Signed-off-
On Mon, Jan 11, 2021 at 03:00:05PM +0200, Mikko Perttunen wrote:
> Add the userspace interface header, specifying interfaces
> for allocating and accessing syncpoints from userspace,
> and for creating sync_file based fences based on syncpoint
> thresholds.
>
> Signed-off-by: Mikko Perttunen
> --
On Mon, Jan 11, 2021 at 03:00:06PM +0200, Mikko Perttunen wrote:
> Add the /dev/host1x device node, implementing the following
> functionality:
>
> - Reading syncpoint values
> - Allocating syncpoints (providing syncpoint FDs)
> - Incrementing syncpoints (based on syncpoint FD)
>
> Signed-off-by:
On Mon, Jan 11, 2021 at 03:00:07PM +0200, Mikko Perttunen wrote:
> Add an implementation of dma_fences based on syncpoints. Syncpoint
> interrupts are used to signal fences. Additionally, after
> software signaling has been enabled, a 30 second timeout is started.
> If the syncpoint threshold is no
On Tue, Mar 23, 2021 at 12:44:28PM +0200, Mikko Perttunen wrote:
> On 3/23/21 12:36 PM, Thierry Reding wrote:
> > On Mon, Jan 11, 2021 at 03:00:04PM +0200, Mikko Perttunen wrote:
> > > Add reference counting for allocated syncpoints to allow keeping
> > > them allocated
On Tue, Mar 23, 2021 at 01:12:36PM +0200, Mikko Perttunen wrote:
> On 3/23/21 12:52 PM, Thierry Reding wrote:
> > On Mon, Jan 11, 2021 at 03:00:05PM +0200, Mikko Perttunen wrote:
[...]
> > > +struct host1x_fence_extract_fence {
> > > + __u32
On Mon, Jan 11, 2021 at 03:00:09PM +0200, Mikko Perttunen wrote:
> Add a callback field to the job structure, to be called just before
> the job is to be freed. This allows the job's submitter to clean
> up any of its own state, like decrement runtime PM refcounts.
>
> Signed-off-by: Mikko Perttun
On Thu, Jan 14, 2021 at 12:34:22PM +0200, Mikko Perttunen wrote:
> On 1/14/21 10:36 AM, Dmitry Osipenko wrote:
> > 13.01.2021 21:56, Mikko Perttunen пишет:
> > > On 1/13/21 8:14 PM, Dmitry Osipenko wrote:
> > > > 11.01.2021 16:00, Mikko Perttunen пишет:
> > > > > +struct drm_tegra_submit_buf {
> >
On Mon, Jan 11, 2021 at 03:00:16PM +0200, Mikko Perttunen wrote:
> To avoid duplication, allocate the per-engine shared channel in the
> core code instead. Once MLOCKs are implemented on Host1x side, we
> can also update this to avoid allocating a shared channel when
> MLOCKs are enabled.
>
> Sign
On Mon, Jan 11, 2021 at 03:00:17PM +0200, Mikko Perttunen wrote:
> Implement the non-submission parts of the new UAPI, including
> channel management and memory mapping. The UAPI is under the
> CONFIG_DRM_TEGRA_STAGING config flag for now.
>
> Signed-off-by: Mikko Perttunen
> ---
> v5:
> * Set io
On Mon, Jan 11, 2021 at 03:00:18PM +0200, Mikko Perttunen wrote:
> Implement the job submission IOCTL with a minimum feature set.
>
> Signed-off-by: Mikko Perttunen
> ---
> v5:
> * Add 16K size limit to copies from userspace.
> * Guard RELOC_BLOCKLINEAR flag handling to only exist in ARM64
> to
From: Thierry Reding
Hi,
this fixes a couple of oddities like slightly off DMA masks and add
support for hardware cursors on newer chips as well as support for the
sector layout bit in NVIDIA framebuffer modifiers.
The first patch in this set is a small helper that I think might be
useful to
From: Thierry Reding
This is useful for checking at runtime whether a given modifier is from
a specific vendor so that any vendor-specific parsing can be done.
Signed-off-by: Thierry Reding
---
include/uapi/drm/drm_fourcc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/uapi
From: Thierry Reding
Inherit the DMA mask from host1x (on Tegra210 and earlier) or the
display hub (on Tegra186 and later). This is necessary in order to
properly map buffers without SMMU support and use the maximum IOVA
space available with SMMU support.
Signed-off-by: Thierry Reding
From: Thierry Reding
Tegra186 and later support a higher maximum resolution than earlier
chips, so make sure to reflect that in the mode configuration.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/tegra/dc.c | 6 ++
drivers/gpu/drm/tegra/drm.c | 13 ++---
drivers/gpu/drm
From: Thierry Reding
The hardware cursor on Tegra186 differs slightly from the implementation
on older SoC generations. In particular the new implementation relies on
software for clipping the cursor against the screen. Fortunately, atomic
KMS already computes clipped coordinates for (cursor
From: Thierry Reding
Add a debug message to let the user know when a framebuffer modifier is
not supported.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/tegra/fb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c
index
From: Thierry Reding
Clarify when a fixed IOV address can be used and when a buffer has to
be mapped before the IOVA can be used.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/tegra/plane.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers
From: Thierry Reding
These callbacks can be used by client drivers to run code during early
init and during late exit. Early init callbacks are run prior to the
regular init callbacks while late exit callbacks run after the regular
exit callbacks.
Signed-off-by: Thierry Reding
---
drivers/gpu
From: Thierry Reding
In order to be able to attach planes to all possible display controllers
the exact number of CRTCs must be known. Keep track of the number of the
display controllers that register during initialization.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/tegra/dc.c | 22
From: Thierry Reding
Tegra194 has a special physical address bit that enables some memory
swizzling logic to support different sector layouts. Support the bit
that selects the sector layout which is passed in the framebuffer
modifier.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/tegra
On Tue, Mar 23, 2021 at 05:00:30PM +0300, Dmitry Osipenko wrote:
> 23.03.2021 15:30, Thierry Reding пишет:
> > On Thu, Jan 14, 2021 at 12:34:22PM +0200, Mikko Perttunen wrote:
> >> On 1/14/21 10:36 AM, Dmitry Osipenko wrote:
> >>> 13.01.2021 21:56, Mikko Perttunen пи
On Tue, Mar 23, 2021 at 04:04:35PM +, Simon Ser wrote:
> Can we instead have a macro/function to get the vendor? This would be
> useful elsewhere as well, see drmGetFormatModifierVendor in a recent-ish
> libdrm patch [1].
>
> [1]:
> https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/108
On Tue, Mar 23, 2021 at 06:00:34PM +0300, Dmitry Osipenko wrote:
> 23.03.2021 17:43, Mikko Perttunen пишет:
> >>
> >> FWIW, I would've been fine with stashing all of this into drm.c as well
> >> since the rest of the UAPI is in that already. The churn in this patch
> >> is reasonably small, but it
On Tue, Mar 23, 2021 at 04:16:00PM +0200, Mikko Perttunen wrote:
> On 3/23/21 3:38 PM, Thierry Reding wrote:
> > On Mon, Jan 11, 2021 at 03:00:18PM +0200, Mikko Perttunen wrote:
> > > Implement the job submission IOCTL with a minimum feature set.
> > >
> >
On Tue, Mar 23, 2021 at 08:32:50PM +0300, Dmitry Osipenko wrote:
> 23.03.2021 19:44, Thierry Reding пишет:
> > On Tue, Mar 23, 2021 at 05:00:30PM +0300, Dmitry Osipenko wrote:
> >> 23.03.2021 15:30, Thierry Reding пишет:
> >>> On Thu, Jan 14, 2021 at 12:34:22P
On Sat, Feb 27, 2021 at 02:19:39PM +0300, Dmitry Osipenko wrote:
> 03.02.2021 14:18, Mikko Perttunen пишет:
> ...
> >> I'll need more time to think about it.
> >>
> >
> > How about something like this:
> >
> > Turn the syncpt_incr field back into an array of structs like
> >
> > #define DRM_TEGR
On Tue, Mar 23, 2021 at 08:57:42PM +0300, Dmitry Osipenko wrote:
> 23.03.2021 18:54, Thierry Reding пишет:
> > @@ -920,15 +934,42 @@ static void tegra_cursor_atomic_update(struct
> > drm_plane *plane,
> > value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CO
On Wed, Mar 24, 2021 at 05:41:08PM +0300, Dmitry Osipenko wrote:
> 23.03.2021 18:54, Thierry Reding пишет:
> > From: Thierry Reding
> >
> > Clarify when a fixed IOV address can be used and when a buffer has to
> > be mapped before the IOVA can be used.
> >
On Tue, Mar 23, 2021 at 10:05:23PM +0300, Dmitry Osipenko wrote:
> 23.03.2021 21:24, Thierry Reding пишет:
> > On Tue, Mar 23, 2021 at 08:57:42PM +0300, Dmitry Osipenko wrote:
> >> 23.03.2021 18:54, Thierry Reding пишет:
> >>> @@ -920,15 +934,42 @@ static void teg
On Tue, Mar 02, 2021 at 04:15:06PM +0300, Dmitry Osipenko wrote:
> RGB output doesn't allow to change parent clock rate of the display and
> PCLK rate is set to 0Hz in this case. The tegra_dc_commit_state() shall
> not set the display clock to 0Hz since this change propagates to the
> parent clock.
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