[PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

From: Matt Atwood DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended receiver capabilities. For panels that use this new feature wait interval would be increased by 512 ms, when

[PATCH 1/2] drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper

From: Matt Atwood As more differentation occurs between DP spec. Its useful to have these as macros in a drm_dp_helper. v2: DPCD_REV_XX to DP_DPCD_REV_XX Signed-off-by: Matt Atwood --- include/drm/drm_dp_helper.h | 5 + 1 file

[PATCH 1/2] drm/dp: add extended receiver capability field present bit

From: Matt Atwood This bit was added to DP Training Aux RD interval with DP 1.3. Via descriptiion of the spec this field indicates the panels true capabilities are described in DPCD address space 02200h through 022FFh. v2: version comment update v3: version comment correction, commit message

[PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

From: Matt Atwood According to DP spec (2.9.3.1 of DP 1.4) if EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD 02200h through 0220Fh shall contain the DPRX's true capability. These values will match 0h through Fh, except for DPCD_REV, MAX_LINK_RATE,

[PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

From: Matt Atwood According to DP spec (2.9.3.1 of DP 1.4) if EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD 02200h through 0220Fh shall contain the DPRX's true capability. These values will match 0h through Fh, except for DPCD_REV, MAX_LINK_RATE,

[PATCH 1/2] drm/dp: add extended receiver capability field present bit

From: Matt Atwood This bit was added to DP Training Aux RD interval sometime between DP 1.2 and DP 1.3. Via description of the spec this field indicates the panels true capabilities are described in DPCD address space 02200h through 022FFh. Signed-off-by: Matt Atwood ---

[PATCH 1/2] drm/dp: add extended receiver capability field present bit

From: Matt Atwood This bit was added to DP Training Aux RD interval with DP 1.3. Via descriptiion of the spec this field indicates the panels true capabilities are described in DPCD address space 02200h through 022FFh. v2: version comment update v3: version comment correction, commit message

[PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

From: Matt Atwood According to DP spec (2.9.3.1 of DP 1.4) if EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD 02200h through 0220Fh shall contain the DPRX's true capability. These values will match 0h through Fh, except for DPCD_REV, MAX_LINK_RATE,

[PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

From: Matt Atwood According to DP spec (2.9.3.1 of DP 1.4) if EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD 02200h through 0220Fh shall contain the DPRX's true capability. These values will match 0h through Fh, except for DPCD_REV, MAX_LINK_RATE,

[PATCH 1/2] drm/dp: add extended receiver capability field present bit

From: Matt Atwood This bit was added to DP Training Aux RD interval sometime between DP 1.2 and DP 1.3. Via description of the spec this field indicates the panels true capabilities are described in DPCD address space 02200h through 022FFh. v2: version comment update Signed-off-by: Matt Atwood

[PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

From: Matt Atwood DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheme from 8 bits to 7 bits in DPCD 0x000e. The 8th bit describes a new feature, for panels that use this new feature, this would cause a wait interval for clock recovery of at least 512 ms,

[PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

From: Matt Atwood DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended receiver capabilities. For panels that use this new feature wait interval would be increased by 512 ms, when

[PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

From: Matt Atwood DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended receiver capabilities. For panels that use this new feature wait interval would be increased by 512 ms, when

[PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

From: Matt Atwood DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended receiver capabilities. For panels that use this new feature wait interval would be increased by 512 ms, when

[PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

From: Matt Atwood DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended receiver capabilities. For panels that use this new feature wait interval would be increased by 512 ms, when

[PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

From: Matt Atwood DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended receiver capabilities. For panels that use this new feature wait interval would be increased by 512 ms, when

[PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

From: Matt Atwood DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended receiver capabilities. For panels that use this new feature wait interval would be increased by 512 ms, when

[PATCH] Intel: Add a Kaby Lake PCI ID

From: Matt Atwood Based on kernel commit '672e314b21dc ("drm/i915/kbl: Add KBL GT2 sku")' v2: name change M -> ULX, add enumeration in KBL ULX v3: add entry to IS_KABYLAKE Signed-off-by: Matt Atwood --- intel/intel_chipset.h | 6 --

[PATCH] Intel: Add a Kaby Lake PCI ID

From: Matt Atwood v2: name change M -> ULX, add enumeration in KBL ULX Signed-off-by: Matt Atwood --- intel/intel_chipset.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/intel/intel_chipset.h

[PATCH] Intel: Add a Kaby Lake PCI ID

From: Matt Atwood Based on kernel commit '672e314b21dc ("drm/i915/kbl: Add KBL GT2 sku")' v2: name change M -> ULX, add enumeration in KBL ULX Signed-off-by: Matt Atwood --- intel/intel_chipset.h | 3 ++- 1 file changed, 2

[PATCH] Intel: Add a Kaby Lake PCI ID

From: Matt Atwood Signed-off-by: Matt Atwood --- intel/intel_chipset.h | 1 + 1 file changed, 1 insertion(+) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 01d250e..6b8fd1d 100644 --- a/intel/intel_chipset.h +++

[PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

From: Matt Atwood DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended receiver capabilities. For panels that use this new feature wait interval would be increased by 512 ms, when

[PATCH 1/2] drm/dp: Move DPCD_REV_XX to drm_dp_helper

From: Matt Atwood As more differentation occurs between DP spec. Its useful to have these as macros in a drm_dp_helper. Signed-off-by: Matt Atwood --- drivers/gpu/drm/amd/display/include/dpcd_defs.h | 8

[PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

From: Matt Atwood DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended receiver capabilities. For panels that use this new feature wait interval would be increased by 512 ms, when

[PATCH] drm/dp: only accept valid DP_TRAINING_AUX_RD_INTERVAL values

From: Matt Atwood For panels that do not follow Display Port specifications mask off invalid values for DP_TRAINING_AUX_RD_INTERVAL. Specification lists acceptable values 0-4 all other values are reserved and bit 7 of DPCD 0xe describes another feature. Currently