On Tue, Jun 30, 2020 at 11:09:57PM -0400, Jonathan Marek wrote:
> This sets up bw tables for A640/A650 similar to A618/A630, 0 DDR bandwidth
> vote, and the CNOC vote. A640 has the same CNOC addresses as A630 and was
> working, but this is required for A650 to work.
>
> Eventually the bw table should be filled by querying the interconnect
> driver for each BW in the dts, but use these dummy tables for now.
Reviewed-by: Jordan Crouse
And yes, I agree that we need to move this into the generic API sooner rather
than later, but this should be good enough to get a working GPU/GMU.
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 74 +++
> 1 file changed, 74 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> index 9921e632f1ca..ccd44d0418f8 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> @@ -281,6 +281,76 @@ static void a618_build_bw_table(struct
> a6xx_hfi_msg_bw_table *msg)
> msg->cnoc_cmds_data[1][0] = 0x6001;
> }
>
> +static void a640_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> +{
> + /*
> + * Send a single "off" entry just to get things running
> + * TODO: bus scaling
> + */
> + msg->bw_level_num = 1;
> +
> + msg->ddr_cmds_num = 3;
> + msg->ddr_wait_bitmask = 0x01;
> +
> + msg->ddr_cmds_addrs[0] = 0x5;
> + msg->ddr_cmds_addrs[1] = 0x5003c;
> + msg->ddr_cmds_addrs[2] = 0x5000c;
> +
> + msg->ddr_cmds_data[0][0] = 0x4000;
> + msg->ddr_cmds_data[0][1] = 0x4000;
> + msg->ddr_cmds_data[0][2] = 0x4000;
> +
> + /*
> + * These are the CX (CNOC) votes - these are used by the GMU but the
> + * votes are known and fixed for the target
> + */
> + msg->cnoc_cmds_num = 3;
> + msg->cnoc_wait_bitmask = 0x01;
> +
> + msg->cnoc_cmds_addrs[0] = 0x50034;
> + msg->cnoc_cmds_addrs[1] = 0x5007c;
> + msg->cnoc_cmds_addrs[2] = 0x5004c;
> +
> + msg->cnoc_cmds_data[0][0] = 0x4000;
> + msg->cnoc_cmds_data[0][1] = 0x;
> + msg->cnoc_cmds_data[0][2] = 0x4000;
> +
> + msg->cnoc_cmds_data[1][0] = 0x6001;
> + msg->cnoc_cmds_data[1][1] = 0x2001;
> + msg->cnoc_cmds_data[1][2] = 0x6001;
> +}
> +
> +static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> +{
> + /*
> + * Send a single "off" entry just to get things running
> + * TODO: bus scaling
> + */
> + msg->bw_level_num = 1;
> +
> + msg->ddr_cmds_num = 3;
> + msg->ddr_wait_bitmask = 0x01;
> +
> + msg->ddr_cmds_addrs[0] = 0x5;
> + msg->ddr_cmds_addrs[1] = 0x50004;
> + msg->ddr_cmds_addrs[2] = 0x5007c;
> +
> + msg->ddr_cmds_data[0][0] = 0x4000;
> + msg->ddr_cmds_data[0][1] = 0x4000;
> + msg->ddr_cmds_data[0][2] = 0x4000;
> +
> + /*
> + * These are the CX (CNOC) votes - these are used by the GMU but the
> + * votes are known and fixed for the target
> + */
> + msg->cnoc_cmds_num = 1;
> + msg->cnoc_wait_bitmask = 0x01;
> +
> + msg->cnoc_cmds_addrs[0] = 0x500a4;
> + msg->cnoc_cmds_data[0][0] = 0x4000;
> + msg->cnoc_cmds_data[1][0] = 0x6001;
> +}
> +
> static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> {
> /* Send a single "off" entry since the 630 GMU doesn't do bus scaling */
> @@ -327,6 +397,10 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
>
> if (adreno_is_a618(adreno_gpu))
> a618_build_bw_table(&msg);
> + else if (adreno_is_a640(adreno_gpu))
> + a640_build_bw_table(&msg);
> + else if (adreno_is_a650(adreno_gpu))
> + a650_build_bw_table(&msg);
> else
> a6xx_build_bw_table(&msg);
>
> --
> 2.26.1
>
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