[PATCH 5/7] ARM: sun8i: a33: Add display pipeline
On Tue, Sep 6, 2016 at 4:21 AM, Maxime Ripard
wrote:
> Hi,
>
> On Fri, Sep 02, 2016 at 02:28:54PM +0800, Chen-Yu Tsai wrote:
>> > + be0: display-backend at 01e6 {
>> > + compatible = "allwinner,sun8i-a33-display-backend";
>> > + reg = <0x01e6 0x1>;
>>
>> Please also list the interrupt, even though we don't use it yet.
>> The manual says it's 127 - 32 = 95.
>
> Yep, you're right.
>
>> > + sat0: sat at 01e8 {
>> > + compatible = "allwinner,sun8i-a33-sat";
>> > + reg = <0x01e8 0x1000>;
>> > + clocks = < CLK_BUS_SAT>;
>> > + resets = < RST_BUS_SAT>;
>> > +
>> > + ports {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > +
>> > + sat0_in: port at 0 {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > + reg = <0>;
>> > +
>> > + sat0_in_fe0: endpoint at 0 {
>> > + reg = <0>;
>> > + remote-endpoint =
>> > <_out_sat0>;
>> > + };
>> > + };
>> > +
>> > + sat0_out: port at 1 {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > + reg = <1>;
>> > +
>> > + sat0_out_be0: endpoint at 0 {
>> > + reg = <0>;
>> > + remote-endpoint =
>> > <_in_sat0>;
>> > + };
>> > + };
>>
>> I'm worried about the representation here.
>>
>> In the user manuals, the SAT is shown as part of the BE. Look at it
>> this way: if it did come before the BE and is independent, we
>> shouldn't have to bring the SAT out of reset for simplefb to work.
>
> Indeed.
>
>> For comparison, a similar function unit called "CMU" found on the
>> other post-sun6i SoCs has the same function description as SAT on
>> the A33. It uses the reserved registers at the beginning of the BE
>> address space.
>
> Hmm, ok, so you would essentially, merge the backend and sat nodes?
>
> That wouldn't be very hard to do, i'll do it.
Yes. That is what I propose.
ChenYu
[PATCH 5/7] ARM: sun8i: a33: Add display pipeline
Hi,
On Fri, Sep 02, 2016 at 02:28:54PM +0800, Chen-Yu Tsai wrote:
> > + be0: display-backend at 01e6 {
> > + compatible = "allwinner,sun8i-a33-display-backend";
> > + reg = <0x01e6 0x1>;
>
> Please also list the interrupt, even though we don't use it yet.
> The manual says it's 127 - 32 = 95.
Yep, you're right.
> > + sat0: sat at 01e8 {
> > + compatible = "allwinner,sun8i-a33-sat";
> > + reg = <0x01e8 0x1000>;
> > + clocks = < CLK_BUS_SAT>;
> > + resets = < RST_BUS_SAT>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + sat0_in: port at 0 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0>;
> > +
> > + sat0_in_fe0: endpoint at 0 {
> > + reg = <0>;
> > + remote-endpoint =
> > <_out_sat0>;
> > + };
> > + };
> > +
> > + sat0_out: port at 1 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <1>;
> > +
> > + sat0_out_be0: endpoint at 0 {
> > + reg = <0>;
> > + remote-endpoint =
> > <_in_sat0>;
> > + };
> > + };
>
> I'm worried about the representation here.
>
> In the user manuals, the SAT is shown as part of the BE. Look at it
> this way: if it did come before the BE and is independent, we
> shouldn't have to bring the SAT out of reset for simplefb to work.
Indeed.
> For comparison, a similar function unit called "CMU" found on the
> other post-sun6i SoCs has the same function description as SAT on
> the A33. It uses the reserved registers at the beginning of the BE
> address space.
Hmm, ok, so you would essentially, merge the backend and sat nodes?
That wouldn't be very hard to do, i'll do it.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[PATCH 5/7] ARM: sun8i: a33: Add display pipeline
Hi,
On Thu, Sep 1, 2016 at 11:32 PM, Maxime Ripard
wrote:
> Add all the needed blocks to the A33 DTSI.
>
> Signed-off-by: Maxime Ripard
> ---
> arch/arm/boot/dts/sun8i-a33.dtsi | 184
> +++
> 1 file changed, 184 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi
> b/arch/arm/boot/dts/sun8i-a33.dtsi
> index deb0cd613e97..5f9dbd17eb50 100644
> --- a/arch/arm/boot/dts/sun8i-a33.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a33.dtsi
> @@ -64,6 +64,42 @@
> };
>
> soc at 01c0 {
> + tcon0: lcd-controller at 01c0c000 {
> + compatible = "allwinner,sun8i-a23-tcon";
> + reg = <0x01c0c000 0x1000>;
> + interrupts = ;
> + clocks = < CLK_BUS_LCD>,
> +< CLK_LCD_CH0>;
> + clock-names = "ahb",
> + "tcon-ch0";
> + clock-output-names = "tcon-pixel-clock";
> + resets = < RST_BUS_LCD>;
> + reset-names = "lcd";
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon0_in: port at 0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> +
> + tcon0_in_drc0: endpoint at 0 {
> + reg = <0>;
> + remote-endpoint =
> <_out_tcon0>;
> + };
> + };
> +
> + tcon0_out: port at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + };
> + };
> + };
> +
> crypto: crypto-engine at 01c15000 {
> compatible = "allwinner,sun4i-a10-crypto";
> reg = <0x01c15000 0x1000>;
> @@ -104,6 +140,154 @@
> status = "disabled";
> #phy-cells = <1>;
> };
> +
> + fe0: display-frontend at 01e0 {
> + compatible = "allwinner,sun8i-a33-display-frontend";
> + reg = <0x01e0 0x2>;
> + interrupts = ;
> + clocks = < CLK_BUS_DE_FE>, < CLK_DE_FE>,
> +< CLK_DRAM_DE_FE>;
> + clock-names = "ahb", "mod",
> + "ram";
> + resets = < RST_BUS_DE_FE>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + fe0_out: port at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + fe0_out_sat0: endpoint at 0 {
> + reg = <0>;
> + remote-endpoint =
> <_in_fe0>;
> + };
> + };
> + };
> + };
> +
> + be0: display-backend at 01e6 {
> + compatible = "allwinner,sun8i-a33-display-backend";
> + reg = <0x01e6 0x1>;
Please also list the interrupt, even though we don't use it yet.
The manual says it's 127 - 32 = 95.
> + clocks = < CLK_BUS_DE_BE>, < CLK_DE_BE>,
> +< CLK_DRAM_DE_BE>;
> + clock-names = "ahb", "mod",
> + "ram";
> + resets = < RST_BUS_DE_BE>;
> +
> + assigned-clocks = < CLK_DE_BE>;
> + assigned-clock-rates = <3>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + be0_in: port at 0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> +
> + be0_in_sat0: endpoint at 0 {
> + reg =
[PATCH 5/7] ARM: sun8i: a33: Add display pipeline
Add all the needed blocks to the A33 DTSI.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun8i-a33.dtsi | 184 +++
1 file changed, 184 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index deb0cd613e97..5f9dbd17eb50 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -64,6 +64,42 @@
};
soc at 01c0 {
+ tcon0: lcd-controller at 01c0c000 {
+ compatible = "allwinner,sun8i-a23-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_LCD>,
+< CLK_LCD_CH0>;
+ clock-names = "ahb",
+ "tcon-ch0";
+ clock-output-names = "tcon-pixel-clock";
+ resets = < RST_BUS_LCD>;
+ reset-names = "lcd";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_drc0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint =
<_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
crypto: crypto-engine at 01c15000 {
compatible = "allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
@@ -104,6 +140,154 @@
status = "disabled";
#phy-cells = <1>;
};
+
+ fe0: display-frontend at 01e0 {
+ compatible = "allwinner,sun8i-a33-display-frontend";
+ reg = <0x01e0 0x2>;
+ interrupts = ;
+ clocks = < CLK_BUS_DE_FE>, < CLK_DE_FE>,
+< CLK_DRAM_DE_FE>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = < RST_BUS_DE_FE>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe0_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe0_out_sat0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint =
<_in_fe0>;
+ };
+ };
+ };
+ };
+
+ be0: display-backend at 01e6 {
+ compatible = "allwinner,sun8i-a33-display-backend";
+ reg = <0x01e6 0x1>;
+ clocks = < CLK_BUS_DE_BE>, < CLK_DE_BE>,
+< CLK_DRAM_DE_BE>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = < RST_BUS_DE_BE>;
+
+ assigned-clocks = < CLK_DE_BE>;
+ assigned-clock-rates = <3>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be0_in: port at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be0_in_sat0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint =
<_out_be0>;
+ };
+ };
+
+ be0_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
