Re: [PATCH v2 07/10] drm/ingenic: Move register definitions to ingenic-drm.h
On Tue, Jun 30, 2020 at 01:52:07AM +0200, Paul Cercueil wrote: > Move the register definitions to ingenic-drm.h, to keep > ingenic-drm-drv.c tidy. > > Signed-off-by: Paul Cercueil Acked-by: Sam Ravnborg > --- > > Notes: > v2: Fix SPDX license tag > > drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 116 +--- > drivers/gpu/drm/ingenic/ingenic-drm.h | 126 ++ > 2 files changed, 128 insertions(+), 114 deletions(-) > create mode 100644 drivers/gpu/drm/ingenic/ingenic-drm.h > > diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > index f7b0c5dc8cd8..6590b61cb915 100644 > --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > @@ -4,6 +4,8 @@ > // > // Copyright (C) 2019, Paul Cercueil > > +#include "ingenic-drm.h" > + > #include > #include > #include > @@ -32,120 +34,6 @@ > #include > #include > > -#define JZ_REG_LCD_CFG 0x00 > -#define JZ_REG_LCD_VSYNC 0x04 > -#define JZ_REG_LCD_HSYNC 0x08 > -#define JZ_REG_LCD_VAT 0x0C > -#define JZ_REG_LCD_DAH 0x10 > -#define JZ_REG_LCD_DAV 0x14 > -#define JZ_REG_LCD_PS0x18 > -#define JZ_REG_LCD_CLS 0x1C > -#define JZ_REG_LCD_SPL 0x20 > -#define JZ_REG_LCD_REV 0x24 > -#define JZ_REG_LCD_CTRL 0x30 > -#define JZ_REG_LCD_STATE 0x34 > -#define JZ_REG_LCD_IID 0x38 > -#define JZ_REG_LCD_DA0 0x40 > -#define JZ_REG_LCD_SA0 0x44 > -#define JZ_REG_LCD_FID0 0x48 > -#define JZ_REG_LCD_CMD0 0x4C > -#define JZ_REG_LCD_DA1 0x50 > -#define JZ_REG_LCD_SA1 0x54 > -#define JZ_REG_LCD_FID1 0x58 > -#define JZ_REG_LCD_CMD1 0x5C > - > -#define JZ_LCD_CFG_SLCD BIT(31) > -#define JZ_LCD_CFG_PS_DISABLEBIT(23) > -#define JZ_LCD_CFG_CLS_DISABLE BIT(22) > -#define JZ_LCD_CFG_SPL_DISABLE BIT(21) > -#define JZ_LCD_CFG_REV_DISABLE BIT(20) > -#define JZ_LCD_CFG_HSYNCMBIT(19) > -#define JZ_LCD_CFG_PCLKM BIT(18) > -#define JZ_LCD_CFG_INV BIT(17) > -#define JZ_LCD_CFG_SYNC_DIR BIT(16) > -#define JZ_LCD_CFG_PS_POLARITY BIT(15) > -#define JZ_LCD_CFG_CLS_POLARITY BIT(14) > -#define JZ_LCD_CFG_SPL_POLARITY BIT(13) > -#define JZ_LCD_CFG_REV_POLARITY BIT(12) > -#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11) > -#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10) > -#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) > -#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8) > -#define JZ_LCD_CFG_18_BITBIT(7) > -#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) > - > -#define JZ_LCD_CFG_MODE_GENERIC_16BIT0 > -#define JZ_LCD_CFG_MODE_GENERIC_18BITBIT(7) > -#define JZ_LCD_CFG_MODE_GENERIC_24BITBIT(6) > - > -#define JZ_LCD_CFG_MODE_SPECIAL_TFT_11 > -#define JZ_LCD_CFG_MODE_SPECIAL_TFT_22 > -#define JZ_LCD_CFG_MODE_SPECIAL_TFT_33 > - > -#define JZ_LCD_CFG_MODE_TV_OUT_P 4 > -#define JZ_LCD_CFG_MODE_TV_OUT_I 6 > - > -#define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN 8 > -#define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN9 > -#define JZ_LCD_CFG_MODE_DUAL_COLOR_STN 10 > -#define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN 11 > - > -#define JZ_LCD_CFG_MODE_8BIT_SERIAL 12 > -#define JZ_LCD_CFG_MODE_LCM 13 > - > -#define JZ_LCD_VSYNC_VPS_OFFSET 16 > -#define JZ_LCD_VSYNC_VPE_OFFSET 0 > - > -#define JZ_LCD_HSYNC_HPS_OFFSET 16 > -#define JZ_LCD_HSYNC_HPE_OFFSET 0 > - > -#define JZ_LCD_VAT_HT_OFFSET 16 > -#define JZ_LCD_VAT_VT_OFFSET 0 > - > -#define JZ_LCD_DAH_HDS_OFFSET16 > -#define JZ_LCD_DAH_HDE_OFFSET0 > - > -#define JZ_LCD_DAV_VDS_OFFSET16 > -#define JZ_LCD_DAV_VDE_OFFSET0 > - > -#define JZ_LCD_CTRL_BURST_4 (0x0 << 28) > -#define JZ_LCD_CTRL_BURST_8 (0x1 << 28) > -#define JZ_LCD_CTRL_BURST_16 (0x2 << 28) > -#define JZ_LCD_CTRL_RGB555
[PATCH v2 07/10] drm/ingenic: Move register definitions to ingenic-drm.h
Move the register definitions to ingenic-drm.h, to keep ingenic-drm-drv.c tidy. Signed-off-by: Paul Cercueil --- Notes: v2: Fix SPDX license tag drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 116 +--- drivers/gpu/drm/ingenic/ingenic-drm.h | 126 ++ 2 files changed, 128 insertions(+), 114 deletions(-) create mode 100644 drivers/gpu/drm/ingenic/ingenic-drm.h diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index f7b0c5dc8cd8..6590b61cb915 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -4,6 +4,8 @@ // // Copyright (C) 2019, Paul Cercueil +#include "ingenic-drm.h" + #include #include #include @@ -32,120 +34,6 @@ #include #include -#define JZ_REG_LCD_CFG 0x00 -#define JZ_REG_LCD_VSYNC 0x04 -#define JZ_REG_LCD_HSYNC 0x08 -#define JZ_REG_LCD_VAT 0x0C -#define JZ_REG_LCD_DAH 0x10 -#define JZ_REG_LCD_DAV 0x14 -#define JZ_REG_LCD_PS 0x18 -#define JZ_REG_LCD_CLS 0x1C -#define JZ_REG_LCD_SPL 0x20 -#define JZ_REG_LCD_REV 0x24 -#define JZ_REG_LCD_CTRL0x30 -#define JZ_REG_LCD_STATE 0x34 -#define JZ_REG_LCD_IID 0x38 -#define JZ_REG_LCD_DA0 0x40 -#define JZ_REG_LCD_SA0 0x44 -#define JZ_REG_LCD_FID00x48 -#define JZ_REG_LCD_CMD00x4C -#define JZ_REG_LCD_DA1 0x50 -#define JZ_REG_LCD_SA1 0x54 -#define JZ_REG_LCD_FID10x58 -#define JZ_REG_LCD_CMD10x5C - -#define JZ_LCD_CFG_SLCDBIT(31) -#define JZ_LCD_CFG_PS_DISABLE BIT(23) -#define JZ_LCD_CFG_CLS_DISABLE BIT(22) -#define JZ_LCD_CFG_SPL_DISABLE BIT(21) -#define JZ_LCD_CFG_REV_DISABLE BIT(20) -#define JZ_LCD_CFG_HSYNCM BIT(19) -#define JZ_LCD_CFG_PCLKM BIT(18) -#define JZ_LCD_CFG_INV BIT(17) -#define JZ_LCD_CFG_SYNC_DIRBIT(16) -#define JZ_LCD_CFG_PS_POLARITY BIT(15) -#define JZ_LCD_CFG_CLS_POLARITYBIT(14) -#define JZ_LCD_CFG_SPL_POLARITYBIT(13) -#define JZ_LCD_CFG_REV_POLARITYBIT(12) -#define JZ_LCD_CFG_HSYNC_ACTIVE_LOWBIT(11) -#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10) -#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) -#define JZ_LCD_CFG_VSYNC_ACTIVE_LOWBIT(8) -#define JZ_LCD_CFG_18_BIT BIT(7) -#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) - -#define JZ_LCD_CFG_MODE_GENERIC_16BIT 0 -#define JZ_LCD_CFG_MODE_GENERIC_18BIT BIT(7) -#define JZ_LCD_CFG_MODE_GENERIC_24BIT BIT(6) - -#define JZ_LCD_CFG_MODE_SPECIAL_TFT_1 1 -#define JZ_LCD_CFG_MODE_SPECIAL_TFT_2 2 -#define JZ_LCD_CFG_MODE_SPECIAL_TFT_3 3 - -#define JZ_LCD_CFG_MODE_TV_OUT_P 4 -#define JZ_LCD_CFG_MODE_TV_OUT_I 6 - -#define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN 8 -#define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN 9 -#define JZ_LCD_CFG_MODE_DUAL_COLOR_STN 10 -#define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN11 - -#define JZ_LCD_CFG_MODE_8BIT_SERIAL12 -#define JZ_LCD_CFG_MODE_LCM13 - -#define JZ_LCD_VSYNC_VPS_OFFSET16 -#define JZ_LCD_VSYNC_VPE_OFFSET0 - -#define JZ_LCD_HSYNC_HPS_OFFSET16 -#define JZ_LCD_HSYNC_HPE_OFFSET0 - -#define JZ_LCD_VAT_HT_OFFSET 16 -#define JZ_LCD_VAT_VT_OFFSET 0 - -#define JZ_LCD_DAH_HDS_OFFSET 16 -#define JZ_LCD_DAH_HDE_OFFSET 0 - -#define JZ_LCD_DAV_VDS_OFFSET 16 -#define JZ_LCD_DAV_VDE_OFFSET 0 - -#define JZ_LCD_CTRL_BURST_4(0x0 << 28) -#define JZ_LCD_CTRL_BURST_8(0x1 << 28) -#define JZ_LCD_CTRL_BURST_16 (0x2 << 28) -#define JZ_LCD_CTRL_RGB555 BIT(27) -#define JZ_LCD_CTRL_OFUP BIT(26) -#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24) -#define JZ_LCD_CTRL_FRC_GRAYSCALE_4(0x1 << 24) -#define JZ_LCD_CTRL_FRC_GRAYSCALE_2(0x2 << 24) -#define JZ_LCD_CTRL_PDD_MASK (0xff << 16) -#define JZ_LCD_CTRL_EOF_IRQBIT(13) -#define JZ_LCD_CTRL_SOF_IRQBIT(12) -#define JZ_L
