The eLCDIF controller has control pin for the external LCD reset pin.
Add support for it and assert this pin in enable and de-assert it in
disable.

Signed-off-by: Robert Chiras <robert.chi...@nxp.com>
---
 drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 14 ++++++++++----
 drivers/gpu/drm/mxsfb/mxsfb_regs.h |  2 ++
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c 
b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index 1be29f5..a4ba368 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
@@ -224,9 +224,12 @@ static void mxsfb_enable_controller(struct 
mxsfb_drm_private *mxsfb)
                clk_prepare_enable(mxsfb->clk_disp_axi);
        clk_prepare_enable(mxsfb->clk);
 
-       if (mxsfb->devdata->ipversion >= 4)
+       if (mxsfb->devdata->ipversion >= 4) {
                writel(CTRL2_OUTSTANDING_REQS(REQ_16),
                       mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
+               /* Assert LCD Reset bit */
+               writel(CTRL2_LCD_RESET, mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
+       }
 
        /* If it was disabled, re-enable the mode again */
        writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);
@@ -244,11 +247,14 @@ static void mxsfb_disable_controller(struct 
mxsfb_drm_private *mxsfb)
 {
        u32 reg;
 
-       if (mxsfb->devdata->ipversion >= 4)
+       writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_CLR);
+
+       if (mxsfb->devdata->ipversion >= 4) {
                writel(CTRL2_OUTSTANDING_REQS(0x7),
                       mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);
-
-       writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_CLR);
+               /* De-assert LCD Reset bit */
+               writel(CTRL2_LCD_RESET, mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);
+       }
 
        /*
         * Even if we disable the controller here, it will still continue
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_regs.h 
b/drivers/gpu/drm/mxsfb/mxsfb_regs.h
index dc4daa0..0f63ba1 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_regs.h
+++ b/drivers/gpu/drm/mxsfb/mxsfb_regs.h
@@ -108,6 +108,8 @@
 #define CTRL2_LINE_PATTERN_BGR 5
 #define CTRL2_LINE_PATTERN_CLR 7
 
+#define CTRL2_LCD_RESET                        BIT(0)
+
 #define TRANSFER_COUNT_SET_VCOUNT(x)   REG_PUT((x), 31, 16)
 #define TRANSFER_COUNT_GET_VCOUNT(x)   REG_GET((x), 31, 16)
 #define TRANSFER_COUNT_SET_HCOUNT(x)   REG_PUT((x), 15, 0)
-- 
2.7.4

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