Quoting Matthew Auld (2019-08-09 23:26:33)
> From: Michal Wajdeczko
>
> HWS placement restrictions can't just rely on HAS_LLC flag.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 634ef45b77da..46658ecd8975 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -512,7 +512,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs
> *engine,
> unsigned int flags;
>
> flags = PIN_GLOBAL;
> - if (!HAS_LLC(engine->i915))
> + if (!HAS_LLC(engine->i915) && HAS_MAPPABLE_APERTURE(engine->i915))
Should we risk IS_GEN() <= 9 instead?
> /*
> * On g33, we cannot place HWS above 256MiB, so
> * restrict its pinning to the low mappable arena.
> --
> 2.20.1
>
> ___
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
