Re: [PATCH] drm/i915: Consistently use enum pipe for PCH transcoders

[Matthias Kaehlcke]

El Mon, Jul 17, 2017 at 11:07:01AM +0200 Daniel Vetter ha dit:

> On Fri, Jul 14, 2017 at 06:04:03PM -0700, Matthias Kaehlcke wrote:
> > The current code uses two different enum types for PCH transcoders and
> > performs implicit conversions between the two types. This is error prone
> > and causes clang to raise warnings like this:
> > 
> > drivers/gpu/drm/i915/intel_dp.c:3546:51: warning: implicit conversion
> >   from enumeration type 'enum pipe' to different enumeration type
> >   'enum transcoder' [-Wenum-conversion]
> > intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
> > 
> > Consistently use the type enum pipe for PCH transcoders.
> > 
> > Signed-off-by: Matthias Kaehlcke 
> 
> Thanks for respinning. Unfortunately it doesn't apply cleanly to
> drm-intel-next-queued, and I don't have a clang setup ready to confirm I
> didn't screw up anything. Can you pls rebase?

Thanks for having a look. The patch was against v4.12, I will rebase
it on drm-intel-next-queued.

> > ---
> >  drivers/gpu/drm/i915/i915_irq.c| 10 +-
> >  drivers/gpu/drm/i915/intel_display.c   | 24 ++--
> >  drivers/gpu/drm/i915/intel_drv.h   |  6 +++---
> >  drivers/gpu/drm/i915/intel_fifo_underrun.c |  6 +++---
> >  4 files changed, 21 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c 
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 190f6aa5d15e..7960d2170750 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2132,10 +2132,10 @@ static void ibx_irq_handler(struct drm_i915_private 
> > *dev_priv, u32 pch_iir)
> > DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
> >  
> > if (pch_iir & SDE_TRANSA_FIFO_UNDER)
> > -   intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
> > +   intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
> >  
> > if (pch_iir & SDE_TRANSB_FIFO_UNDER)
> > -   intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
> > +   intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
> >  }
> >  
> >  static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
> > @@ -2169,13 +2169,13 @@ static void cpt_serr_int_handler(struct 
> > drm_i915_private *dev_priv)
> > DRM_ERROR("PCH poison interrupt\n");
> >  
> > if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
> > -   intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
> > +   intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
> >  
> > if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
> > -   intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
> > +   intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
> >  
> > if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
> > -   intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
> > +   intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_C);
> >  
> > I915_WRITE(SERR_INT, serr_int);
> >  }
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 9106ea32b048..21a8fea46ad9 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1782,7 +1782,7 @@ static void lpt_enable_pch_transcoder(struct 
> > drm_i915_private *dev_priv,
> >  
> > /* FDI must be feeding us bits for PCH ports */
> > assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
> > -   assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
> > +   assert_fdi_rx_enabled(dev_priv, PIPE_A);
> >  
> > /* Workaround: set timing override bit. */
> > val = I915_READ(TRANS_CHICKEN2(PIPE_A));
> > @@ -1858,16 +1858,16 @@ void lpt_disable_pch_transcoder(struct 
> > drm_i915_private *dev_priv)
> > I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
> >  }
> >  
> > -enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
> > +enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
> >  {
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  
> > WARN_ON(!crtc->config->has_pch_encoder);
> >  
> > if (HAS_PCH_LPT(dev_priv))
> > -   return TRANSCODER_A;
> > +   return PIPE_A;
> > else
> > -   return (enum transcoder) crtc->pipe;
> > +   return crtc->pipe;
> >  }
> >  
> >  /**
> > @@ -1906,7 +1906,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
> > if (crtc->config->has_pch_encoder) {
> > /* if driving the PCH, we need FDI enabled */
> > assert_fdi_rx_pll_enabled(dev_priv,
> > - (enum pipe) 
> > intel_crtc_pch_transcoder(crtc));
> > + 
> > intel_crtc_pch_transcoder(crtc));
> > assert_fdi_tx_pll_enabled(dev_priv,
> >   (enum pipe) 

Re: [PATCH] drm/i915: Consistently use enum pipe for PCH transcoders

[Daniel Vetter]

On Fri, Jul 14, 2017 at 06:04:03PM -0700, Matthias Kaehlcke wrote:
> The current code uses two different enum types for PCH transcoders and
> performs implicit conversions between the two types. This is error prone
> and causes clang to raise warnings like this:
> 
> drivers/gpu/drm/i915/intel_dp.c:3546:51: warning: implicit conversion
>   from enumeration type 'enum pipe' to different enumeration type
>   'enum transcoder' [-Wenum-conversion]
> intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
> 
> Consistently use the type enum pipe for PCH transcoders.
> 
> Signed-off-by: Matthias Kaehlcke 

Thanks for respinning. Unfortunately it doesn't apply cleanly to
drm-intel-next-queued, and I don't have a clang setup ready to confirm I
didn't screw up anything. Can you pls rebase?

Thanks a lot.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_irq.c| 10 +-
>  drivers/gpu/drm/i915/intel_display.c   | 24 ++--
>  drivers/gpu/drm/i915/intel_drv.h   |  6 +++---
>  drivers/gpu/drm/i915/intel_fifo_underrun.c |  6 +++---
>  4 files changed, 21 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 190f6aa5d15e..7960d2170750 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2132,10 +2132,10 @@ static void ibx_irq_handler(struct drm_i915_private 
> *dev_priv, u32 pch_iir)
>   DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
>  
>   if (pch_iir & SDE_TRANSA_FIFO_UNDER)
> - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
> + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
>  
>   if (pch_iir & SDE_TRANSB_FIFO_UNDER)
> - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
> + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
>  }
>  
>  static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
> @@ -2169,13 +2169,13 @@ static void cpt_serr_int_handler(struct 
> drm_i915_private *dev_priv)
>   DRM_ERROR("PCH poison interrupt\n");
>  
>   if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
> - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
> + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
>  
>   if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
> - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
> + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
>  
>   if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
> - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
> + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_C);
>  
>   I915_WRITE(SERR_INT, serr_int);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 9106ea32b048..21a8fea46ad9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1782,7 +1782,7 @@ static void lpt_enable_pch_transcoder(struct 
> drm_i915_private *dev_priv,
>  
>   /* FDI must be feeding us bits for PCH ports */
>   assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
> - assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
> + assert_fdi_rx_enabled(dev_priv, PIPE_A);
>  
>   /* Workaround: set timing override bit. */
>   val = I915_READ(TRANS_CHICKEN2(PIPE_A));
> @@ -1858,16 +1858,16 @@ void lpt_disable_pch_transcoder(struct 
> drm_i915_private *dev_priv)
>   I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
>  }
>  
> -enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
> +enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
>  {
>   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>   WARN_ON(!crtc->config->has_pch_encoder);
>  
>   if (HAS_PCH_LPT(dev_priv))
> - return TRANSCODER_A;
> + return PIPE_A;
>   else
> - return (enum transcoder) crtc->pipe;
> + return crtc->pipe;
>  }
>  
>  /**
> @@ -1906,7 +1906,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
>   if (crtc->config->has_pch_encoder) {
>   /* if driving the PCH, we need FDI enabled */
>   assert_fdi_rx_pll_enabled(dev_priv,
> -   (enum pipe) 
> intel_crtc_pch_transcoder(crtc));
> +   
> intel_crtc_pch_transcoder(crtc));
>   assert_fdi_tx_pll_enabled(dev_priv,
> (enum pipe) cpu_transcoder);
>   }
> @@ -4573,7 +4573,7 @@ static void lpt_pch_enable(const struct 
> intel_crtc_state *crtc_state)
>   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  
> -