Re: [PATCH 09/11] drm/meson: Add G12A Video Clock setup
On Mon, 2019-03-25 at 15:18 +0100, Neil Armstrong wrote:
> While switching to the Common Clock Framework is still Work In Progress,
> this patch adds the corresponding G12A HDMI PLL setup to be on-par
> with the other SoCs support.
>
> The G12A has only a single tweak about the high frequency setup,
> where the HDMI PLL needs a specific setup to handle correctly the
> 5.94GHz DCO frequency.
>
> Apart that, it handle correctly all the other HDMI frequencies
> and can achieve even better DMT clock frequency precision with
> the larger fractional dividier width.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/gpu/drm/meson/meson_vclk.c | 119 ++---
> 1 file changed, 108 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/meson/meson_vclk.c
> b/drivers/gpu/drm/meson/meson_vclk.c
> index c15a5a5df633..b39034745444 100644
> --- a/drivers/gpu/drm/meson/meson_vclk.c
> +++ b/drivers/gpu/drm/meson/meson_vclk.c
> @@ -113,9 +113,12 @@
> #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */
> #define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
> #define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
> +#define HHI_HDMI_PLL_CNTL7 0x338 /* 0xce offset in data sheet */
>
> #define HDMI_PLL_RESET BIT(28)
> +#define HDMI_PLL_RESET_G12A BIT(29)
> #define HDMI_PLL_LOCKBIT(31)
> +#define HDMI_PLL_LOCK_G12A (3 << 30)
GENMASK(31, 30) ?
>
> #define FREQ_1000_1001(_freq)DIV_ROUND_CLOSEST(_freq * 1000, 1001)
>
> @@ -257,6 +260,10 @@ static void meson_venci_cvbs_clock_config(struct
> meson_drm *priv)
> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x0e55);
> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d);
> +
> + /* Poll for lock bit */
> + regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
> + (val & HDMI_PLL_LOCK), 10, 0);
> } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
> meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x427b);
> @@ -271,11 +278,26 @@ static void meson_venci_cvbs_clock_config(struct
> meson_drm *priv)
> HDMI_PLL_RESET, HDMI_PLL_RESET);
> regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
> HDMI_PLL_RESET, 0);
> - }
>
> - /* Poll for lock bit */
> - regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
> - (val & HDMI_PLL_LOCK), 10, 0);
> + /* Poll for lock bit */
> + regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
> + (val & HDMI_PLL_LOCK), 10, 0);
> + } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
> + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7);
> + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x0001);
> + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x);
> + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x6a28dc00);
> + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x65771290);
> + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
> + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x5654);
> + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x3a0504f7);
> + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7);
> +
> + /* Poll for lock bit */
> + regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
> + ((val & HDMI_PLL_LOCK_G12A) == HDMI_PLL_LOCK_G12A),
> + 10, 0);
> + }
>
> /* Disable VCLK2 */
> regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
> @@ -288,8 +310,13 @@ static void meson_venci_cvbs_clock_config(struct
> meson_drm *priv)
> VCLK2_DIV_MASK, (55 - 1));
>
> /* select vid_pll for vclk2 */
> - regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> - VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
> + if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> + VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
> + else
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> + VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
> +
> /* enable vclk2 gate */
> regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
>
> @@ -476,32 +503,80 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv,
> unsigned int m,
> /* Poll for lock bit */
>
Re: [PATCH 09/11] drm/meson: Add G12A Video Clock setup
On 09/04/2019 10:46, Jerome Brunet wrote:
> On Mon, 2019-03-25 at 15:18 +0100, Neil Armstrong wrote:
>> While switching to the Common Clock Framework is still Work In Progress,
>> this patch adds the corresponding G12A HDMI PLL setup to be on-par
>> with the other SoCs support.
>>
>> The G12A has only a single tweak about the high frequency setup,
>> where the HDMI PLL needs a specific setup to handle correctly the
>> 5.94GHz DCO frequency.
>>
>> Apart that, it handle correctly all the other HDMI frequencies
>> and can achieve even better DMT clock frequency precision with
>> the larger fractional dividier width.
>>
>> Signed-off-by: Neil Armstrong
>> ---
>> drivers/gpu/drm/meson/meson_vclk.c | 119 ++---
>> 1 file changed, 108 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/meson/meson_vclk.c
>> b/drivers/gpu/drm/meson/meson_vclk.c
>> index c15a5a5df633..b39034745444 100644
>> --- a/drivers/gpu/drm/meson/meson_vclk.c
>> +++ b/drivers/gpu/drm/meson/meson_vclk.c
>> @@ -113,9 +113,12 @@
>> #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */
>> #define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
>> #define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
>> +#define HHI_HDMI_PLL_CNTL7 0x338 /* 0xce offset in data sheet */
>>
>> #define HDMI_PLL_RESET BIT(28)
>> +#define HDMI_PLL_RESET_G12A BIT(29)
>> #define HDMI_PLL_LOCK BIT(31)
>> +#define HDMI_PLL_LOCK_G12A (3 << 30)
>
> GENMASK(31, 30) ?
Ack
>
>>
>> #define FREQ_1000_1001(_freq) DIV_ROUND_CLOSEST(_freq * 1000, 1001)
>>
>> @@ -257,6 +260,10 @@ static void meson_venci_cvbs_clock_config(struct
>> meson_drm *priv)
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x0e55);
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d);
>> +
>> +/* Poll for lock bit */
>> +regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
>> + (val & HDMI_PLL_LOCK), 10, 0);
>> } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
>> meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x427b);
>> @@ -271,11 +278,26 @@ static void meson_venci_cvbs_clock_config(struct
>> meson_drm *priv)
>> HDMI_PLL_RESET, HDMI_PLL_RESET);
>> regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
>> HDMI_PLL_RESET, 0);
>> -}
>>
>> -/* Poll for lock bit */
>> -regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
>> - (val & HDMI_PLL_LOCK), 10, 0);
>> +/* Poll for lock bit */
>> +regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
>> + (val & HDMI_PLL_LOCK), 10, 0);
>> +} else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
>> +regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7);
>> +regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x0001);
>> +regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x);
>> +regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x6a28dc00);
>> +regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x65771290);
>> +regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
>> +regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x5654);
>> +regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x3a0504f7);
>> +regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7);
>> +
>> +/* Poll for lock bit */
>> +regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
>> +((val & HDMI_PLL_LOCK_G12A) == HDMI_PLL_LOCK_G12A),
>> +10, 0);
>> +}
>>
>> /* Disable VCLK2 */
>> regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
>> @@ -288,8 +310,13 @@ static void meson_venci_cvbs_clock_config(struct
>> meson_drm *priv)
>> VCLK2_DIV_MASK, (55 - 1));
>>
>> /* select vid_pll for vclk2 */
>> -regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>> -VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
>> +if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
>> +regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>> +VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
>> +else
>> +regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>> +VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
>> +
>> /* enable vclk2 gate */
>> regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
>>
>> @@ -476,32 +503,80 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv,
>>
