Re: [PATCH v3 1/2] arm64: dts: qcom: sa8775p: Add gpu and gmu nodes
On 10/30/2024 12:32 PM, Akhil P Oommen wrote:
> From: Puranam V G Tejaswi
>
> Add gpu and gmu nodes for sa8775p chipset. As of now all
> SKUs have the same GPU fmax, so there is no requirement of
> speed bin support.
>
> Signed-off-by: Puranam V G Tejaswi
> Signed-off-by: Akhil P Oommen
> Reviewed-by: Dmitry Baryshkov
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 94
> +++
> 1 file changed, 94 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index e8dbc8d820a6..c6cb18193787 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -3072,6 +3072,100 @@ tcsr_mutex: hwlock@1f4 {
> #hwlock-cells = <1>;
> };
>
> + gpu: gpu@3d0 {
> + compatible = "qcom,adreno-663.0", "qcom,adreno";
> + reg = <0x0 0x03d0 0x0 0x4>,
> + <0x0 0x03d9e000 0x0 0x1000>,
> + <0x0 0x03d61000 0x0 0x800>;
> + reg-names = "kgsl_3d0_reg_memory",
> + "cx_mem",
> + "cx_dbgc";
> + interrupts = ;
> + iommus = <&adreno_smmu 0 0xc00>,
> + <&adreno_smmu 1 0xc00>;
> + operating-points-v2 = <&gpu_opp_table>;
> + qcom,gmu = <&gmu>;
> + interconnects = <&gem_noc MASTER_GFX3D
> QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1
> QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "gfx-mem";
> + #cooling-cells = <2>;
> +
> + status = "disabled";
> +
> + gpu_zap_shader: zap-shader {
> + memory-region = <&pil_gpu_mem>;
> + };
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-40500 {
> + opp-hz = /bits/ 64 <40500>;
> + opp-level =
> ;
> + opp-peak-kBps = <5285156>;
> + };
> +
> + opp-67600 {
> + opp-hz = /bits/ 64 <67600>;
> + opp-level = ;
> + opp-peak-kBps = <8171875>;
> + };
> +
> + opp-77800 {
> + opp-hz = /bits/ 64 <77800>;
> + opp-level =
> ;
> + opp-peak-kBps = <10687500>;
> + };
> +
> + opp-8 {
> + opp-hz = /bits/ 64 <8>;
> + opp-level =
> ;
> + opp-peak-kBps = <12484375>;
> + };
> + };
> + };
> +
> + gmu: gmu@3d6a000 {
> + compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu";
> + reg = <0x0 0x03d6a000 0x0 0x34000>,
> + <0x0 0x03de 0x0 0x1>,
> + <0x0 0x0b29 0x0 0x1>;
> + reg-names = "gmu", "rscc", "gmu_pdc";
> + interrupts = ,
> + ;
> + interrupt-names = "hfi", "gmu";
> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_CXO_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gpucc GPU_CC_AHB_CLK>,
> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
> + clock-names = "gmu",
> + "cxo",
> + "axi",
> + "memnoc",
> + "ahb",
> + "hub",
> + "smmu_vote";
> + power-domains = <&gpucc GPU_CC_CX_GDSC>,
> + <&gpucc GPU_CC_GX_GDSC>;
> + power-domain-names = "cx",
> + "gx";
> + iommus = <&adreno_smmu 5 0xc00>;
> + operating-points-v2 = <&gmu_opp_table>;
> +
> + gmu_opp_table: opp-table {
> + compatible = "opera
Re: [PATCH v3 1/2] arm64: dts: qcom: sa8775p: Add gpu and gmu nodes
On 11/1/2024 2:00 AM, Konrad Dybcio wrote:
> On 30.10.2024 8:02 AM, Akhil P Oommen wrote:
>> From: Puranam V G Tejaswi
>>
>> Add gpu and gmu nodes for sa8775p chipset. As of now all
>> SKUs have the same GPU fmax, so there is no requirement of
>> speed bin support.
>>
>> Signed-off-by: Puranam V G Tejaswi
>> Signed-off-by: Akhil P Oommen
>> Reviewed-by: Dmitry Baryshkov
>> ---
>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 94
>> +++
>> 1 file changed, 94 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> index e8dbc8d820a6..c6cb18193787 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> @@ -3072,6 +3072,100 @@ tcsr_mutex: hwlock@1f4 {
>> #hwlock-cells = <1>;
>> };
>>
>> +gpu: gpu@3d0 {
>> +compatible = "qcom,adreno-663.0", "qcom,adreno";
>
> Is the patchlevel zero for this SKU?
Yes. There is only a single revision implemented downstream.
>
>
>> +reg = <0x0 0x03d0 0x0 0x4>,
>> + <0x0 0x03d9e000 0x0 0x1000>,
>> + <0x0 0x03d61000 0x0 0x800>;
>> +reg-names = "kgsl_3d0_reg_memory",
>> +"cx_mem",
>> +"cx_dbgc";
>> +interrupts = ;
>> +iommus = <&adreno_smmu 0 0xc00>,
>> + <&adreno_smmu 1 0xc00>;
>> +operating-points-v2 = <&gpu_opp_table>;
>> +qcom,gmu = <&gmu>;
>> +interconnects = <&gem_noc MASTER_GFX3D
>> QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1
>> QCOM_ICC_TAG_ALWAYS>;
>> +interconnect-names = "gfx-mem";
>> +#cooling-cells = <2>;
>
> You might want to hook this up to a thermal-zone right away
I am checking with our Thermal team on this. Will get back shortly.
-Akhil.
>
> Konrad
Re: [PATCH v3 1/2] arm64: dts: qcom: sa8775p: Add gpu and gmu nodes
On 30.10.2024 8:02 AM, Akhil P Oommen wrote:
> From: Puranam V G Tejaswi
>
> Add gpu and gmu nodes for sa8775p chipset. As of now all
> SKUs have the same GPU fmax, so there is no requirement of
> speed bin support.
>
> Signed-off-by: Puranam V G Tejaswi
> Signed-off-by: Akhil P Oommen
> Reviewed-by: Dmitry Baryshkov
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 94
> +++
> 1 file changed, 94 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index e8dbc8d820a6..c6cb18193787 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -3072,6 +3072,100 @@ tcsr_mutex: hwlock@1f4 {
> #hwlock-cells = <1>;
> };
>
> + gpu: gpu@3d0 {
> + compatible = "qcom,adreno-663.0", "qcom,adreno";
Is the patchlevel zero for this SKU?
> + reg = <0x0 0x03d0 0x0 0x4>,
> + <0x0 0x03d9e000 0x0 0x1000>,
> + <0x0 0x03d61000 0x0 0x800>;
> + reg-names = "kgsl_3d0_reg_memory",
> + "cx_mem",
> + "cx_dbgc";
> + interrupts = ;
> + iommus = <&adreno_smmu 0 0xc00>,
> + <&adreno_smmu 1 0xc00>;
> + operating-points-v2 = <&gpu_opp_table>;
> + qcom,gmu = <&gmu>;
> + interconnects = <&gem_noc MASTER_GFX3D
> QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1
> QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "gfx-mem";
> + #cooling-cells = <2>;
You might want to hook this up to a thermal-zone right away
Konrad
