-20201113
i386 randconfig-a005-20201113
i386 randconfig-a002-20201113
i386 randconfig-a001-20201113
i386 randconfig-a003-20201113
i386 randconfig-a004-20201113
x86_64 randconfig-a015-20201113
x86_64
powerpc allmodconfig
powerpc allnoconfig
i386 randconfig-a006-20201113
i386 randconfig-a005-20201113
i386 randconfig-a002-20201113
i386 randconfig-a001-20201113
i386
On Sat, Nov 14, 2020 at 12:19 AM Greg KH wrote:
>
> On Fri, Nov 13, 2020 at 04:26:08PM +0100, Sergio Paracuellos wrote:
> > Hi Greg,
> >
> > On Mon, Nov 2, 2020 at 9:25 PM Sergio Paracuellos
> > wrote:
> > >
> > > After upgrading kernel to version 5.9.x the driver was not
> > > working anymore sh
When gb_audio_apbridgea_register_cport failed, maybe:
1) gb_pm_runtime_get_sync failed, usage counter remained unchanged;
2) gb_hd_output failed, usage counter remained increased;
In error state, there are two different states in usage cpounter. So,
if gb_hd_output failed, we should call gb_
On Mon, Nov 09, 2020 at 09:13:47PM +0800, Zhang Qilong wrote:
> When gb_audio_apbridgea_register_cport failed, maybe:
>
> 1) gb_pm_runtime_get_sync failed, usage counter remained unchanged;
>
> 2) gb_hd_output failed, usage counter remained increased;
>
> In error state, there are two differ
On Fri, Nov 13, 2020 at 04:26:08PM +0100, Sergio Paracuellos wrote:
> Hi Greg,
>
> On Mon, Nov 2, 2020 at 9:25 PM Sergio Paracuellos
> wrote:
> >
> > After upgrading kernel to version 5.9.x the driver was not
> > working anymore showing the following kernel trace:
> >
> > ...
> > mt7621-pci 1e140
Sequence Number api provides interfaces for unsigned atomic up counters
leveraging atomic_t and atomic64_t ops underneath. Convert it to use
seqnum_ops.
atomic_t variables used for stats are atomic counters. Convert them to
use seqnum_ops.
Signed-off-by: Shuah Khan
---
drivers/staging/rtl8188eu
Sequence Number api provides interfaces for unsigned atomic up counters
leveraging atomic_t and atomic64_t ops underneath. Convert it to use
seqnum_ops.
atomic_t variable used for error_count are atomic counters. Convert it to
use seqnum_ops.
Signed-off-by: Shuah Khan
---
.../staging/unisys/vis
Sequence Number api provides interfaces for unsigned atomic up counters
leveraging atomic_t and atomic64_t ops underneath. Convert it to use
seqnum_ops.
atomic_t variables used for stats are atomic counters. Convert them to
use seqnum_ops.
Signed-off-by: Shuah Khan
---
drivers/staging/rtl8723bs
On Fri, Nov 13, 2020 at 08:13:49PM +0300, Dmitry Osipenko wrote:
> 13.11.2020 19:15, Mark Brown пишет:
> > On Fri, Nov 13, 2020 at 06:55:27PM +0300, Dmitry Osipenko wrote:
> >> 13.11.2020 17:29, Mark Brown пишет:
> >
> >>> It's not clear if it matters - it's more a policy decision on the part
> >>
On Fri, Nov 13, 2020 at 08:13:49PM +0300, Dmitry Osipenko wrote:
> 13.11.2020 19:15, Mark Brown пишет:
> > My point here is that the driver shouldn't be checking for a dummy
> > regulator, the driver should be checking the features that are provided
> > to it by the regulator and handling those.
13.11.2020 19:15, Mark Brown пишет:
> On Fri, Nov 13, 2020 at 06:55:27PM +0300, Dmitry Osipenko wrote:
>> 13.11.2020 17:29, Mark Brown пишет:
>
>>> It's not clear if it matters - it's more a policy decision on the part
>>> of the driver about what it thinks safe error handling is. If it's not
>
Buenos días
Desde FOESCO os informamos que se encuentra abierto el plazo de inscripción para
la presente y ÚLTIMA CONVOCATORIA 2020 de Cursos Bonificables.
Recordamos que los cursos van dirigidos a empleados en activo y en situación
de ERTE y son totalmente bonificables con cargo al Crédito de
On Fri, Nov 13, 2020 at 01:14:45AM +0300, Dmitry Osipenko wrote:
> 12.11.2020 23:43, Thierry Reding пишет:
> >> The difference in comparison to using voltage regulator directly is
> >> minimal, basically the core-supply phandle is replaced is replaced with
> >> a power-domain phandle in a device tr
On Fri, Nov 13, 2020 at 06:55:27PM +0300, Dmitry Osipenko wrote:
> 13.11.2020 17:29, Mark Brown пишет:
> > It's not clear if it matters - it's more a policy decision on the part
> > of the driver about what it thinks safe error handling is. If it's not
> If regulator_get() returns a dummy regula
13.11.2020 17:45, Ulf Hansson пишет:
> On Thu, 12 Nov 2020 at 23:14, Dmitry Osipenko wrote:
>>
>> 12.11.2020 23:43, Thierry Reding пишет:
The difference in comparison to using voltage regulator directly is
minimal, basically the core-supply phandle is replaced is replaced with
a pow
13.11.2020 17:29, Mark Brown пишет:
> On Fri, Nov 13, 2020 at 01:37:01AM +0300, Dmitry Osipenko wrote:
>> 12.11.2020 23:01, Mark Brown пишет:
But it's not allowed to change voltage of a dummy regulator, is it
intentional?
>
>>> Of course not, we can't know if the requested new voltage is
Adds device tree binding documentation for clocks in the
MT7621 SOC.
Signed-off-by: Sergio Paracuellos
---
.../bindings/clock/mediatek,mt7621-clk.yaml | 61 +++
1 file changed, 61 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yam
The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or s
Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-dts/g
Adding myself as maintainer for mt7621 clock driver.
Signed-off-by: Sergio Paracuellos
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f1f088a29bc2..30822ad6837c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11142,6 +11142,12 @@ L: l
This patchset ports CPU clock detection for MT7621 from OpenWrt
and adds a complete clock plan for the mt7621 SOC.
The documentation for this SOC only talks about two registers
regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped
refclock. PLL and dividers
Adds dt binding header for 'mediatek,mt7621-clk' clocks.
Signed-off-by: Sergio Paracuellos
---
include/dt-bindings/clock/mt7621-clk.h | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
diff --git a/include/dt-bindings/clo
Hi Greg,
On Mon, Nov 2, 2020 at 9:25 PM Sergio Paracuellos
wrote:
>
> After upgrading kernel to version 5.9.x the driver was not
> working anymore showing the following kernel trace:
>
> ...
> mt7621-pci 1e14.pcie: resource collision:
> [mem 0x6000-0x6fff] conflicts with pcie@1e14
On Thu, 12 Nov 2020 at 23:14, Dmitry Osipenko wrote:
>
> 12.11.2020 23:43, Thierry Reding пишет:
> >> The difference in comparison to using voltage regulator directly is
> >> minimal, basically the core-supply phandle is replaced is replaced with
> >> a power-domain phandle in a device tree.
> > T
On Fri, Nov 13, 2020 at 01:37:01AM +0300, Dmitry Osipenko wrote:
> 12.11.2020 23:01, Mark Brown пишет:
> >> But it's not allowed to change voltage of a dummy regulator, is it
> >> intentional?
> > Of course not, we can't know if the requested new voltage is valid - the
> > driver would have to hav
On Thu, 2020-11-12 at 18:25 +0100, Bartosz Golaszewski wrote:
> On Thu, Nov 12, 2020 at 5:44 PM Nicolas Saenz Julienne
> wrote:
> > Itroduce devm_rpi_firmware_get(), it'll simplify the firmware handling
> > for most consumers.
> >
> > Suggested-by: Bartosz Golaszewski
> > Signed-off-by: Nicolas
The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or s
Adds dt binding header for 'mediatek,mt7621-clk' clocks.
Signed-off-by: Sergio Paracuellos
---
include/dt-bindings/clock/mt7621-clk.h | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
diff --git a/include/dt-bindings/clo
Adding myself as maintainer for mt7621 clock driver.
Signed-off-by: Sergio Paracuellos
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f1f088a29bc2..30822ad6837c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11142,6 +11142,12 @@ L: l
This patchset ports CPU clock detection for MT7621 from OpenWrt
and adds a complete clock plan for the mt7621 SOC.
The documentation for this SOC only talks about two registers
regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped
refclock. PLL and dividers
Adds device tree binding documentation for clocks in the
MT7621 SOC.
Signed-off-by: Sergio Paracuellos
---
.../bindings/clock/mediatek,mt7621-clk.yaml | 61 +++
1 file changed, 61 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yam
Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-dts/g
33 matches
Mail list logo
