Re: [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation

d 500MHz clock or a clock created by the memory controller. sysctl contains a bootstrap register to determine crystal clock, a clock mux for choosing between the 3 sources for CPU clock, and a clock gate register for various peripherals. The ralink,memctl phandle here is to read the cpu clock freque

Re: [PATCH v3 3/5] clk: ralink: add clock driver for mt7621 SoC

k design of mt7621 doesn't seem to be part of ralink legacy stuff, and ralink is already acquired by mediatek anyway. I think it should be put in drivers/clk/mediatek instead. -- Regards, Chuanhong Guo ___ devel mailing list de...@linuxdriv

Re: [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621

g. -- Regards, Chuanhong Guo ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel

Re: [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621

On Thu, Nov 12, 2020 at 9:26 AM Chuanhong Guo wrote: > > I've already said in previous threads that clock assignment in > current linux kernel is not trustworthy. > I've got the clock plan for mt7621 now. (Can't share it, sorry.) > Most of your clock assumptions above are incorre

Re: [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621

ot;: "ahb" > - "pcie1": "ahb" > - "pcie2": "ahb" > - "crypto": "ahb" > - "shxc": "ahb" > > There was a previous attempt of doing this here[0] but the author > did no

Re: [PATCH v4 5/6] staging: mt7621-pci: release gpios after pci initialization

es = "default"; > > pinctrl-0 = <_pins>; > > + > > + reset-gpios = < 19 GPIO_ACTIVE_LOW>, > > + < 8 GPIO_ACTIVE_LOW>, > > + < 7 GPIO_ACTIVE_LOW>; > > status = "okay"; > &g

Re: [PATCH v4 5/6] staging: mt7621-pci: release gpios after pci initialization

n't be detected on a specific board without gpio7 and/or gpio8, override gpio-resets in dts of that board. -- Regards, Chuanhong Guo ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel

Re: [PATCH v4 5/6] staging: mt7621-pci: release gpios after pci initialization

driver error path. This pin conflict comes from incorrectly occupying pins that are not used by pcie, and should be fixed by not occupying those pins in the first place. Releasing all gpios isn't the proper way to go. -- Regards, Chuanhong Guo ___ devel

Are people from linux-mediatek also interested in Mediatek MIPS SoCs? [Was: [PATCH] staging: mt7621-dts: add dt node for 2nd/3rd uart on mt7621]

On Tue, Feb 4, 2020 at 6:37 PM Dan Carpenter wrote: > > On Tue, Feb 04, 2020 at 05:59:21PM +0800, Chuanhong Guo wrote: > > Hi! > > > > On Tue, Feb 4, 2020 at 5:47 PM Dan Carpenter > > wrote: > > > > > > Please use ./scripts/

Re: [PATCH] staging: mt7621-dts: add dt node for 2nd/3rd uart on mt7621

ld be corrected. Regards, Chuanhong Guo ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel

[PATCH] staging: mt7621-dts: add dt node for 2nd/3rd uart on mt7621

There are 3 uarts on mt7621. This patch adds device tree node for 2nd and 2rd ones. Signed-off-by: Chuanhong Guo --- drivers/staging/mt7621-dts/mt7621.dtsi | 38 ++ 1 file changed, 38 insertions(+) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging

[PATCH] staging: mt7621-dts: fix register range of memc node in mt7621.dtsi

The memc node from mt7621.dtsi has incorrect register resource. Fix it according to the programming guide. Signed-off-by: Weijie Gao Signed-off-by: Chuanhong Guo --- drivers/staging/mt7621-dts/mt7621.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

. Of course I can't read through the ancient and heavily hacked > > vendor kernel to figure out a clock plan myself. > > Ok, I provided you some productive technical hints how it should be > done. I don't think mt7620 has better documentation then

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

On Sun, Aug 18, 2019 at 4:26 PM Chuanhong Guo wrote: > > Hi! > > On Sun, Aug 18, 2019 at 3:59 PM Oleksij Rempel wrote: > > > > Am 18.08.19 um 09:19 schrieb Chuanhong Guo: > > > Hi! > > > > > > On Sun, Aug 18, 2019 at 2:10 PM Oleksij Rempel &

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

Hi! On Sun, Aug 18, 2019 at 3:59 PM Oleksij Rempel wrote: > > Am 18.08.19 um 09:19 schrieb Chuanhong Guo: > > Hi! > > > > On Sun, Aug 18, 2019 at 2:10 PM Oleksij Rempel > > wrote: > >> > >>>> We have at least 2 know registers: > >&g

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

elated part and there is no information to properly implement it unless MTK decided to release a clock plan somehow. > This code is currently on prototyping phase Code for clock calculation is done, not "prototyping". > It means, we cannot expect that this driver will be fixed

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

river will work part of power > management and nice devicetree without fixed clocks. Regards, Chuanhong Guo ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

ce of info is missing in datasheet. > > IMO - this information is enough to create full blown > drivers/clk/mediatek/clk-mt7621.c And this information isn't enough because the assumption above is incorrect :P Regards, Chuanhong Guo ___

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

ing clock frequencies for every peripherals, thus unable to write a working clock driver. > > > + > > + #clock-cells = <1>; > > + clock-output-names = "cpu", "bus"; > > + }; > > -- > &g

[PATCH v2 6/6] staging: mt7621-dts: add dt nodes for mt7621-pll

This commit adds device-tree node for mt7621-pll and use its clocks accordingly. Signed-off-by: Chuanhong Guo --- Changes since v1: 1. drop cpuclock node in gbpc1.dts 2. drop syscon in mt7621-pll node drivers/staging/mt7621-dts/gbpc1.dts | 5 - drivers/staging/mt7621-dts/mt7621.dtsi

[PATCH v2 3/6] MIPS: ralink: add clock device providing cpu/bus clock for mt7621

-by: Weijie Gao Signed-off-by: Chuanhong Guo --- Changes since v1: 1. split patch. 2. calculate clocks using the function called by CLK_OF_DECLARE drop direct function call in timer-gic.c of ralink_clk_init 3. drop assignment of mips-hpt-frequency arch/mips/include/asm/mach-ralink/mt7621.h | 20

[PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

This commit adds device tree binding documentation for MT7621 PLL controller. Signed-off-by: Chuanhong Guo --- Change since v1: drop useless syscon in compatible string .../bindings/clock/mediatek,mt7621-pll.txt | 18 ++ 1 file changed, 18 insertions(+) create mode 100644

[PATCH v2 5/6] staging: mt7621-dts: fix register range of memc node in mt7621.dtsi

The memc node from mt7621.dtsi has incorrect register resource. Fix it according to the programming guide. Signed-off-by: Weijie Gao Signed-off-by: Chuanhong Guo --- Change since v1: None. drivers/staging/mt7621-dts/mt7621.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[PATCH v2 0/6] MIPS: ralink: add CPU clock detection for MT7621

and used it in mt7621-dts at drivers/staging. Changes since v1: 1. changed commit title prefix for dt include 2. split the patch adding clock node (details in that patch body) 3. drop useless syscon in dt documentation 4. drop cpuclock node for gbpc1 Chuanhong Guo (6): dt-bindings: clock: add dt

[PATCH v2 2/6] MIPS: ralink: drop ralink_clk_init for mt7621

This function isn't called anywhere. just drop it. Signed-off-by: Chuanhong Guo --- Change since v1: New patch. Split from: "MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices" arch/mips/ralink/mt7621.c | 43 --- 1 file changed, 43

[PATCH v2 1/6] dt-bindings: clock: add dt binding header for mt7621-pll

This patch adds dt binding header for mediatek,mt7621-pll Signed-off-by: Weijie Gao Signed-off-by: Chuanhong Guo Reviewed-by: Rob Herring --- Change since v1: Change commit title prefix. include/dt-bindings/clock/mt7621-clk.h | 14 ++ 1 file changed, 14 insertions(+) create mode

Re: [PATCH 4/5] staging: mt7621-dts: add dt nodes for mt7621-pll

On Wed, Jul 10, 2019 at 2:22 AM Chuanhong Guo wrote: > > This commit adds device-tree node for mt7621-pll and use its clock > accordingly. > > Signed-off-by: Chuanhong Guo Oops. Please ignore this single patch for now. I forgot to drop cpuclock node in drivers/staging/mt7621-dts

[PATCH 5/5] staging: mt7621-dts: fix register range of memc node in mt7621.dtsi

The memc node from mt7621.dtsi has incorrect register resource. Fix it according to the programming guide. Signed-off-by: Weijie Gao Signed-off-by: Chuanhong Guo --- drivers/staging/mt7621-dts/mt7621.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging

[PATCH 3/5] dt: bindings: add mt7621-pll dt binding documentation

This commit adds device tree binding documentation for MT7621 PLL controller. Signed-off-by: Chuanhong Guo --- .../bindings/clock/mediatek,mt7621-pll.txt| 19 +++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621

[PATCH 2/5] MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices

Signed-off-by: Weijie Gao Signed-off-by: Chuanhong Guo --- arch/mips/include/asm/mach-ralink/mt7621.h | 20 arch/mips/ralink/mt7621.c | 102 ++--- arch/mips/ralink/timer-gic.c | 4 +- 3 files changed, 93 insertions(+), 33 deletions(-) diff

[PATCH 4/5] staging: mt7621-dts: add dt nodes for mt7621-pll

This commit adds device-tree node for mt7621-pll and use its clock accordingly. Signed-off-by: Chuanhong Guo --- drivers/staging/mt7621-dts/mt7621.dtsi | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging

[PATCH 0/5] MIPS: ralink: add CPU clock detection for MT7621

and used it in mt7621-dts at drivers/staging. BTW: What should I do with such a patchset that touches multiple parts in kernel? Is it correct to send the entire patchset to lists of all involved subsystems? Chuanhong Guo (5): MIPS: ralink: add dt binding header for mt7621-pll MIPS: ralink: fix cpu

[PATCH 1/5] MIPS: ralink: add dt binding header for mt7621-pll

This patch adds dt binding header for mediatek,mt7621-pll Signed-off-by: Weijie Gao Signed-off-by: Chuanhong Guo Reviewed-by: Rob Herring --- include/dt-bindings/clock/mt7621-clk.h | 14 ++ 1 file changed, 14 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h

Re: [PATCH] MT7621-SPI: spi-mt7621: Fix alignment and style problems Fixed Coding function and style issues

t7621_spi(spi); > > if ((spi->max_speed_hz == 0) || > - (spi->max_speed_hz > (rs->sys_freq / 2))) > + (spi->max_speed_hz > (rs->sys_freq / 2))) > spi->max_speed_hz = (rs->sys_freq / 2); >

Re: [PATCH] spi: mediatek: Attempt to address style issues in spi-mt7621.c

n fixed by my two "drop broken spi modes" patches. > > John: do you have any more details of the problem other than what is in > the commit message? > > Thanks, > NeilBrown Regards, Chuanhong Guo ___ devel mailing list de...@li

Re: [PATCH] spi: mediatek: Attempt to address style issues in spi-mt7621.c

Hi! On Wed, Mar 13, 2019 at 8:28 PM Matthias Brugger wrote: > > > > On 13/03/2019 13:24, Armando Miraglia wrote: > [...] > Apart from fixing styling issues it would be usefull to see if we can add > support for mt7621 to drivers/spi/spi-mt65xx.c It's impossible. They are completely different IPs.

[PATCH v3 2/2] staging: mt7621-spi: drop support for SPI mode 1/2/3

RT2880_SPI_MODE_BITS macro because we now have only SPI_LSB_FIRST implemented and the mode_bits is so short that we don't need a macro there. Signed-off-by: Chuanhong Guo --- Change since v2: fixed the following checkpatch.pl complaining: CHECK: Please don't use multiple blank lines #45: FILE: drivers

[PATCH v3 0/2] staging: mt7621-spi: drop broken SPI modes

by checkpatch.pl Chuanhong Guo (2): staging: mt7621-spi: drop the broken full-duplex mode staging: mt7621-spi: drop support for SPI mode 1/2/3 drivers/staging/mt7621-spi/spi-mt7621.c | 147 1 file changed, 24 insertions(+), 123 deletions(-) -- 2.19.1

[PATCH v3 1/2] staging: mt7621-spi: drop the broken full-duplex mode

-duplex mode is broken. This piece of code also make CS1 unavailable since it forces the broken full-duplex mode to be used on CS1. Signed-off-by: Chuanhong Guo --- Change since v2: fixed the following checkpatch.pl complaining: ERROR: space required before the open parenthesis '(' #82: FILE: drivers

Re: [PATCH v2] staging: mt7621-spi: drop support for SPI mode 1/2/3

Chuanhong Guo 于2018年12月6日周四 下午7:19写道： > > As explained in previous patch, this SPI controller seems to be > tested on SPI flash only before mass production and some bits are > swizzled under other SPI modes probably due to incorrect wiring > inside the silicon. Drop implementation

Re: [PATCH v2] staging: mt7621-spi: drop the broken full-duplex mode

Chuanhong Guo 于2018年12月6日周四 下午7:19写道： > > According to John Crispin (aka blogic) on IRC on Nov 26 2018: > so basically i made cs1 work for MTK/labs when i built > the linkit smart for them. the req-sheet said that cs1 should be proper > duplex spi. however >1) th

[PATCH v2] staging: mt7621-spi: drop support for SPI mode 1/2/3

RT2880_SPI_MODE_BITS macro because we now have only SPI_LSB_FIRST implemented and the mode_bits is so short that we don't need a macro there. Signed-off-by: Chuanhong Guo --- Changes since v1: drop unspoorted modes from mode_bits instead of reject them in mt7621_spi_prepare. dropped RT2880_SPI_MODES_BITS

[PATCH v2] staging: mt7621-spi: drop the broken full-duplex mode

-duplex mode is broken. This piece of code also make CS1 unavailable since it forces the broken full-duplex mode to be used on CS1. Signed-off-by: Chuanhong Guo --- Changes since v1: Quoted John's reply in commit message slightly modified code comment drivers/staging/mt7621-spi/spi-mt7621.c | 120

Re: [PATCH] staging: mt7621-spi: drop the broken full-duplex mode

forgot to reply to mailing list... NeilBrown 于2018年12月5日周三 上午8:06写道： > > On Tue, Dec 04 2018, Chuanhong Guo wrote: > > > Hi! > > NeilBrown 于2018年12月4日周二 上午5:55写道： > >> > >> On Mon, Dec 03 2018, Chuanhong Guo wrote: > >> > >> > Unde

Re: [PATCH] staging: mt7621-spi: drop the broken full-duplex mode

Hi! NeilBrown 于2018年12月4日周二 上午5:55写道： > > On Mon, Dec 03 2018, Chuanhong Guo wrote: > > > Under MORE_BUF_MODE the controller will always shift one bit out of > > spi_opcode if (mosi_bit_cnt > 0) && (cmd_bit_cnt == 0) so the full- > > duplex mode is broken

[PATCH] staging: mt7621-spi: drop support for SPI mode 1/2/3

This SPI controller seems to be tested on SPI flash only before mass production and some bits are swizzled under other SPI modes probably due to incorrect wiring inside the silicon. Reject all modes except mode0 because they are broken. Signed-off-by: Chuanhong Guo --- drivers/staging/mt7621

[PATCH] staging: mt7621-spi: drop the broken full-duplex mode

the broken full-duplex mode to be enabled on CS1. Signed-off-by: Chuanhong Guo --- drivers/staging/mt7621-spi/spi-mt7621.c | 120 +++- 1 file changed, 15 insertions(+), 105 deletions(-) diff --git a/drivers/staging/mt7621-spi/spi-mt7621.c b/drivers/staging/mt7621-spi/spi-mt7