Re: [RFC PATCH v5] Xilinx AXI-Stream FIFO v4.1 IP core

On Wed, Aug 01, 2018 at 11:52:39AM +0300, Dan Carpenter wrote: > The README is empty... It should say what changes are needed to get > this out of staging. > > regards, > dan carpenter > Right :) It's ready as far as I'm concerned. Best, Jacob ___

[RFC PATCH v5] Xilinx AXI-Stream FIFO v4.1 IP core

- AXI4 (non-lite) Signed-off-by: Jacob Feder --- Added EOL Cheers, Jacob drivers/staging/Kconfig |2 + drivers/staging/Makefile|1 + drivers/staging/axis-fifo/Kconfig |9 + drivers/staging/axis-fifo/Makefile |1 + drivers/staging/axis

[RFC PATCH v4] Xilinx AXI-Stream FIFO v4.1 IP core driver

- AXI4 (non-lite) Signed-off-by: Jacob Feder --- Just had a typo in my makefile. It should be compiling correctly now with no warnings. Best, Jacob drivers/staging/Kconfig |2 + drivers/staging/Makefile|1 + drivers/staging/axis-fifo/Kconfig |9

Re: [RFC PATCH v3] Xilinx AXI-Stream FIFO v4.1 IP core driver

First I run "make menuconfig" and select my driver in "device drivers" > "staging". If I run "make" or "make all" or "make drivers/staging/axis-fifo" everything compiles without errors or warnings even if I put blatant syntax errors in my code. What am I missing here? Thanks, Jacob

[RFC PATCH v3] Xilinx AXI-Stream FIFO v4.1 IP core driver

mode with a 32-bit AXI4 Lite interface. DOES NOT support: - cut-through mode - AXI4 (non-lite) Signed-off-by: Jacob Feder --- drivers/staging/axisfifo/Kconfig |9 + drivers/staging/axisfifo/Makefile |1 + drivers/staging/axisfifo/axis-fifo.c | 1125

Re: [RFC PATCH v2] Xilinx AXI-Stream FIFO v4.1 IP core driver

On Mon, Jul 16, 2018 at 09:43:47AM +0200, Greg KH wrote: > On Sun, Jul 15, 2018 at 04:38:51PM -0400, Jacob Feder wrote: > > On Sun, Jul 15, 2018 at 09:44:58PM +0200, Greg KH wrote: > > > On Sun, Jul 15, 2018 at 12:34:28PM -0400, Jacob Feder wrote: > > > &

Re: [RFC PATCH v2] Xilinx AXI-Stream FIFO v4.1 IP core driver

On Sun, Jul 15, 2018 at 09:44:58PM +0200, Greg KH wrote: > On Sun, Jul 15, 2018 at 12:34:28PM -0400, Jacob Feder wrote: > > Hi, > > I have updated this with the recommended changes. I haven't tried out the > > UIO though. It will be a pretty significant undertaking and I do

[RFC PATCH v2] Xilinx AXI-Stream FIFO v4.1 IP core driver

-by: Jacob Feder --- Documentation/devicetree/bindings/axisfifo.txt | 89 ++ drivers/staging/axisfifo/axis-fifo.c | 1242 2 files changed, 1331 insertions(+) create mode 100644 Documentation/devicetree/bindings/axisfifo.txt create mode 100644 drivers/staging

Re: [RFC PATCH v1] Xilinx AXI-Stream FIFO v4.1 IP core driver

On Mon, Jul 09, 2018 at 05:25:21PM +0300, Dan Carpenter wrote: > On Sat, Jul 07, 2018 at 10:19:40PM -0400, Jacob Feder wrote: > > +static ssize_t sysfs_write(struct device *dev, const char *buf, > > + size_t count, unsigned int addr_offset) > &

Re: [RFC PATCH v1] Xilinx AXI-Stream FIFO v4.1 IP core driver

On Mon, Jul 09, 2018 at 09:43:28AM +0200, Greg KH wrote: > On Sun, Jul 08, 2018 at 02:25:38PM -0400, jacob feder wrote: > > On Sun, Jul 8, 2018 at 9:28 AM Greg KH wrote: > > > > On Sat, Jul 07, 2018 at 10:19:40PM -0400, Jacob Feder wrote: > > > Hi a

Re: [RFC PATCH v1] Xilinx AXI-Stream FIFO v4.1 IP core driver

On Sun, Jul 08, 2018 at 03:28:16PM +0200, Greg KH wrote: > On Sat, Jul 07, 2018 at 10:19:40PM -0400, Jacob Feder wrote: > > Hi all, > > I have developed this driver for a Xilinx-provided IP block for their Zynq > > SoC. I fixed all of the checkpatch.pl problems I knew how to.

[RFC PATCH v1] Xilinx AXI-Stream FIFO v4.1 IP core driver

that can be read/written to with standard open/read/write/close. See Xilinx PG080 document for IP details. Currently supports only store-forward mode with a 32-bit AXI4-Lite interface. DOES NOT support: - cut-through mode - AXI4 (non-lite) Signed-off-by: Jacob Feder --- drivers