Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

2019-08-18 Thread Oleksij Rempel
Am 18.08.19 um 10:44 schrieb Chuanhong Guo: > On Sun, Aug 18, 2019 at 4:26 PM Chuanhong Guo wrote: >> >> Hi! >> >> On Sun, Aug 18, 2019 at 3:59 PM Oleksij Rempel >> wrote: >>> >>> Am 18.08.19 um 09:19 schrieb Chuanhong Guo: >>>&g

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

2019-08-18 Thread Oleksij Rempel
Am 18.08.19 um 09:19 schrieb Chuanhong Guo: > Hi! > > On Sun, Aug 18, 2019 at 2:10 PM Oleksij Rempel wrote: >> >>>> We have at least 2 know registers: >>>> SYSC_REG_CPLL_CLKCFG0 - it provides some information about boostrapped >>>> refclock. PLL

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

2019-08-18 Thread Oleksij Rempel
Am 18.08.19 um 04:29 schrieb Chuanhong Guo: > Hi! > > On Sun, Aug 18, 2019 at 2:06 AM Oleksij Rempel wrote: >>>> SYSC_REG_CPLL_CLKCFG1 register is a clock gate controller. It is used to >>>> enable or disable clocks. >>>> Jist wild assumptio

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

2019-08-17 Thread Oleksij Rempel
Am 17.08.19 um 18:22 schrieb Chuanhong Guo: > Hi! > > On Sat, Aug 17, 2019 at 11:40 PM Oleksij Rempel wrote: > >> In provided link [0] the ralink_clk_init function is reading >> SYSC_REG_CPLL_CLKCFG0 R/W register. >> This register is used to determine clock sour

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

2019-08-17 Thread Oleksij Rempel
Hi, Am 17.08.19 um 16:42 schrieb Chuanhong Guo: Hi! On Tue, Aug 13, 2019 at 11:51 PM Rob Herring wrote: [...] +Example: + pll { + compatible = "mediatek,mt7621-pll"; You didn't answer Stephen's question on v1. I thought he was asking why there's a syscon in compatible

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

2019-08-17 Thread Oleksij Rempel
Hi, Am 17.08.19 um 16:42 schrieb Chuanhong Guo: Hi! On Tue, Aug 13, 2019 at 11:51 PM Rob Herring wrote: [...] +Example: + pll { + compatible = "mediatek,mt7621-pll"; You didn't answer Stephen's question on v1. I thought he was asking why there's a syscon in compatible

Re: Two rtlwifi drivers?

2017-10-16 Thread Oleksij Rempel
Am 16.10.2017 um 15:07 schrieb Kalle Valo: > Oleksij Rempel <li...@rempel-privat.de> writes: > >>> 4) As Kalle mentioned, rtlwifi contains many magic numbers, and I >>>plan to fix them after rtl8723de and rtl8821ce. Because the drivers >>>are de

Re: Two rtlwifi drivers?

2017-10-16 Thread Oleksij Rempel
Hi Just my two cents, :) Am 16.10.2017 um 04:41 schrieb Pkshih: > > >> -Original Message- >> From: Greg Kroah-Hartman [mailto:gre...@linuxfoundation.org] >> Sent: Thursday, October 12, 2017 6:35 PM >> To: Kalle Valo >> Cc: Larry Finger; Dan Carpenter; Pkshih; 莊彥宣; Johannes Berg;

Re: Ralink 6570 / Mediatek MT7601STA (was Re: Addition of a wifi kernel module to the linux source tree)

2014-12-04 Thread Oleksij Rempel
Am 04.12.2014 um 09:23 schrieb Stanislaw Gruszka: On Thu, Dec 04, 2014 at 03:52:52PM +1100, Julian Calaby wrote: On Thu, Dec 4, 2014 at 3:39 PM, Greg Kroah-Hartman gre...@linuxfoundation.org wrote: On Thu, Dec 04, 2014 at 07:07:58AM +0530, Parth Sane wrote: Hi, I'd say I'm midway through

Re: Ralink 6570 / Mediatek MT7601STA (was Re: Addition of a wifi kernel module to the linux source tree)

2014-12-04 Thread Oleksij Rempel
Am 04.12.2014 um 10:26 schrieb Parth Sane: Hi, Guys I'll be using my other account on my private domain laer.in now onwards. Be sure to add me in your contacts. My new email is parths...@laer.in -Parth On 4 December 2014 at 14:19, Oleksij Rempel li...@rempel-privat.de wrote: Am 04.12.2014

work on Alcor Micro AU6601

2014-03-13 Thread Oleksij Rempel
Hello all, i have a ultrabook with Alcor Micro AU6601 pcie card reader. Suddenly there is no driver for it, so i would like to make one. If i see it correctly, Alcor Micro don't wont to be contacted by any one except OEMs. I started collecting all possible information