[PATCH 0/7] Reorder i.MX IPU display enable/disable sequence

2014-04-14 Thread Philipp Zabel
Repeatedly enabling and disabling the display currently can lead to a state in which the IPU doesn't produce a valid signal anymore because we disable IPU submodules before they can finish their interaction. This series reorders the enable/disable sequence so that we first wait for the DC/DP to

Re: [PATCH 0/7] Reorder i.MX IPU display enable/disable sequence

2014-04-14 Thread Russell King - ARM Linux
On Mon, Apr 14, 2014 at 05:21:28PM +0200, Philipp Zabel wrote: Repeatedly enabling and disabling the display currently can lead to a state in which the IPU doesn't produce a valid signal anymore because we disable IPU submodules before they can finish their interaction. Well done at finding

Re: [PATCH 0/7] Reorder i.MX IPU display enable/disable sequence

2014-04-14 Thread Russell King - ARM Linux
On Mon, Apr 14, 2014 at 05:21:28PM +0200, Philipp Zabel wrote: Repeatedly enabling and disabling the display currently can lead to a state in which the IPU doesn't produce a valid signal anymore because we disable IPU submodules before they can finish their interaction. I'm afraid to say that