On Mon, Nov 04, 2019 at 01:20:09PM +0100, Greg KH wrote:
On Mon, Nov 04, 2019 at 07:22:20PM +0800, Jack Ping CHNG wrote:
This driver enables the Intel's LGM SoC GSWIP block.
GSWIP is a core module tailored for L2/L3/L4+ data plane and QoS functions.
It allows CPUs and other accelerators connecte
From: Greg KH
Date: Mon, 4 Nov 2019 13:20:09 +0100
> Why is this being submitted to staging? What is wrong with the "real"
> part of the kernel for this?
Agreed, this makes no sense at all.
___
devel mailing list
de...@linuxdriverproject.org
http://dr
On Mon, Nov 04, 2019 at 01:20:09PM +0100, Greg KH wrote:
> On Mon, Nov 04, 2019 at 07:22:20PM +0800, Jack Ping CHNG wrote:
> > This driver enables the Intel's LGM SoC GSWIP block.
> > GSWIP is a core module tailored for L2/L3/L4+ data plane and QoS functions.
> > It allows CPUs and other accelerato
On Mon, Nov 04, 2019 at 07:22:20PM +0800, Jack Ping CHNG wrote:
> This driver enables the Intel's LGM SoC GSWIP block.
> GSWIP is a core module tailored for L2/L3/L4+ data plane and QoS functions.
> It allows CPUs and other accelerators connected to the SoC datapath
> to enqueue and dequeue packets
