Re: [PATCH v2 4/7] staging: mt7621-pci: fix reset lines for each pcie port

2018-11-26 Thread Dan Carpenter
On Tue, Nov 27, 2018 at 01:12:42PM +1100, NeilBrown wrote: > On Tue, Nov 27 2018, Dan Carpenter wrote: > > > On Mon, Nov 26, 2018 at 08:57:09PM +0100, Sergio Paracuellos wrote: > >> On Mon, Nov 26, 2018 at 10:57 AM Dan Carpenter > >> wrote: > >> > > >> > On Sat, Nov 24, 2018 at 06:54:54PM

Re: [PATCH v2 4/7] staging: mt7621-pci: fix reset lines for each pcie port

2018-11-26 Thread NeilBrown
On Tue, Nov 27 2018, Dan Carpenter wrote: > On Mon, Nov 26, 2018 at 08:57:09PM +0100, Sergio Paracuellos wrote: >> On Mon, Nov 26, 2018 at 10:57 AM Dan Carpenter >> wrote: >> > >> > On Sat, Nov 24, 2018 at 06:54:54PM +0100, Sergio Paracuellos wrote: >> > > Depending of chip revision reset lines

Re: [PATCH v2 4/7] staging: mt7621-pci: fix reset lines for each pcie port

2018-11-26 Thread Dan Carpenter
On Mon, Nov 26, 2018 at 08:57:09PM +0100, Sergio Paracuellos wrote: > On Mon, Nov 26, 2018 at 10:57 AM Dan Carpenter > wrote: > > > > On Sat, Nov 24, 2018 at 06:54:54PM +0100, Sergio Paracuellos wrote: > > > Depending of chip revision reset lines are inverted. It is also > > > necessary to read

Re: [PATCH v2 4/7] staging: mt7621-pci: fix reset lines for each pcie port

2018-11-26 Thread Sergio Paracuellos
On Mon, Nov 26, 2018 at 10:57 AM Dan Carpenter wrote: > > On Sat, Nov 24, 2018 at 06:54:54PM +0100, Sergio Paracuellos wrote: > > Depending of chip revision reset lines are inverted. It is also > > necessary to read PCIE_FTS_NUM register before enabling the phy. > > Hence update the code to

Re: [PATCH v2 4/7] staging: mt7621-pci: fix reset lines for each pcie port

2018-11-26 Thread Dan Carpenter
On Sat, Nov 24, 2018 at 06:54:54PM +0100, Sergio Paracuellos wrote: > Depending of chip revision reset lines are inverted. It is also > necessary to read PCIE_FTS_NUM register before enabling the phy. > Hence update the code to achieve this. > > Fixes: 745eeeac68d7: "staging: mt7621-pci: factor

[PATCH v2 4/7] staging: mt7621-pci: fix reset lines for each pcie port

2018-11-24 Thread Sergio Paracuellos
Depending of chip revision reset lines are inverted. It is also necessary to read PCIE_FTS_NUM register before enabling the phy. Hence update the code to achieve this. Fixes: 745eeeac68d7: "staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function" Reported-by: NeilBrown Signed-off-by:

[PATCH v2 4/7] staging: mt7621-pci: fix reset lines for each pcie port

2018-11-24 Thread Sergio Paracuellos
Depending of chip revision reset lines are inverted. It is also necessary to read PCIE_FTS_NUM register before enabling the phy. Hence update the code to achieve this. Fixes: 745eeeac68d7: "staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function" Reported-by: NeilBrown Signed-off-by: