On Wed, Aug 01, 2018 at 11:52:39AM +0300, Dan Carpenter wrote:
> The README is empty... It should say what changes are needed to get
> this out of staging.
>
> regards,
> dan carpenter
>
Right :)
It's ready as far as I'm concerned.
Best,
Jacob
___
On Sun, Jul 22, 2018 at 09:27:37PM -0400, Jacob Feder wrote:
> This IP core has read and write AXI-Stream FIFOs, the contents of which can
> be accessed from the AXI4 memory-mapped interface. This is useful for
> transferring data from a processor into the FPGA fabric. The driver creates
> a
This IP core has read and write AXI-Stream FIFOs, the contents of which can
be accessed from the AXI4 memory-mapped interface. This is useful for
transferring data from a processor into the FPGA fabric. The driver creates
a character device that can be read/written to with standard
