Re: [PATCH v3 0/4] Improve VCHIQ cache line size handling

2018-11-06 Thread Stefan Wahren
> Phil Elwell hat am 17. September 2018 um 20:01 > geschrieben: > > > On 17/09/2018 18:51, Florian Fainelli wrote: > > On 09/17/2018 04:47 AM, Phil Elwell wrote: > >> Hi Stefan, > >> > >> On 17/09/2018 12:39, Stefan Wahren wrote: > >>> Hi Phil, > >>> > >>> Am 17.09.2018 um 10:22 schrieb Phil

Re: [PATCH v3 0/4] Improve VCHIQ cache line size handling

2018-09-17 Thread Phil Elwell
On 17/09/2018 18:51, Florian Fainelli wrote: On 09/17/2018 04:47 AM, Phil Elwell wrote: Hi Stefan, On 17/09/2018 12:39, Stefan Wahren wrote: Hi Phil, Am 17.09.2018 um 10:22 schrieb Phil Elwell: Both sides of the VCHIQ communications mechanism need to agree on the cache line size. Using an

Re: [PATCH v3 0/4] Improve VCHIQ cache line size handling

2018-09-17 Thread Florian Fainelli
On 09/17/2018 04:47 AM, Phil Elwell wrote: > Hi Stefan, > > On 17/09/2018 12:39, Stefan Wahren wrote: >> Hi Phil, >> >> Am 17.09.2018 um 10:22 schrieb Phil Elwell: >>> Both sides of the VCHIQ communications mechanism need to agree on the cache >>> line size. Using an incorrect value can lead to

Re: [PATCH v3 0/4] Improve VCHIQ cache line size handling

2018-09-17 Thread Phil Elwell
Hi Stefan, On 17/09/2018 12:39, Stefan Wahren wrote: > Hi Phil, > > Am 17.09.2018 um 10:22 schrieb Phil Elwell: >> Both sides of the VCHIQ communications mechanism need to agree on the cache >> line size. Using an incorrect value can lead to data corruption, but having >> the >> two sides using

Re: [PATCH v3 0/4] Improve VCHIQ cache line size handling

2018-09-17 Thread Stefan Wahren
Hi Phil, Am 17.09.2018 um 10:22 schrieb Phil Elwell: > Both sides of the VCHIQ communications mechanism need to agree on the cache > line size. Using an incorrect value can lead to data corruption, but having > the > two sides using different values is usually worse. > > In the absence of an