Re: [PATCH] staging: comedi: cast to (void __user *)

On Thu, Feb 18, 2021 at 11:58:40AM +0530, Atul Gopinathan wrote: > Resolve the following sparse warning: > drivers/staging//comedi/comedi_fops.c:2983:41: warning: incorrect type in > argument 1 (different address spaces) > drivers/staging//comedi/comedi_fops.c:2983:41:expected void [noderef]

[PATCH v7 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L:

[PATCH v7 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml' contains 'mediatek' as a valid vendor string. Some nodes in the device tree are using an invalid vendor string vfor 'mtk' instead. Fix all of them in dts file. Update also ralink mt7621 related code to properly match new

[PATCH v7 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

This patchset ports CPU clock detection for MT7621 from OpenWrt and adds a complete clock plan for the mt7621 SOC. The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and

[PATCH v7 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git

[PATCH v1 03/18] arm64: dts: imx8mq-evk: add reserve memory node for CMA region

Define allocation range for the default CMA region. Signed-off-by: Benjamin Gaignard Signed-off-by: Ezequiel Garcia Signed-off-by: Adrian Ratiu --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 15 +++ 1 file changed, 15 insertions(+) diff --git

Re: [PATCH v1 00/18] Add HANTRO G2/HEVC decoder support for IMX8MQ

On Wed, Feb 17, 2021 at 09:28:09AM +0100, Benjamin Gaignard wrote: > > Le 17/02/2021 à 09:08, Greg KH a écrit : > > On Wed, Feb 17, 2021 at 09:02:48AM +0100, Benjamin Gaignard wrote: > > > The IMX8MQ got two VPUs but until now only G1 has been enabled. > > > This series aim to add the second VPU

[PATCH v1 13/18] media: hantro: Introduce G2/HEVC decoder

Implement all the logic to get G2 hardware decoding HEVC frames. It support up level 5.1 HEVC stream. It doesn't support yet 10 bits formats or scaling feature. Add HANTRO HEVC dedicated control to skip some bits at the beginning of the slice header. That is very specific to this hardware so

[PATCH v1 16/18] media: hantro: IMX8M: add variant for G2/HEVC codec

Add variant to IMX8M to enable G2/HEVC codec. Define the capabilities for the hardware up to 3840x2160. Retrieve the hardware version at init to distinguish G1 from G2. Signed-off-by: Benjamin Gaignard Signed-off-by: Ezequiel Garcia Signed-off-by: Adrian Ratiu ---

[PATCH v7 3/6] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS. * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or

[PATCH v7 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v7 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++ 1 file changed, 66 insertions(+) create mode 100644

Re: [PATCH v7 3/6] clk: ralink: add clock driver for mt7621 SoC

patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Sergio-Paracuellos/MIPS-ralink-add-CPU-clock-detection-and-clock-driver-for-MT7621/20210217-194316 base: https://git.kernel.org/pub/scm/linux/kernel/git

Re: [PATCH] staging: emxx_udc: remove unused variable driver_desc

On Wed, Feb 17, 2021 at 09:24:17AM -0500, Sean Behan wrote: > When building with W=1, there is a warning that this variable is unused. > > It is not used so remove it to fix the warning. > > Thanks to nat...@kernel.org for helping me submit my first patch. This is nice, but is it needed in the

[PATCH] drivers: staging: comedi: Fixed side effects from macro definition.

Warning found by checkpatch.pl script. Signed-off-by: chakravarthikulkarni --- drivers/staging/comedi/comedi.h | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/staging/comedi/comedi.h b/drivers/staging/comedi/comedi.h index b5d00a006dbb..b2af6a88d389 100644

[PATCH] staging: emxx_udc: remove unused variable driver_desc

When building with W=1 (or however you found it), there is a warning that this variable is unused. It is not used so remove it to fix the warning. Signed-off-by: Sean Behan --- drivers/staging/emxx_udc/emxx_udc.c | 1 - 1 file changed, 1 deletion(-) diff --git

[PATCH] staging: emxx_udc: remove unused variable driver_desc

When building with W=1, there is a warning that this variable is unused. It is not used so remove it to fix the warning. Thanks to nat...@kernel.org for helping me submit my first patch. Signed-off-by: Sean Behan --- drivers/staging/emxx_udc/emxx_udc.c | 1 - 1 file changed, 1 deletion(-)

[PATCH v8 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git

[PATCH v8 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++ 1 file changed, 66 insertions(+) create mode 100644

[PATCH v8 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v8 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L:

[PATCH v8 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

This patchset ports CPU clock detection for MT7621 from OpenWrt and adds a complete clock plan for the mt7621 SOC. The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and

[PATCH v8 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml' contains 'mediatek' as a valid vendor string. Some nodes in the device tree are using an invalid vendor string vfor 'mtk' instead. Fix all of them in dts file. Update also ralink mt7621 related code to properly match new

[PATCH v8 3/6] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS. * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or

Re: [PATCH] staging: gasket Fix comparision with Null

On Wed, Feb 17, 2021 at 06:58:16PM +0530, mayanksu...@live.com wrote: > From: Mayank Suman > > The change was suggested by checkpatch.pl. What change? Please read the section entitled "The canonical patch format" in the kernel file, Documentation/SubmittingPatches for a description of how to

[PATCH] staging: gasket Fix comparision with Null

From: Mayank Suman The change was suggested by checkpatch.pl. Signed-off-by: Mayank Suman --- drivers/staging/gasket/gasket_sysfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/gasket/gasket_sysfs.c b/drivers/staging/gasket/gasket_sysfs.c index

Re: [PATCH] staging: wlan-ng: Fixed incorrect type warning in p80211netdev.c

On Wed, Feb 17, 2021 at 09:12:55PM +0530, Pritthijit Nath wrote: > This change fixes a sparse warning "incorrect type in argument 1 > (different address spaces)". > > Signed-off-by: Pritthijit Nath > --- > drivers/staging/wlan-ng/p80211netdev.c | 2 +- > 1 file changed, 1 insertion(+), 1

[PATCH] staging: comedi: cast to (unsigned int *)

Resolve the following warning generated by sparse: drivers/staging//comedi/comedi_fops.c:2956:23: warning: incorrect type in assignment (different address spaces) drivers/staging//comedi/comedi_fops.c:2956:23:expected unsigned int *chanlist drivers/staging//comedi/comedi_fops.c:2956:23:

Re: [PATCH] staging: comedi: cast to (unsigned int *)

On Wed, Feb 17, 2021 at 06:35:15PM +0100, Greg KH wrote: > On Wed, Feb 17, 2021 at 10:29:08PM +0530, Atul Gopinathan wrote: > > Resolve the following warning generated by sparse: > > > > drivers/staging//comedi/comedi_fops.c:2956:23: warning: incorrect type in > > assignment (different address

[PATCH 0/3] staging: rtl8192e: sequence_control union cleanups

This patchset fixes the checkpatch issues related to the `sequence_control` union defined in `rtl8192e/rtl819x_BA.h` (avoid camelcase). William Durand (3): staging: rtl8192e: rename ShortData to short_data in sequence_control union staging: rtl8192e: rename FragNum to frag_num in

[PATCH 2/3] staging: rtl8192e: rename FragNum to frag_num in sequence_control union

Fixes a checkpatch CHECK message. Signed-off-by: William Durand --- drivers/staging/rtl8192e/rtl819x_BA.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/rtl8192e/rtl819x_BA.h b/drivers/staging/rtl8192e/rtl819x_BA.h index 34d66b8f5155..3e5bd3fc78ce 100644

[PATCH 1/3] staging: rtl8192e: rename ShortData to short_data in sequence_control union

Fixes a checkpatch CHECK message. Signed-off-by: William Durand --- drivers/staging/rtl8192e/rtl819x_BA.h | 2 +- drivers/staging/rtl8192e/rtl819x_BAProc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/rtl8192e/rtl819x_BA.h

[PATCH 3/3] staging: rtl8192e: rename SeqNum to seq_num in sequence_control union

Fixes a checkpatch CHECK message. Signed-off-by: William Durand --- drivers/staging/rtl8192e/rtl819x_BA.h | 2 +- drivers/staging/rtl8192e/rtl819x_BAProc.c | 2 +- drivers/staging/rtl8192e/rtllib_tx.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git

[driver-core:debugfs_remove_return_value 2/8] drivers/net/wireless/broadcom/b43/debugfs.c:661:28: error: void value not ignored as it ought to be

tree: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git debugfs_remove_return_value head: 5187c2360ee1d023078e4302dad32fda1e895772 commit: 72f2bf74b31aae983fb200aa7e84a05943bf27fc [2/8] debugfs: remove return value of debugfs_create_bool() config:

Re: [PATCH] staging: wlan-ng: Fixed incorrect type warning in p80211netdev.c

On 17/02/21 9:23 pm, Greg KH wrote: > On Wed, Feb 17, 2021 at 09:12:55PM +0530, Pritthijit Nath wrote: >> This change fixes a sparse warning "incorrect type in argument 1 >> (different address spaces)". >> >> Signed-off-by: Pritthijit Nath >> --- >> drivers/staging/wlan-ng/p80211netdev.c | 2 +-

[PATCH] staging: wlan-ng: Fixed incorrect type warning in p80211netdev.c

This change fixes a sparse warning "incorrect type in argument 1 (different address spaces)". Signed-off-by: Pritthijit Nath --- drivers/staging/wlan-ng/p80211netdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/wlan-ng/p80211netdev.c

Re: [PATCH v1 13/18] media: hantro: Introduce G2/HEVC decoder

Hi Benjamin, Before I review the implementation in detail, there's one thing that looks suspicious. On Wed, 2021-02-17 at 09:03 +0100, Benjamin Gaignard wrote: > Implement all the logic to get G2 hardware decoding HEVC frames. > It support up level 5.1 HEVC stream. > It doesn't support yet 10

Re: [PATCH] staging: comedi: cast to (unsigned int *)

On Wed, Feb 17, 2021 at 11:40:00PM +0530, Atul Gopinathan wrote: > On Wed, Feb 17, 2021 at 06:35:15PM +0100, Greg KH wrote: > > On Wed, Feb 17, 2021 at 10:29:08PM +0530, Atul Gopinathan wrote: > > > Resolve the following warning generated by sparse: > > > > > >

Re: [PATCH] staging: comedi: cast to (unsigned int *)

On Wed, Feb 17, 2021 at 10:29:08PM +0530, Atul Gopinathan wrote: > Resolve the following warning generated by sparse: > > drivers/staging//comedi/comedi_fops.c:2956:23: warning: incorrect type in > assignment (different address spaces) > drivers/staging//comedi/comedi_fops.c:2956:23:expected

Re: [PATCH v4 3/3] drm/bridge: anx7625: add MIPI DPI input feature support

On Fri, Feb 05, 2021 at 01:33:46PM +0100, Robert Foss wrote: > Hey Xin, Hi Robert Foss, thanks for the comment, I'll split this patch at this seria. Thanks, Xin > > On Thu, 28 Jan 2021 at 04:12, Xin Ji wrote: > > > > Add MIPI rx DPI input support > > > > Reported-by: kernel test robot > >

[PATCH] staging: comedi: cast to (void __user *)

Resolve the following sparse warning: drivers/staging//comedi/comedi_fops.c:2983:41: warning: incorrect type in argument 1 (different address spaces) drivers/staging//comedi/comedi_fops.c:2983:41:expected void [noderef] *uptr drivers/staging//comedi/comedi_fops.c:2983:41:got unsigned

[PATCH v9 3/6] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS. * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or

[PATCH v9 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v9 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml' contains 'mediatek' as a valid vendor string. Some nodes in the device tree are using an invalid vendor string vfor 'mtk' instead. Fix all of them in dts file. Update also ralink mt7621 related code to properly match new

[PATCH v9 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

This patchset ports CPU clock detection for MT7621 from OpenWrt and adds a complete clock plan for the mt7621 SOC. The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and

[PATCH v9 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git

[PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++ 1 file changed, 66 insertions(+) create mode 100644

[PATCH v9 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L: