Re: [PATCH v6 4/8] media: platform: Add Cedrus VPU decoder driver
On Wed, 2018-07-25 at 12:02 +0200, Paul Kocialkowski wrote:
> This introduces the Cedrus VPU driver that supports the VPU found in
> Allwinner SoCs, also known as Video Engine. It is implemented through
> a v4l2 m2m decoder device and a media device (used for media requests).
> So far, it only supports MPEG2 decoding.
>
> Since this VPU is stateless, synchronization with media requests is
> required in order to ensure consistency between frame headers that
> contain metadata about the frame to process and the raw slice data that
> is used to generate the frame.
>
> This driver was made possible thanks to the long-standing effort
> carried out by the linux-sunxi community in the interest of reverse
> engineering, documenting and implementing support for Allwinner VPU.
>
> Signed-off-by: Paul Kocialkowski
[..]
> +static int cedrus_probe(struct platform_device *pdev)
> +{
> + struct cedrus_dev *dev;
> + struct video_device *vfd;
> + int ret;
> +
> + dev = devm_kzalloc(>dev, sizeof(*dev), GFP_KERNEL);
> + if (!dev)
> + return -ENOMEM;
> +
> + dev->dev = >dev;
> + dev->pdev = pdev;
> +
> + ret = cedrus_hw_probe(dev);
> + if (ret) {
> + dev_err(>dev, "Failed to probe hardware\n");
> + return ret;
> + }
> +
> + dev->dec_ops[CEDRUS_CODEC_MPEG2] = _dec_ops_mpeg2;
> +
> + mutex_init(>dev_mutex);
> + spin_lock_init(>irq_lock);
> +
A minor thing.
I believe this spinlock is not needed. All the data structures
it's accessing are already protected, and some operations
(stop_streaming) are guaranteed to not run at the same
time as a job.
Regards,
Eze
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Re: [PATCH net-next] [RFC] dpaa2-eth: Move DPAA2 Ethernet driver from staging to drivers/net
> +static int dpaa2_eth_probe(struct fsl_mc_device *dpni_dev)
> +{
> + struct device *dev;
> + struct net_device *net_dev = NULL;
> + struct dpaa2_eth_priv *priv = NULL;
> + int err = 0;
> +
> + dev = _dev->dev;
> +
> + /* Net device */
> + net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA2_ETH_MAX_TX_QUEUES);
> + if (!net_dev) {
> + dev_err(dev, "alloc_etherdev_mq() failed\n");
> + return -ENOMEM;
> + }
> +
> + SET_NETDEV_DEV(net_dev, dev);
> + dev_set_drvdata(dev, net_dev);
> +
> + priv = netdev_priv(net_dev);
> + priv->net_dev = net_dev;
> +
> + priv->iommu_domain = iommu_get_domain_for_dev(dev);
> +
> + /* Obtain a MC portal */
> + err = fsl_mc_portal_allocate(dpni_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL,
> + >mc_io);
> + if (err) {
> + if (err == -ENXIO)
> + err = -EPROBE_DEFER;
> + else
> + dev_err(dev, "MC portal allocation failed\n");
> + goto err_portal_alloc;
> + }
> +
> + /* MC objects initialization and configuration */
> + err = setup_dpni(dpni_dev);
> + if (err)
> + goto err_dpni_setup;
> +
> + err = setup_dpio(priv);
> + if (err)
> + goto err_dpio_setup;
> +
> + setup_fqs(priv);
> +
> + err = setup_dpbp(priv);
> + if (err)
> + goto err_dpbp_setup;
> +
> + err = bind_dpni(priv);
> + if (err)
> + goto err_bind;
> +
> + /* Add a NAPI context for each channel */
> + add_ch_napi(priv);
> +
> + /* Percpu statistics */
> + priv->percpu_stats = alloc_percpu(*priv->percpu_stats);
> + if (!priv->percpu_stats) {
> + dev_err(dev, "alloc_percpu(percpu_stats) failed\n");
> + err = -ENOMEM;
> + goto err_alloc_percpu_stats;
> + }
> + priv->percpu_extras = alloc_percpu(*priv->percpu_extras);
> + if (!priv->percpu_extras) {
> + dev_err(dev, "alloc_percpu(percpu_extras) failed\n");
> + err = -ENOMEM;
> + goto err_alloc_percpu_extras;
> + }
> +
> + err = netdev_init(net_dev);
> + if (err)
> + goto err_netdev_init;
At the end of netdev_init() you call netdev_register(). From that
point on, you device is live. Its .ndo's can be called
> +
> + /* Configure checksum offload based on current interface flags */
> + err = set_rx_csum(priv, !!(net_dev->features & NETIF_F_RXCSUM));
> + if (err)
> + goto err_csum;
> +
> + err = set_tx_csum(priv, !!(net_dev->features &
> +(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)));
> + if (err)
> + goto err_csum;
> +
> + err = alloc_rings(priv);
> + if (err)
> + goto err_alloc_rings;
How well does the device work if it has not allocated the rings yet,
when it is asked to do something?
> +
> + net_dev->ethtool_ops = _ethtool_ops;
> +
> + err = setup_irqs(dpni_dev);
How well do it work without interrupts being set up?
> + if (err) {
> + netdev_warn(net_dev, "Failed to set link interrupt, fall back
> to polling\n");
> + priv->poll_thread = kthread_run(poll_link_state, priv,
> + "%s_poll_link", net_dev->name);
> + if (IS_ERR(priv->poll_thread)) {
> + netdev_err(net_dev, "Error starting polling thread\n");
> + goto err_poll_thread;
> + }
> + priv->do_link_poll = true;
> + }
Probably the correct place to register the netdev is here.
Andrew
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Re: [PATCH] staging/vc04_services: Use __user annotation for user-space pointers
Hi Carlos, > Carlos Maiolino hat am 30. Juli 2018 um 11:57 > geschrieben: > > > On Mon, Jul 30, 2018 at 11:49 AM, Stefan Wahren > wrote: > > Am 30.07.2018 um 11:43 schrieb Carlos Maiolino: > >> On Mon, Jul 30, 2018 at 11:34 AM, Stefan Wahren > >> wrote: > >>> i think easiest the way would be to get a recent Raspbian Lite ( > >>> https://www.raspberrypi.org/downloads/raspbian/ ), > >>> build the kernel with bcm2835_defconfig, modify config.txt to use the > >>> upstream DTB, add the upstream kernel and DTB to boot partition. > >>> > >>> The following command must be successful: > >>> > >>> vchiq_test -f 1 > >> K, I'll take a look and find a way to test it, I don't have a rPI at > >> the moment to test > >> it, I'll take a look if I can borrow one. in mean time, can it be > >> tested somehow in x86 environment? > > > > I don't see a chance because this driver talks to the VC4 firmware. > > > > kk > > thx i only want to point out that there was a regression (deadlock) in linux-next, which has been reverted [1] / fixed. [1] - https://lkml.org/lkml/2018/8/2/578 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
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Spende
Hallo, ich bin Herr Tayeb Souami, New Jersey, Vereinigte Staaten von Amerika, Sie haben eine Wohltätigkeitsspende in Höhe von € 2.000.000,00, ich habe die America Lotterie in Amerika im Wert von $ 315 Millionen gewonnen, und ich gebe einen Teil davon an fünf glückliche Menschen und wohltätige Häuser, um Armut aus dieser Welt zu beseitigen, bekämpfe ich die Armut. Kontaktieren Sie mich für weitere Informationen: wumt.claimserv...@gmail.com Das ist dein Spendencode: [DFC530342018] Antworten Sie mit dem Spendencode auf diese E-Mail: wumt.claimserv...@gmail.com Ich hoffe, Sie und Ihre Familie glücklich zu machen. Grüße Herr Tayeb Souami ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v6 00/13] media: staging/imx7: add i.MX7 media driver
On 08/02/18 18:45, Rui Miguel Silva wrote: > Hi Hans, > On Thu 02 Aug 2018 at 13:37, Hans Verkuil wrote: >> Hi Rui, >> >> On 05/22/18 16:52, Rui Miguel Silva wrote: >>> Hi, >>> This series introduces the Media driver to work with the i.MX7 >>> SoC. it uses the >>> already existing imx media core drivers but since the i.MX7, >>> contrary to >>> i.MX5/6, do not have an IPU and because of that some changes in >>> the imx media >>> core are made along this series to make it support that case. >>> >>> This patches adds CSI and MIPI-CSI2 drivers for i.MX7, along >>> with several >>> configurations changes for this to work as a capture subsystem. >>> Some bugs are >>> also fixed along the line. And necessary documentation. >>> >>> For a more detailed view of the capture paths, pads links in >>> the i.MX7 please >>> take a look at the documentation in PATCH 14. >>> >>> The system used to test and develop this was the Warp7 board >>> with an OV2680 >>> sensor, which output format is 10-bit bayer. So, only MIPI >>> interface was >>> tested, a scenario with an parallel input would nice to have. >>> >>> *Important note*, this code depends on Steve Longerbeam series >>> [0]: >>> [PATCH v4 00/13] media: imx: Switch to subdev notifiers >>> which the merging status is not clear to me, but the changes in >>> there make >>> senses to this series >>> >>> Bellow goes an example of the output of the pads and links and >>> the output of >>> v4l2-compliance testing. >>> >>> The v4l-utils version used is: >>> v4l2-compliance SHA : >>> 47d43b130dc6e9e0edc900759fb37649208371e4 from Apr 4th. >>> >>> The Media Driver fail some tests but this failures are coming >>> from code out of >>> scope of this series (video-mux, imx-capture), and some from >>> the sensor OV2680 >>> but that I think not related with the sensor driver but with >>> the testing and >>> core. >>> >>> The csi and mipi-csi entities pass all compliance tests. >>> >>> Cheers, >>> Rui >>> >>> [0]: >>> https://www.mail-archive.com/linux-media@vger.kernel.org/msg131186.html >> >> This patch series was delayed quite a bit since the patch series >> above >> it depends on is still not merged. >> >> But the v6 version of that series will be merged once the 4.20 >> cycle opens: >> https://www.mail-archive.com/linux-media@vger.kernel.org/msg133391.html > > Good news. > >> >> Sakari has a branch with that series on top of the latest >> media_tree master: >> https://git.linuxtv.org/sailus/media_tree.git/log/?h=v4l2-fwnode >> >> Can you rebase this imx7 series on top of that? And test it >> again with the >> *latest* v4l2-compliance? (I've added new checks recently, so >> you need to >> update this utility) >> >> Please post the output of the v4l2-compliance test (after fixing >> any issues >> it raises of course), either as a reply to this post or in the >> cover letter >> of a v7 version of this series if you had to make changes. > > Sure, I will rebase on top of Sakari tree and will update the > compliance > tests and run them again. Oops, forgot to mention: you will likely need to update the include/linux/media.h header: Look for MEDIA_V2_ENTITY_HAS_FLAGS and MEDIA_V2_PAD_HAS_INDEX and change 19 to 18 in those defines. This is added for kernel 4.19, but since in our master tree the kernel version is still 4.18 the v4l2-compliance utility thinks these features are not present when in fact they are. Without this change (temporarily since this will automatically be fixed after the 4.19 merge window closes) v4l2-compliance will fail with an error. Regards, Hans ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH 3/3] staging: wilc1000: remove TODO item for comments and code style
Remove below item from TODO as these changes were included as part of previous submitted patch series. 'rework comments and function headers(also coding style)' Signed-off-by: Ajay Singh --- drivers/staging/wilc1000/TODO | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/staging/wilc1000/TODO b/drivers/staging/wilc1000/TODO index 6fd3a4c..862e9ea 100644 --- a/drivers/staging/wilc1000/TODO +++ b/drivers/staging/wilc1000/TODO @@ -1,4 +1,3 @@ TODO: -- rework comments and function headers(also coding style) - support soft-ap and p2p mode - support resume/suspend function -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH 1/3] staging: wilc1000: added Microchip copyright notice header
Cleanup the copyright notice header from the WILC1000 files.
Replace copyright header of 'Atmel' & 'NewportMedia' with 'Microchip & its
subsidiaries'. Also added the same copyright notice header for all
wilc1000 driver source and header files.
Signed-off-by: Ajay Singh
---
drivers/staging/wilc1000/coreconfigurator.c | 5 +
drivers/staging/wilc1000/coreconfigurator.h | 5 +
drivers/staging/wilc1000/host_interface.c | 5 +
drivers/staging/wilc1000/host_interface.h | 5 +
drivers/staging/wilc1000/linux_mon.c | 5 +
drivers/staging/wilc1000/linux_wlan.c | 5 +
drivers/staging/wilc1000/wilc_debugfs.c | 10 ++
drivers/staging/wilc1000/wilc_sdio.c | 5 ++---
drivers/staging/wilc1000/wilc_spi.c | 5 ++---
drivers/staging/wilc1000/wilc_wfi_cfgoperations.c | 5 +
drivers/staging/wilc1000/wilc_wfi_cfgoperations.h | 5 +
drivers/staging/wilc1000/wilc_wfi_netdevice.h | 5 +
drivers/staging/wilc1000/wilc_wlan.c | 5 +
drivers/staging/wilc1000/wilc_wlan.h | 5 +
drivers/staging/wilc1000/wilc_wlan_cfg.c | 12
drivers/staging/wilc1000/wilc_wlan_cfg.h | 12
drivers/staging/wilc1000/wilc_wlan_if.h | 12
17 files changed, 73 insertions(+), 38 deletions(-)
diff --git a/drivers/staging/wilc1000/coreconfigurator.c
b/drivers/staging/wilc1000/coreconfigurator.c
index e09f10d..e542067 100644
--- a/drivers/staging/wilc1000/coreconfigurator.c
+++ b/drivers/staging/wilc1000/coreconfigurator.c
@@ -1,4 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
+ * All rights reserved.
+ */
+
#include
#include "coreconfigurator.h"
diff --git a/drivers/staging/wilc1000/coreconfigurator.h
b/drivers/staging/wilc1000/coreconfigurator.h
index 90d3d65..b62acb4 100644
--- a/drivers/staging/wilc1000/coreconfigurator.h
+++ b/drivers/staging/wilc1000/coreconfigurator.h
@@ -1,4 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
+ * All rights reserved.
+ */
+
#ifndef CORECONFIGURATOR_H
#define CORECONFIGURATOR_H
diff --git a/drivers/staging/wilc1000/host_interface.c
b/drivers/staging/wilc1000/host_interface.c
index 86d8aaf..42d8acc 100644
--- a/drivers/staging/wilc1000/host_interface.c
+++ b/drivers/staging/wilc1000/host_interface.c
@@ -1,4 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
+ * All rights reserved.
+ */
+
#include "wilc_wfi_netdevice.h"
#define HOST_IF_SCAN_TIMEOUT4000
diff --git a/drivers/staging/wilc1000/host_interface.h
b/drivers/staging/wilc1000/host_interface.h
index 3ddeec2..84866a6 100644
--- a/drivers/staging/wilc1000/host_interface.h
+++ b/drivers/staging/wilc1000/host_interface.h
@@ -1,4 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries
+ * All rights reserved.
+ */
+
#ifndef HOST_INT_H
#define HOST_INT_H
#include
diff --git a/drivers/staging/wilc1000/linux_mon.c
b/drivers/staging/wilc1000/linux_mon.c
index 9d12a91..1afdb9e 100644
--- a/drivers/staging/wilc1000/linux_mon.c
+++ b/drivers/staging/wilc1000/linux_mon.c
@@ -1,4 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
+ * All rights reserved.
+ */
+
#include "wilc_wfi_cfgoperations.h"
struct wilc_wfi_radiotap_hdr {
diff --git a/drivers/staging/wilc1000/linux_wlan.c
b/drivers/staging/wilc1000/linux_wlan.c
index c9e771a..01cf4bd 100644
--- a/drivers/staging/wilc1000/linux_wlan.c
+++ b/drivers/staging/wilc1000/linux_wlan.c
@@ -1,4 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
+ * All rights reserved.
+ */
+
#include
#include
#include
diff --git a/drivers/staging/wilc1000/wilc_debugfs.c
b/drivers/staging/wilc1000/wilc_debugfs.c
index ac26e94..edc7287 100644
--- a/drivers/staging/wilc1000/wilc_debugfs.c
+++ b/drivers/staging/wilc1000/wilc_debugfs.c
@@ -1,13 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * NewportMedia WiFi chipset driver test tools - wilc-debug
- * Copyright (c) 2012 NewportMedia Inc.
- * Author: SSW
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
+ * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
+ * All rights reserved.
*/
#if defined(WILC_DEBUGFS)
diff --git a/drivers/staging/wilc1000/wilc_sdio.c
b/drivers/staging/wilc1000/wilc_sdio.c
index 8bda550..d5f904d 100644
--- a/drivers/staging/wilc1000/wilc_sdio.c
[PATCH 2/3] staging: wilc1000: replace ISWILC1000() macro with inline function
Cleanup patch to avoid below checkpatch issue by replacing the macro
with inline function.
Macro argument 'id' may be better as '(id)' to avoid precedence issues.
Signed-off-by: Ajay Singh
---
drivers/staging/wilc1000/wilc_wlan.c | 9 +++--
drivers/staging/wilc1000/wilc_wlan.h | 2 --
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/wilc1000/wilc_wlan.c
b/drivers/staging/wilc1000/wilc_wlan.c
index cd27352..6787b6e 100644
--- a/drivers/staging/wilc1000/wilc_wlan.c
+++ b/drivers/staging/wilc1000/wilc_wlan.c
@@ -11,6 +11,11 @@
static enum chip_ps_states chip_ps_state = CHIP_WAKEDUP;
+static inline bool is_wilc1000(u32 id)
+{
+ return ((id & 0xf000) == 0x10 ? true : false);
+}
+
static inline void acquire_bus(struct wilc *wilc, enum bus_acquire acquire)
{
mutex_lock(>hif_cs);
@@ -794,7 +799,7 @@ static void wilc_pllupdate_isr_ext(struct wilc *wilc, u32
int_stats)
else
mdelay(WILC_PLL_TO_SPI);
- while (!(ISWILC1000(wilc_get_chipid(wilc, true)) && --trials))
+ while (!(is_wilc1000(wilc_get_chipid(wilc, true)) && --trials))
mdelay(1);
}
@@ -1294,7 +1299,7 @@ u32 wilc_get_chipid(struct wilc *wilc, bool update)
if (chipid == 0 || update) {
wilc->hif_func->hif_read_reg(wilc, 0x1000, );
wilc->hif_func->hif_read_reg(wilc, 0x13f4, );
- if (!ISWILC1000(tempchipid)) {
+ if (!is_wilc1000(tempchipid)) {
chipid = 0;
return chipid;
}
diff --git a/drivers/staging/wilc1000/wilc_wlan.h
b/drivers/staging/wilc1000/wilc_wlan.h
index 1a4ac49..7467188 100644
--- a/drivers/staging/wilc1000/wilc_wlan.h
+++ b/drivers/staging/wilc1000/wilc_wlan.h
@@ -9,8 +9,6 @@
#include
-#define ISWILC1000(id) ((id & 0xf000) == 0x10 ? 1 : 0)
-
/
*
* Mac eth header length
--
2.7.4
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[PATCH 0/3] staging: wilc1000: updated copyright header and TODO list
This patch series contains the remaining patches from [1]. Included the updated copyright information for all source and header file. Also included the patch to remove checkpatch error and updated the TODO item. After this patch only 3 checkpatch related warning are remaining(2 will be remove after moving binding reference to './Documentation/devicetree/bindings/' ./drivers/staging/wilc1000/wilc_sdio.c:211: WARNING: DT compatible string "microchip,wilc1000-sdio" appears un-documented ./drivers/staging/wilc1000/wilc_spi.c:142: WARNING: DT compatible string "microchip,wilc1000-spi" appears un-documented ./drivers/staging/wilc1000/wilc_wlan.c:438: CHECK: usleep_range is preferred over udelay; [1]. https://www.spinics.net/lists/linux-driver-devel/msg115571.html Ajay Singh (3): staging: wilc1000: added Microchip copyright notice header staging: wilc1000: replace ISWILC1000() macro with inline function staging: wilc1000: remove TODO item for comments and code style drivers/staging/wilc1000/TODO | 1 - drivers/staging/wilc1000/coreconfigurator.c | 5 + drivers/staging/wilc1000/coreconfigurator.h | 5 + drivers/staging/wilc1000/host_interface.c | 5 + drivers/staging/wilc1000/host_interface.h | 5 + drivers/staging/wilc1000/linux_mon.c | 5 + drivers/staging/wilc1000/linux_wlan.c | 5 + drivers/staging/wilc1000/wilc_debugfs.c | 10 ++ drivers/staging/wilc1000/wilc_sdio.c | 5 ++--- drivers/staging/wilc1000/wilc_spi.c | 5 ++--- drivers/staging/wilc1000/wilc_wfi_cfgoperations.c | 5 + drivers/staging/wilc1000/wilc_wfi_cfgoperations.h | 5 + drivers/staging/wilc1000/wilc_wfi_netdevice.h | 5 + drivers/staging/wilc1000/wilc_wlan.c | 14 -- drivers/staging/wilc1000/wilc_wlan.h | 7 +-- drivers/staging/wilc1000/wilc_wlan_cfg.c | 12 drivers/staging/wilc1000/wilc_wlan_cfg.h | 12 drivers/staging/wilc1000/wilc_wlan_if.h | 12 18 files changed, 80 insertions(+), 43 deletions(-) -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH 7/8] staging: wilc1000: replace udelay with usleep_range
Hi Greg,
On Thu, 2 Aug 2018 09:34:15 +0200
Greg KH wrote:
> On Sun, Jul 29, 2018 at 11:36:56AM +0530, Ajay Singh wrote:
> > Cleanup patch to avoid the below checkpatch reported issue.
> >
> > "usleep_range is preferred over udelay; see
> > Documentation/timers/timers-howto.txt".
> >
> > Signed-off-by: Ajay Singh
> > ---
> > drivers/staging/wilc1000/wilc_wlan.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/staging/wilc1000/wilc_wlan.c
> > b/drivers/staging/wilc1000/wilc_wlan.c index 6bac3f7..655952a 100644
> > --- a/drivers/staging/wilc1000/wilc_wlan.c
> > +++ b/drivers/staging/wilc1000/wilc_wlan.c
> > @@ -425,7 +425,7 @@ void chip_wakeup(struct wilc *wilc)
> > } while (wilc_get_chipid(wilc, true) == 0);
> > } else if ((wilc->io_type & 0x1) == HIF_SDIO) {
> > wilc->hif_func->hif_write_reg(wilc, 0xfa, 1);
> > - udelay(200);
> > + usleep_range(200, 201);
>
> Hah, that's funny.
>
> No, do it right, don't try to game checkpatch here.
The delay of 200us was added to have a short wait between HW register
write and read operation. The short delay of 200us was enough for this
but the duration range is not available. So to replace udelay() of
200us with usleep_range(), I have used used range from 200, 201.
How should we handle these type of scenarios and is there any suggested
way to specify these range.
Should we leave this code as it is and ignore this checkpatch warning.
Please provide your suggestion/input.
Thank you.
Regards,
Ajay
___
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http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v10 04/15] staging: mt7621-pci: use pcie_[read|write] in [write|read]_config
Instead of custom macros use pcie_read and pcie_write functions.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 67 -
1 file changed, 32 insertions(+), 35 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index fe9c68f..f1abf6c 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -240,41 +240,38 @@ struct pci_ops mt7621_pci_ops = {
};
static void
-read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned
long reg, unsigned long *val)
+read_config(struct mt7621_pcie *pcie,
+ unsigned long bus, unsigned long dev,
+ unsigned long func, unsigned long reg, unsigned long *val)
{
- u32 address_reg, data_reg, address;
-
- address_reg = RALINK_PCI_CONFIG_ADDR;
- data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
- address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
- MV_WRITE(address_reg, address);
- MV_READ(data_reg, val);
- return;
+ u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+
+ pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
+ *val = pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
}
static void
-write_config(unsigned long bus, unsigned long dev, unsigned long func,
unsigned long reg, unsigned long val)
+write_config(struct mt7621_pcie *pcie,
+unsigned long bus, unsigned long dev,
+unsigned long func, unsigned long reg, unsigned long val)
{
- u32 address_reg, data_reg, address;
-
- address_reg = RALINK_PCI_CONFIG_ADDR;
- data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
- address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
- MV_WRITE(address_reg, address);
- MV_WRITE(data_reg, val);
- return;
+ u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+
+ pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
+ pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
}
int
pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
+ struct mt7621_pcie *pcie = dev->bus->sysdata;
u16 cmd;
u32 val;
int irq;
if (dev->bus->number == 0) {
- write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
- read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long
*));
+ write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
+ read_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned
long *));
printk("BAR0 at slot %d = %x\n", slot, val);
}
@@ -572,13 +569,13 @@ static int mt7621_pci_probe(struct platform_device *pdev)
bypass_pipe_rst();
set_phy_for_ssc();
- read_config(0, 0, 0, 0x70c, );
+ read_config(pcie, 0, 0, 0, 0x70c, );
printk("Port 0 N_FTS = %x\n", (unsigned int)val);
- read_config(0, 1, 0, 0x70c, );
+ read_config(pcie, 0, 1, 0, 0x70c, );
printk("Port 1 N_FTS = %x\n", (unsigned int)val);
- read_config(0, 2, 0, 0x70c, );
+ read_config(pcie, 0, 2, 0, 0x70c, );
printk("Port 2 N_FTS = %x\n", (unsigned int)val);
rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
@@ -699,28 +696,28 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
switch (pcie_link_status) {
case 7:
- read_config(0, 2, 0, 0x4, );
- write_config(0, 2, 0, 0x4, val|0x4);
- read_config(0, 2, 0, 0x70c, );
+ read_config(pcie, 0, 2, 0, 0x4, );
+ write_config(pcie, 0, 2, 0, 0x4, val|0x4);
+ read_config(pcie, 0, 2, 0, 0x70c, );
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(0, 2, 0, 0x70c, val);
+ write_config(pcie, 0, 2, 0, 0x70c, val);
case 3:
case 5:
case 6:
- read_config(0, 1, 0, 0x4, );
- write_config(0, 1, 0, 0x4, val|0x4);
- read_config(0, 1, 0, 0x70c, );
+ read_config(pcie, 0, 1, 0, 0x4, );
+ write_config(pcie, 0, 1, 0, 0x4, val|0x4);
+ read_config(pcie, 0, 1, 0, 0x70c, );
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(0, 1, 0, 0x70c, val);
+ write_config(pcie, 0, 1, 0, 0x70c, val);
default:
- read_config(0, 0, 0, 0x4, );
- write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
- read_config(0, 0, 0, 0x70c, );
+ read_config(pcie, 0, 0, 0, 0x4, );
+ write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable
+ read_config(pcie, 0, 0, 0, 0x70c, );
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(0, 0, 0, 0x70c, val);
+
[PATCH v10 08/15] staging: mt7621-pci: avoid register duplication per controller using pcie_[read|write]
Use pcie_[read|write] fucntions to read and write controller registers.
Define those only by offset and pass controller offset + register offset
relative to base address to functions.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 70 -
1 file changed, 34 insertions(+), 36 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 4200c68..e1245a4 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -74,8 +74,8 @@
#define RALINK_PCI_CONFIG_ADDR 0x20
#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
-#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE +
0x0028)
-#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE +
0x002C)
+#define RALINK_PCI_MEMBASE 0x28
+#define RALINK_PCI_IOBASE 0x2C
#define RALINK_PCIE0_RST (1<<24)
#define RALINK_PCIE1_RST (1<<25)
#define RALINK_PCIE2_RST (1<<26)
@@ -88,26 +88,12 @@
#define RT6855_PCIE1_OFFSET0x3000
#define RT6855_PCIE2_OFFSET0x4000
-#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0010)
-#define RALINK_PCI0_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0018)
-#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0030)
-#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0034)
-#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0038)
-#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0050)
-
-#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0010)
-#define RALINK_PCI1_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0018)
-#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0030)
-#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0034)
-#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0038)
-#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0050)
-
-#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0010)
-#define RALINK_PCI2_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0018)
-#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0030)
-#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0034)
-#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0038)
-#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0050)
+#define RALINK_PCI_BAR0SETUP_ADDR 0x0010
+#define RALINK_PCI_IMBASEBAR0_ADDR 0x0018
+#define RALINK_PCI_ID 0x0030
+#define RALINK_PCI_CLASS 0x0034
+#define RALINK_PCI_SUBID 0x0038
+#define RALINK_PCI_STATUS 0x0050
#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
@@ -566,7 +552,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;
// set DATA
mdelay(1000);
- if ((RALINK_PCI0_STATUS & 0x1) == 0) {
+ if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
printk("PCIE0 no card, disable it(RST)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
@@ -576,7 +562,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
}
- if ((RALINK_PCI1_STATUS & 0x1) == 0) {
+ if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
printk("PCIE1 no card, disable it(RST)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
@@ -586,7 +572,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
}
- if ((RALINK_PCI2_STATUS & 0x1) == 0) {
+ if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
printk("PCIE2 no card, disable it(RST)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
[PATCH v10 11/15] staging: mt7621-pci: remove RALINK_PCI_BASE from remaining definitions
RALINK_PCI_BASE has no sense and this driver has base address readed
and mapped from device tree. Remove remaining uses of it and
change code to use pcie_read and pcie_write functions in places
where this was being used.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 131
1 file changed, 67 insertions(+), 64 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 1a301e8..972a802 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -76,7 +76,6 @@
#define RALINK_PCI_PCICFG_ADDR 0x
#define RALINK_PCI_PCIMSK_ADDR 0x000C
-#define RALINK_PCI_BASE0xBE14
#define RT6855_PCIE0_OFFSET0x2000
#define RT6855_PCIE1_OFFSET0x3000
@@ -89,8 +88,8 @@
#define RALINK_PCI_SUBID 0x0038
#define RALINK_PCI_STATUS 0x0050
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
-#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
+#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
+#define RALINK_PCIEPHY_P2_CTL_OFFSET 0xA000
#define RALINK_PCI_MM_MAP_BASE 0x6000
#define RALINK_PCI_IO_MAP_BASE 0x1e16
@@ -242,105 +241,109 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8
pin)
}
void
-set_pcie_phy(u32 *addr, int start_b, int bits, int val)
+set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
+int start_b, int bits, int val)
{
- *(unsigned int *)(addr) &= ~(((1<> 6) & 0x7;
/* Set PCIe Port0 & Port1 PHY to disable SSC */
/* Debug Xtal Type */
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1,
0x01); // rg_pe1_frc_h_xtal_type
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2,
0x00); // rg_pe1_h_xtal_type
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1,
0x01); // rg_pe1_frc_phy_en//Force Port 0 enable control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1,
0x01); // rg_pe1_frc_phy_en//Force Port 1 enable control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1,
0x00); // rg_pe1_phy_en//Port 0 disable
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1,
0x00); // rg_pe1_phy_en//Port 1 disable
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1,
0x01); // rg_pe1_frc_h_xtal_type
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2,
0x00); // rg_pe1_h_xtal_type
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1,
0x01); // rg_pe1_frc_phy_en//Force Port 0 enable control
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1,
0x01); // rg_pe1_frc_phy_en//Force Port 1 enable control
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1,
0x00); // rg_pe1_phy_en//Port 0 disable
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1,
0x00); // rg_pe1_phy_en//Port 1 disable
if (reg <= 5 && reg >= 3) { // 40MHz Xtal
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),
6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),
6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
printk("* Xtal 40MHz *\n");
} else {// 25MHz | 20MHz Xtal
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),
6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),
6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
if (reg >= 6) {
printk("* Xtal 25MHz *\n");
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x49c), 0, 31, 0x1800); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO
PCW (for host mode)
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither
period control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4a8), 0, 12, 0x4a);// RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither
amplitude control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4a8), 16, 12, 0x4a);// RG_PE1_H_LCDDS_SSC_DELTA1//DDS SSC dither
amplitude control for initial
+
[PATCH v10 01/15] staging: mt7621-pci: use generic kernel pci subsystem read and write
map_bus callback is called before every .read/.write operation.
Implement it and change custom read write operations for the
pci subsystem generics. Make the probe function to don't use
legacy stuff and request bus resources directly. Get pci register
base and ranges from device tree.
The driver is not using PCI_LEGACY code anymore and shall use the
PCI_DRIVERS_GENERIC option to correct compile it. Add also new
Kconfig file for this controller setting there its correct dependencies.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/Kconfig | 2 +
drivers/staging/mt7621-pci/Kconfig | 7 +
drivers/staging/mt7621-pci/pci-mt7621.c | 226 +---
3 files changed, 218 insertions(+), 17 deletions(-)
create mode 100644 drivers/staging/mt7621-pci/Kconfig
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 2bce647..732b631 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -110,6 +110,8 @@ source "drivers/staging/vboxvideo/Kconfig"
source "drivers/staging/pi433/Kconfig"
+source "drivers/staging/mt7621-pci/Kconfig"
+
source "drivers/staging/mt7621-pinctrl/Kconfig"
source "drivers/staging/mt7621-spi/Kconfig"
diff --git a/drivers/staging/mt7621-pci/Kconfig
b/drivers/staging/mt7621-pci/Kconfig
new file mode 100644
index 000..d335338
--- /dev/null
+++ b/drivers/staging/mt7621-pci/Kconfig
@@ -0,0 +1,7 @@
+config PCI_MT7621
+ tristate "MediaTek MT7621 PCI Controller"
+ depends on RALINK
+ select PCI_DRIVERS_GENERIC
+ help
+ This selects a driver for the MediaTek MT7621 PCI Controller.
+
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 650e49b..1270291 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -53,11 +53,16 @@
#include
#include
#include
+#include
+#include
+#include
#include
#include
#include
+#include "../../pci/pci.h"
+
/*
* These functions and structures provide the BIOS scan and mapping of the PCI
* devices.
@@ -178,6 +183,43 @@ static int pcie_link_status = 0;
#define PCI_ACCESS_WRITE_2 4
#define PCI_ACCESS_WRITE_4 5
+/**
+ * struct mt7621_pcie_port - PCIe port information
+ * @base: IO mapped register base
+ * @list: port list
+ * @pcie: pointer to PCIe host info
+ * @reset: pointer to port reset control
+ */
+struct mt7621_pcie_port {
+ void __iomem *base;
+ struct list_head list;
+ struct mt7621_pcie *pcie;
+ struct reset_control *reset;
+};
+
+/**
+ * struct mt7621_pcie - PCIe host information
+ * @base: IO Mapped Register Base
+ * @io: IO resource
+ * @mem: non-prefetchable memory resource
+ * @busn: bus range
+ * @offset: IO / Memory offset
+ * @dev: Pointer to PCIe device
+ * @ports: pointer to PCIe port information
+ */
+struct mt7621_pcie {
+ void __iomem *base;
+ struct device *dev;
+ struct resource io;
+ struct resource mem;
+ struct resource busn;
+ struct {
+ resource_size_t mem;
+ resource_size_t io;
+ } offset;
+ struct list_head ports;
+};
+
static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
unsigned int func, unsigned int where)
{
@@ -297,17 +339,22 @@ pci_config_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u
}
}
-struct pci_ops mt7621_pci_ops = {
- .read = pci_config_read,
- .write = pci_config_write,
-};
+static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
+unsigned int devfn, int where)
+{
+ struct mt7621_pcie *pcie = bus->sysdata;
+ u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+PCI_FUNC(devfn), where);
+
+ writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
+
+ return pcie->base + RALINK_PCI_CONFIG_DATA_VIRTUAL_REG + (where & 3);
+}
-static struct resource mt7621_res_pci_mem1;
-static struct resource mt7621_res_pci_io1;
-static struct pci_controller mt7621_controller = {
- .pci_ops= _pci_ops,
- .mem_resource = _res_pci_mem1,
- .io_resource= _res_pci_io1,
+struct pci_ops mt7621_pci_ops = {
+ .map_bus= mt7621_pcie_map_bus,
+ .read = pci_generic_config_read,
+ .write = pci_generic_config_write,
};
static void
@@ -463,9 +510,10 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1,
0x00); // rg_pe1_frc_phy_en//Force Port 0 disable control
}
-void setup_cm_memory_region(struct resource *mem_resource)
+static void setup_cm_memory_region(struct resource *mem_resource)
{
resource_size_t mask;
+
if (mips_cps_numiocu(0)) {
/* FIXME: hardware doesn't accept mask values with 1s after
[PATCH v10 02/15] staging: mt7621-pci: remove dead code derived to not use custom reads and writes
Driver is using now pci subsystem generics reads and writes and requesting
bus resources without using legacy code functions. Because of this there is
a lot of dead code that can be removed.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 128
1 file changed, 128 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 1270291..68f4714 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -123,15 +123,6 @@
*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
#define MV_READ(ofs, data) \
*(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-#define MV_WRITE_16(ofs, data) \
- *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
-#define MV_READ_16(ofs, data) \
- *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
-
-#define MV_WRITE_8(ofs, data) \
- *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
-#define MV_READ_8(ofs, data) \
- *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
#define RALINK_PCI_MM_MAP_BASE 0x6000
#define RALINK_PCI_IO_MAP_BASE 0x1e16
@@ -176,13 +167,6 @@
#define MEMORY_BASE 0x0
static int pcie_link_status = 0;
-#define PCI_ACCESS_READ_1 0
-#define PCI_ACCESS_READ_2 1
-#define PCI_ACCESS_READ_4 2
-#define PCI_ACCESS_WRITE_1 3
-#define PCI_ACCESS_WRITE_2 4
-#define PCI_ACCESS_WRITE_4 5
-
/**
* struct mt7621_pcie_port - PCIe port information
* @base: IO mapped register base
@@ -227,118 +211,6 @@ static inline u32 mt7621_pci_get_cfgaddr(unsigned int
bus, unsigned int slot,
(func << 8) | (where & 0xfc) | 0x8000;
}
-static int config_access(unsigned char access_type, struct pci_bus *bus,
- unsigned int devfn, unsigned int where, u32 *data)
-{
- unsigned int slot = PCI_SLOT(devfn);
- u8 func = PCI_FUNC(devfn);
- u32 address_reg, data_reg;
- unsigned int address;
-
- address_reg = RALINK_PCI_CONFIG_ADDR;
- data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-
- address = mt7621_pci_get_cfgaddr(bus->number, slot, func, where);
-
- MV_WRITE(address_reg, address);
-
- switch (access_type) {
- case PCI_ACCESS_WRITE_1:
- MV_WRITE_8(data_reg+(where&0x3), *data);
- break;
- case PCI_ACCESS_WRITE_2:
- MV_WRITE_16(data_reg+(where&0x3), *data);
- break;
- case PCI_ACCESS_WRITE_4:
- MV_WRITE(data_reg, *data);
- break;
- case PCI_ACCESS_READ_1:
- MV_READ_8(data_reg+(where&0x3), data);
- break;
- case PCI_ACCESS_READ_2:
- MV_READ_16(data_reg+(where&0x3), data);
- break;
- case PCI_ACCESS_READ_4:
- MV_READ(data_reg, data);
- break;
- default:
- printk("no specify access type\n");
- break;
- }
- return 0;
-}
-
-static int
-read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val)
-{
- return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned
int)where, (u32 *)val);
-}
-
-static int
-read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 *val)
-{
- return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned
int)where, (u32 *)val);
-}
-
-static int
-read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 *val)
-{
- return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned
int)where, (u32 *)val);
-}
-
-static int
-write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
-{
- if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where,
(u32 *)))
- return -1;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
-{
- if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)))
- return -1;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
-{
- if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, ))
- return -1;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size,
u32 *val)
-{
- switch (size) {
- case 1:
- return read_config_byte(bus, devfn, where, (u8 *) val);
- case 2:
- return read_config_word(bus, devfn, where, (u16 *) val);
- default:
- return read_config_dword(bus, devfn, where, val);
- }
-}
-
-static int
-pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size,
u32 val)
-{
- switch (size) {
- case 1:
- return
[PATCH v10 15/15] staging: mt7621-dts: add pcie controller port registers
The pcie node of the device tree only contains registers
for the host-bridge and pcie port 0. Add the pcie port 1
and pcie port 2 also.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-dts/mt7621.dtsi | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 4610403..2e837e6 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -394,8 +394,10 @@
pcie: pcie@1e14 {
compatible = "mediatek,mt7621-pci";
- reg = <0x1e14 0x100
- 0x1e142000 0x100>;
+ reg = <0x1e14 0x100 /* host-pci bridge registers */
+ 0x1e142000 0x100/* pcie port 0 RC control registers
*/
+ 0x1e143000 0x100/* pcie port 1 RC control registers
*/
+ 0x1e144000 0x100>; /* pcie port 2 RC control registers
*/
#address-cells = <3>;
#size-cells = <2>;
--
2.7.4
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[PATCH v10 10/15] staging: mt7621-pci: use pcie_[read|write] in RALINK_PCI_PCICFG_ADDR and RALINK_PCI_PCIMSK_ADDR
RALINK_PCI_PCICFG_ADDR and RALINK_PCI_PCIMSK_ADDR are defined to be directly
referenced for read and write. Use pcie_read and pcie_write instead changing
its definition to a simple relative offset to pcie base address.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 54 +
1 file changed, 34 insertions(+), 20 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 4a20138..1a301e8 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -74,8 +74,8 @@
#define RALINK_PCIE1_RST (1<<25)
#define RALINK_PCIE2_RST (1<<26)
-#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE +
0x)
-#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE +
0x000C)
+#define RALINK_PCI_PCICFG_ADDR 0x
+#define RALINK_PCI_PCIMSK_ADDR 0x000C
#define RALINK_PCI_BASE0xBE14
#define RT6855_PCIE0_OFFSET0x2000
@@ -553,7 +553,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status &= ~(1<<0);
} else {
pcie_link_status |= 1<<0;
- RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
+ val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+ val |= (1<<20); // enable pcie1 interrupt
+ pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
}
if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
@@ -563,7 +565,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status &= ~(1<<1);
} else {
pcie_link_status |= 1<<1;
- RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
+ val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+ val |= (1<<21); // enable pcie1 interrupt
+ pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
}
if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
@@ -573,7 +577,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status &= ~(1<<2);
} else {
pcie_link_status |= 1<<2;
- RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
+ val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+ val |= (1<<22); // enable pcie2 interrupt
+ pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
}
if (pcie_link_status == 0)
@@ -592,27 +598,35 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
*/
switch (pcie_link_status) {
case 2:
- RALINK_PCI_PCICFG_ADDR &= ~0x00ff;
- RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;//port0
- RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;//port1
+ val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+ val &= ~0x00ff;
+ val |= 0x1 << 16; // port 0
+ val |= 0x0 << 20; // port 1
+ pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
break;
case 4:
- RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
- RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;//port0
- RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;//port1
- RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;//port2
+ val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+ val &= ~0x0fff;
+ val |= 0x1 << 16; //port0
+ val |= 0x2 << 20; //port1
+ val |= 0x0 << 24; //port2
+ pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
break;
case 5:
- RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
- RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;//port0
- RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;//port1
- RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;//port2
+ val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+ val &= ~0x0fff;
+ val |= 0x0 << 16; //port0
+ val |= 0x2 << 20; //port1
+ val |= 0x1 << 24; //port2
+ pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
break;
case 6:
- RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
- RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;//port0
- RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;//port1
- RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;//port2
+ val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+ val &= ~0x0fff;
+ val |= 0x2 << 16; //port0
+ val |= 0x0 << 20; //port1
+ val |= 0x1 << 24; //port2
+ pcie_write(pcie, val,
[PATCH v10 13/15] staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG definition
RALINK_PCI_CONFIG_DATA_VIRTUAL_REG is a very long name. Make it a bit
shorter renaming it to RALINK_PCI_CONFIG_DATA.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index c288b26..dd1a728 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -67,7 +67,7 @@
#define RALINK_PCIE2_CLK_ENBIT(26)
#define RALINK_PCI_CONFIG_ADDR 0x20
-#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
+#define RALINK_PCI_CONFIG_DATA 0x24
#define RALINK_PCI_MEMBASE 0x28
#define RALINK_PCI_IOBASE 0x2C
#define RALINK_PCIE0_RST BIT(24)
@@ -187,7 +187,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus
*bus,
writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
- return pcie->base + RALINK_PCI_CONFIG_DATA_VIRTUAL_REG + (where & 3);
+ return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
}
struct pci_ops mt7621_pci_ops = {
@@ -202,7 +202,7 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev, u32
reg)
u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
- return pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
+ return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
}
static void
@@ -211,7 +211,7 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev,
u32 reg, u32 val)
u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
- pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
+ pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
}
int
--
2.7.4
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[PATCH v10 14/15] staging: mt7621-pci: remove remaining pci_legacy dependant code
pcibios_* remaining code is not neccessary at all. We can use
map_irq set to of_irq_parse_and_map_pci driver 'probe' function.
Remove this code.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 33 +
1 file changed, 1 insertion(+), 32 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index dd1a728..a49e279 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -214,32 +214,6 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev,
u32 reg, u32 val)
pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
}
-int
-pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- struct mt7621_pcie *pcie = dev->bus->sysdata;
- u16 cmd;
- u32 val;
- int irq;
-
- if (dev->bus->number == 0) {
- write_config(pcie, slot, PCI_BASE_ADDRESS_0, MEMORY_BASE);
- val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
- printk("BAR0 at slot %d = %x\n", slot, val);
- }
-
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure
cache line size 0x14
- pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure
latency timer 0x10
- pci_read_config_word(dev, PCI_COMMAND, );
- cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
- pci_write_config_word(dev, PCI_COMMAND, cmd);
-
- irq = of_irq_parse_and_map_pci(dev, slot, pin);
-
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
- return irq;
-}
-
void
set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
int start_b, int bits, int val)
@@ -461,7 +435,7 @@ static int mt7621_pcie_register_host(struct pci_host_bridge
*host,
host->busnr = pcie->busn.start;
host->dev.parent = pcie->dev;
host->ops = _pci_ops;
- host->map_irq = pcibios_map_irq;
+ host->map_irq = of_irq_parse_and_map_pci;
host->swizzle_irq = pci_common_swizzle;
host->sysdata = pcie;
@@ -726,11 +700,6 @@ pcie(2/1/0) link statuspcie2_num pcie1_num
pcie0_num
return 0;
}
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
-
static const struct of_device_id mt7621_pci_ids[] = {
{ .compatible = "mediatek,mt7621-pci" },
{},
--
2.7.4
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[PATCH v10 07/15] staging: mt7621-pci: remove unused macros
There some macros that are not being used. Remove them. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 24 +--- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 3b45c59..4200c68 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -84,7 +84,6 @@ #define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C) #define RALINK_PCI_BASE0xBE14 -#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000) #define RT6855_PCIE0_OFFSET0x2000 #define RT6855_PCIE1_OFFSET0x3000 #define RT6855_PCIE2_OFFSET0x4000 @@ -95,8 +94,6 @@ #define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034) #define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038) #define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050) -#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060) -#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064) #define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010) #define RALINK_PCI1_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018) @@ -104,8 +101,6 @@ #define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034) #define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038) #define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050) -#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060) -#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064) #define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010) #define RALINK_PCI2_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018) @@ -113,17 +108,10 @@ #define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034) #define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038) #define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050) -#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060) -#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064) #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000) #define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000) -#define MV_WRITE(ofs, data)\ - *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data) -#define MV_READ(ofs, data) \ - *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs))) - #define RALINK_PCI_MM_MAP_BASE 0x6000 #define RALINK_PCI_IO_MAP_BASE 0x1e16 @@ -141,28 +129,18 @@ else\ rt_sysc_m32(0, val, RALINK_RSTCTRL);\ } while (0) + #define RALINK_CLKCFG1 0x30 #define RALINK_RSTCTRL 0x34 #define RALINK_GPIOMODE0x60 #define RALINK_PCIE_CLK_GEN0x7c #define RALINK_PCIE_CLK_GEN1 0x80 -#define PPLL_CFG1 0x9c -#define PPLL_DRV 0xa0 -/* SYSC_REG_SYSTEM_CONFIG1 bits */ -#define RALINK_PCI_HOST_MODE_EN(1<<7) -#define RALINK_PCIE_RC_MODE_EN (1<<8) //RALINK_RSTCTRL bit #define RALINK_PCIE_RST(1<<23) #define RALINK_PCI_RST (1<<24) //RALINK_CLKCFG1 bit #define RALINK_PCI_CLK_EN (1<<19) #define RALINK_PCIE_CLK_EN (1<<21) -//RALINK_GPIOMODE bit -#define PCI_SLOTx2 (1<<11) -#define PCI_SLOTx1 (2<<11) -//MTK PCIE PLL bit -#define PDRV_SW_SET(1<<31) -#define LC_CKDRVPD_(1<<19) #define MEMORY_BASE 0x0 static int pcie_link_status = 0; -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v10 09/15] staging: mt7621-pci: review includes putting them in alphabethic order
There are some includes that are being used that are not really needed to correct driver compilation. Remove them and reorder the rest alphabetically. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 22 -- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index e1245a4..4a20138 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -40,26 +40,20 @@ ** */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include +#include #include +#include #include -#include -#include #include #include +#include +#include +#include #include - -#include +#include #include +#include #include "../../pci/pci.h" -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v10 06/15] staging: mt7621-pci: simplify write_config function
write_config function is always called with bus and func
being 0. Avoid those params and just use 0 inside the
function. Review parameter types changing for more proper
ones.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index ad480f2..3b45c59 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -249,11 +249,9 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev,
u32 reg)
}
static void
-write_config(struct mt7621_pcie *pcie,
-unsigned long bus, unsigned long dev,
-unsigned long func, unsigned long reg, unsigned long val)
+write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
{
- u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+ u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
@@ -268,7 +266,7 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
int irq;
if (dev->bus->number == 0) {
- write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
+ write_config(pcie, slot, PCI_BASE_ADDRESS_0, MEMORY_BASE);
val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
printk("BAR0 at slot %d = %x\n", slot, val);
}
@@ -695,27 +693,27 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
switch (pcie_link_status) {
case 7:
val = read_config(pcie, 2, 0x4);
- write_config(pcie, 0, 2, 0, 0x4, val|0x4);
+ write_config(pcie, 2, 0x4, val|0x4);
val = read_config(pcie, 2, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(pcie, 0, 2, 0, 0x70c, val);
+ write_config(pcie, 2, 0x70c, val);
case 3:
case 5:
case 6:
val = read_config(pcie, 1, 0x4);
- write_config(pcie, 0, 1, 0, 0x4, val|0x4);
+ write_config(pcie, 1, 0x4, val|0x4);
val = read_config(pcie, 1, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(pcie, 0, 1, 0, 0x70c, val);
+ write_config(pcie, 1, 0x70c, val);
default:
val = read_config(pcie, 0, 0x4);
- write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable
+ write_config(pcie, 0, 0x4, val|0x4); //bus master enable
val = read_config(pcie, 0, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(pcie, 0, 0, 0, 0x70c, val);
+ write_config(pcie, 0, 0x70c, val);
}
err = mt7621_pci_parse_request_of_pci_ranges(pcie);
--
2.7.4
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[PATCH v10 12/15] staging: mt7621-pci: use BIT macro in preprocessor definitions
Some preprocessor definitions are using a custom implementation of BIT macro. Just use linux kernel BIT macro instead. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 972a802..c288b26 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -62,17 +62,17 @@ * devices. */ -#define RALINK_PCIE0_CLK_EN(1<<24) -#define RALINK_PCIE1_CLK_EN(1<<25) -#define RALINK_PCIE2_CLK_EN(1<<26) +#define RALINK_PCIE0_CLK_ENBIT(24) +#define RALINK_PCIE1_CLK_ENBIT(25) +#define RALINK_PCIE2_CLK_ENBIT(26) #define RALINK_PCI_CONFIG_ADDR 0x20 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24 #define RALINK_PCI_MEMBASE 0x28 #define RALINK_PCI_IOBASE 0x2C -#define RALINK_PCIE0_RST (1<<24) -#define RALINK_PCIE1_RST (1<<25) -#define RALINK_PCIE2_RST (1<<26) +#define RALINK_PCIE0_RST BIT(24) +#define RALINK_PCIE1_RST BIT(25) +#define RALINK_PCIE2_RST BIT(26) #define RALINK_PCI_PCICFG_ADDR 0x #define RALINK_PCI_PCIMSK_ADDR 0x000C @@ -115,11 +115,11 @@ #define RALINK_PCIE_CLK_GEN0x7c #define RALINK_PCIE_CLK_GEN1 0x80 //RALINK_RSTCTRL bit -#define RALINK_PCIE_RST(1<<23) -#define RALINK_PCI_RST (1<<24) +#define RALINK_PCIE_RSTBIT(23) +#define RALINK_PCI_RST BIT(24) //RALINK_CLKCFG1 bit -#define RALINK_PCI_CLK_EN (1<<19) -#define RALINK_PCIE_CLK_EN (1<<21) +#define RALINK_PCI_CLK_EN BIT(19) +#define RALINK_PCIE_CLK_EN BIT(21) #define MEMORY_BASE 0x0 static int pcie_link_status = 0; -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v10 05/15] staging: mt7621-pci: simplify read_config function
read_config function is always called with bus and func
being 0. Avoid those params and just use 0 inside the
function. Return readed value instead pass a reference
parameter.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 32 +++-
1 file changed, 15 insertions(+), 17 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index f1abf6c..ad480f2 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -239,15 +239,13 @@ struct pci_ops mt7621_pci_ops = {
.write = pci_generic_config_write,
};
-static void
-read_config(struct mt7621_pcie *pcie,
- unsigned long bus, unsigned long dev,
- unsigned long func, unsigned long reg, unsigned long *val)
+static u32
+read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
{
- u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+ u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
- *val = pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
+ return pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
}
static void
@@ -271,7 +269,7 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
if (dev->bus->number == 0) {
write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
- read_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned
long *));
+ val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
printk("BAR0 at slot %d = %x\n", slot, val);
}
@@ -517,7 +515,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
struct mt7621_pcie *pcie;
struct pci_host_bridge *bridge;
int err;
- unsigned long val = 0;
+ u32 val = 0;
LIST_HEAD(res);
if (!dev->of_node)
@@ -569,13 +567,13 @@ static int mt7621_pci_probe(struct platform_device *pdev)
bypass_pipe_rst();
set_phy_for_ssc();
- read_config(pcie, 0, 0, 0, 0x70c, );
+ val = read_config(pcie, 0, 0x70c);
printk("Port 0 N_FTS = %x\n", (unsigned int)val);
- read_config(pcie, 0, 1, 0, 0x70c, );
+ val = read_config(pcie, 1, 0x70c);
printk("Port 1 N_FTS = %x\n", (unsigned int)val);
- read_config(pcie, 0, 2, 0, 0x70c, );
+ val = read_config(pcie, 2, 0x70c);
printk("Port 2 N_FTS = %x\n", (unsigned int)val);
rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
@@ -696,25 +694,25 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
switch (pcie_link_status) {
case 7:
- read_config(pcie, 0, 2, 0, 0x4, );
+ val = read_config(pcie, 2, 0x4);
write_config(pcie, 0, 2, 0, 0x4, val|0x4);
- read_config(pcie, 0, 2, 0, 0x70c, );
+ val = read_config(pcie, 2, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
write_config(pcie, 0, 2, 0, 0x70c, val);
case 3:
case 5:
case 6:
- read_config(pcie, 0, 1, 0, 0x4, );
+ val = read_config(pcie, 1, 0x4);
write_config(pcie, 0, 1, 0, 0x4, val|0x4);
- read_config(pcie, 0, 1, 0, 0x70c, );
+ val = read_config(pcie, 1, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
write_config(pcie, 0, 1, 0, 0x70c, val);
default:
- read_config(pcie, 0, 0, 0, 0x4, );
+ val = read_config(pcie, 0, 0x4);
write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable
- read_config(pcie, 0, 0, 0, 0x70c, );
+ val = read_config(pcie, 0, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
write_config(pcie, 0, 0, 0, 0x70c, val);
--
2.7.4
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[PATCH v10 00/15] staging: mt7621-pci: avoid custom pci config read and writes
This patch series include an attempt to avoid the use of custom read and writes in driver code and use PCI subsystem common ones. In order to do this 'map_bus' callback is implemented and also data structures for driver are included. The regs base address ranges and data is being readed from device tree and the driver gets clean a lot of code. This patchet also removes all legacy PCI code using now PCI_DRIVERS_GENERIC kernel api. Changes in v10: - PATCH 1: Do 'ioremap' directly using 'ranges.cpu_addr' from the io resource and add it directly as a resource to the resources list like mips pci-legacy code do for this. We cannot do anything else since using new kernel pci generic apis (call to 'devm_of_pci_get_host_bridge_resources') we get bad io resource getting 'OF_BAD_ADDR' because of the fact that the io resource for this platform starts in 0x1e16 which is higher than IO_SPACE_LIMIT (0x). Because of this io resource is not added to the resources list and system gets into a not working state. - Other patches rebased and adapted to this changes. Changes in v9: - PATCH 1: Use 'res' as resources list and void store resources in the pcie data struct. - PATCH 1: Rewrite 'mt7621_pci_parse_request_of_pci_ranges' to use 'devm_of_pci_get_host_bridge_resources' and use 'remap' directly with the returned 'iobase' address instead of 'devm_pci_remap_iospace' which get into a WARN_ONCE statement because 'PCI_IOBASE' is not defined for mips. - Other patches rebased and adapted to this changes. Changes in v8: - PATCH 1: don't check 'of_pci_range_to_resource' return value which is not being checked for the legacy code. - PATCH 1: call 'mt7621_pci_parse_request_of_pci_ranges' 'and setup_cm_memory_region' after the port initialization code. - PATCH 1: make use of 'pci_host_probe' to avoid code duplication in function 'mt7621_pcie_register_host'. - PATCH 1: set resource limits with no limit for the end in 'ioport_resource' and 'iomem_resource'. It seems mips needs this to work properly. - Other patches rebased and adapted to this changes. Changes in v7: - PATCH 1: Store resources in mt7621_pci data structure. - PATCH 1: Change completely function mt7621_pci_parse_request_of_pci_ranges to parse resources from ranges manually instead of use the function devm_of_pci_get_host_bridge_resources. This is closer to the mips pci legacy code. - PATCH 1: Create 'mt7621_pcie_request_resources' function to request resources parsed from ranges property in the DT. Use pci_add_resource_offset and set them manually like the mips pci-legacy code do. - PATCH 1: don't delete function setup_cm_memory_region and call it with memory resource. - Other patches rebased and adapted to this changes. Changes in v6: - Reorder patches to be each patch correct in itself. - PATCH 1 adds also Kconfig to do the step from legacy to generic code - PATCH 1 remaps io space using devm_pci_remap_iospace for io resource in a new function called 'mt7621_pci_parse_request_of_pci_ranges'. - Other patches rebased and adapted with this changes. Changes in v5: - Include driver Kconfig file to add compilation depends of PCI_DRIVERS_GENERIC. The new added configuration option is CONFIG_PCI_MT7621. - Add list_splice_init(, >windows); in PATCH 1 to set windows from resources obtanined from devm_request_pci_bus_resources. - Move devm_of_pci_get_host_bridge_resources and devm_request_pci_bus_resources after the ports initialization legacy code. - Add pcie ports 1 and 2 RC registers to device tree. There was only being included port RC register for port 0. - Review includes and order them alphabetically. Changes in v4: - Rebased onto staging-next. Changes in v3: - Include new patches to delete all RALINK_BASE definition dependant code and be able to avoid use of pci_legacy code. - use devm_of_pci_get_host_bridge_resources, devm_request_pci_bus_resources and pci_scan_root_bus_bridge and pci_bus_add_devices Changes in v2: - squash PATCH 1 and PATCH 2 of previous series in only PATCH 1 - Change name for host structure. - Create a new port structure (platform has 3 pcie controllers) - Replace the use of pci_generic_config_[read|write]32 in favour of pci_generic_config_[read|write] and change map_bus implemen- tation for hopefully the right one. Best regards, Sergio Paracuellos Sergio Paracuellos (15): staging: mt7621-pci: use generic kernel pci subsystem read and write staging: mt7621-pci: remove dead code derived to not use custom reads and writes staging: mt7621-pci: add pcie_write and pcie_read helpers staging: mt7621-pci: use pcie_[read|write] in [write|read]_config staging: mt7621-pci: simplify read_config function
[PATCH v10 03/15] staging: mt7621-pci: add pcie_write and pcie_read helpers
Introdice this functions to make easier to write/read to/from
an offset relative to base address
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 68f4714..fe9c68f 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -204,6 +204,16 @@ struct mt7621_pcie {
struct list_head ports;
};
+static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
+{
+ return readl(pcie->base + reg);
+}
+
+static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
+{
+ writel(val, pcie->base + reg);
+}
+
static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
unsigned int func, unsigned int where)
{
--
2.7.4
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[PATCH] staging: wlan-ng: remove unused definitions from p80211types.h
Remove the following unused definitions from p80211types.h:
* struct p80211enum
* struct p80211enumpair
* struct catlistitem declaration and associated function pointer
typedefs (along with preceding block comment)
Signed-off-by: Tim Collier
---
drivers/staging/wlan-ng/p80211types.h | 27 ---
1 file changed, 27 deletions(-)
diff --git a/drivers/staging/wlan-ng/p80211types.h
b/drivers/staging/wlan-ng/p80211types.h
index 7c37d56dd9b7..ac254542fde6 100644
--- a/drivers/staging/wlan-ng/p80211types.h
+++ b/drivers/staging/wlan-ng/p80211types.h
@@ -194,20 +194,6 @@
P80211DID_LSB_ACCESS)
/**/
-/* The following structure types are used for the representation */
-/* of ENUMint type metadata. */
-
-struct p80211enumpair {
- u32 val;
- char *name;
-};
-
-struct p80211enum {
- int nitems;
- struct p80211enumpair *list;
-};
-
-/**/
/* The following structure types are used to store data items in */
/* messages. */
@@ -330,17 +316,4 @@ struct p80211item_unk4096 {
u8 data[4096];
} __packed;
-struct catlistitem;
-
-/**/
-/* The following structure type is used to represent all of the */
-/* metadata items. Some components may choose to use more, */
-/* less or different metadata items. */
-
-typedef void (*p80211_totext_t) (struct catlistitem *, u32 did, u8 *itembuf,
-char *textbuf);
-typedef void (*p80211_fromtext_t) (struct catlistitem *, u32 did, u8 *itembuf,
- char *textbuf);
-typedef u32(*p80211_valid_t) (struct catlistitem *, u32 did, u8 *itembuf);
-
#endif /* _P80211TYPES_H */
--
2.11.0
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Re: [PATCH v9 00/15] staging: mt7621-pci: avoid custom pci config read and writes
On Fri, Aug 03, 2018 at 02:33:22PM +1000, NeilBrown wrote:
> On Thu, Aug 02 2018, Sergio Paracuellos wrote:
>
> > This patch series include an attempt to avoid the use of custom
> > read and writes in driver code and use PCI subsystem common ones.
> >
> > In order to do this 'map_bus' callback is implemented and also
> > data structures for driver are included. The regs base address
> > ranges and data is being readed from device tree and the driver
> > gets clean a lot of code.
> >
> > This patchet also removes all legacy PCI code using now PCI_DRIVERS_GENERIC
> > kernel api.
> >
> > Changes in v9:
> > - PATCH 1: Use 'res' as resources list and void store resources in
> > the pcie data struct.
> > - PATCH 1: Rewrite 'mt7621_pci_parse_request_of_pci_ranges' to use
> > 'devm_of_pci_get_host_bridge_resources' and use 'remap' directly
> > with the returned 'iobase' address instead of
> > 'devm_pci_remap_iospace'
> > which get into a WARN_ONCE statement because 'PCI_IOBASE' is not
> > defined for mips.
> > - Other patches rebased and adapted to this changes.
>
> You probably expected this, but still no change.
As always thanks for your time, Neil.
Not really I was expecting still not working (I am loosing my faith :-)) but
avoid the first WARN_ON and see if root resources were properly listed using
the v8 code which I think is better. Anyway, the problem is with the io
resource.
When we call the function to get the resources
'devm_of_pci_get_host_bridge_resources'
this ends up in a 'for_each_of_pci_range' parsing every range in the device
tree
and trying to get a resource from it calling to 'of_pci_range_to_resource'
function.
This function fails for the IO resource because of the call to
'pci_address_to_pio(range->cpu_addr);'
with an address (0x1e16) which is greater than IO_SPACE_LIMIT (0x)
setting a 'OF_BAD_ADDR' for 'start' and 'end' in the resource and
returns EINVAL which is get by 'devm_of_pci_get_host_bridge_resources' to just
don't add the resource to the list and 'continue' with the next range (without
failing).
So the difference with previous v7 and lower PATCHes version is that the system
does not hang because
probably the increase of the ioport_resource (parent) memory range end limit to
0x. Why the legacy code works? Just because it just adds the range as a
valid
resource and directly remaps to kernel virtual space the 'range.cpu_addr' to
avoid the problem
when accesing from the ahci driver. That simple. So it seems that in this case
with an
io address upper of IO_SPACE_LIMIT we cannot do nothing but little 'hack' the
code to
get the 'map_bus' callback etc from generic pci api properly working (which
cleans the code a lot),
but we cannot use some of other useful and cleaner functions. I am going to
send hopefully last v10
which I really expect to work applying the things I am explaining here but we
should think if
this is the only way to get this properly clean and working.
> Just for completeness boot log is below.
>
> Thanks,
> NeilBrown
>
> Starting kernel ...
>
> [0.00] Linux version 4.18.0-rc7+ (neilb@noble) (gcc version 7.2.0
> (GCC)) #277 SMP Fri Aug 3 14:30:02 AEST 2018
> [0.00] SoC Type: MediaTek MT7621 ver:1 eco:3
> [0.00] bootconsole [early0] enabled
> [0.00] CPU0 revision is: 0001992f (MIPS 1004Kc)
> [0.00] MIPS: machine is GB-PC1
> [0.00] Determined physical RAM map:
> [0.00] memory: 1c00 @ (usable)
> [0.00] memory: 0400 @ 2000 (usable)
> [0.00] Initrd not found or empty - disabling initrd
> [0.00] VPE topology {2,2} total 4
> [0.00] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [0.00] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32
> bytes
> [0.00] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [0.00] Zone ranges:
> [0.00] Normal [mem 0x-0x1fff]
> [0.00] HighMem [mem 0x2000-0x23ff]
> [0.00] Movable zone start for each node
> [0.00] Early memory node ranges
> [0.00] node 0: [mem 0x-0x1bff]
> [0.00] node 0: [mem 0x2000-0x23ff]
> [0.00] Initmem setup node 0 [mem
> 0x-0x23ff]
> [0.00] random: get_random_bytes called from start_kernel+0xb4/0x4ec
> with crng_init=0
> [0.00] percpu: Embedded 15 pages/cpu @(ptrval) s30480 r8192 d22768
> u61440
> [0.00] Built 1 zonelists, mobility grouping on. Total pages: 130048
> [0.00] Kernel command line: console=ttyS0,57600
> [0.00] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
> [0.00] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
> [0.00] Writing ErrCtl register=000108a2
> [0.00]
