On 05-11-20, 17:18, Dmitry Osipenko wrote:
> 05.11.2020 12:58, Viresh Kumar пишет:
> >> +static void sdhci_tegra_deinit_opp_table(void *data)
> >> +{
> >> + struct device *dev = data;
> >> + struct opp_table *opp_table;
> >> +
> >> + opp_table = dev_pm_opp_get_opp_table(dev);
> >
05.11.2020 19:07, Alan Stern пишет:
>> +err = devm_tegra_ehci_init_opp_table(>dev);
>> +if (err)
>> +return dev_err_probe(>dev, err,
>> + "Failed to initialize OPP\n");
> Why log a second error message? Just return err.
Indeed, thanks.
05.11.2020 19:07, Alan Stern пишет:
> Do you really want to use the same error unwinding for opp_table values
> obtained from dev_pm_opp_set_regulators() as from
> dev_pm_opp_get_opp_table()?
They both are pointing at the same opp_table, which is refcounted.
The dev_pm_opp_set_regulators() is
On Thu, Nov 05, 2020 at 02:44:18AM +0300, Dmitry Osipenko wrote:
> Add initial OPP and SoC core voltage scaling support to the Tegra EHCI
> driver. This is required for enabling system-wide DVFS on older Tegra
> SoCs.
>
> Tested-by: Peter Geis
> Tested-by: Nicolas Chauvet
> Signed-off-by:
05.11.2020 12:45, Ulf Hansson пишет:
...
> I need some more time to review this, but just a quick check found a
> few potential issues...
Thank you for starting the review! I'm pretty sure it will take a couple
revisions until all the questions will be resolved :)
> The "core-supply", that you
Hi,
On Wed 04 Nov 20, 13:36, Helen Koike wrote:
> Hi Paul,
>
> On 11/4/20 8:11 AM, Paul Kocialkowski wrote:
> > Hi Helen,
> >
> > On Fri 30 Oct 20, 19:44, Helen Koike wrote:
> >> Hi Paul,
> >>
> >> I have some comments through the series, I hope this helps.
> >
> > Thanks for your comments :)
Hi Sakari and thanks for the review!
On Thu 05 Nov 20, 10:45, Sakari Ailus wrote:
> On Fri, Oct 23, 2020 at 07:45:40PM +0200, Paul Kocialkowski wrote:
> > The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 controller
> > found on Allwinner SoCs such as the A31 and V3/V3s.
> >
> > It is a
Hi,
On Wed 04 Nov 20, 19:56, Maxime Ripard wrote:
> On Wed, Nov 04, 2020 at 12:34:58PM +0100, Paul Kocialkowski wrote:
> > > > + regmap_write(regmap, SUN6I_MIPI_CSI2_CFG_REG,
> > > > +SUN6I_MIPI_CSI2_CFG_CHANNEL_MODE(1) |
> > > > +
05.11.2020 12:58, Viresh Kumar пишет:
>> +static void sdhci_tegra_deinit_opp_table(void *data)
>> +{
>> + struct device *dev = data;
>> + struct opp_table *opp_table;
>> +
>> + opp_table = dev_pm_opp_get_opp_table(dev);
> So you need to get an OPP table to put one :)
> You need
On 11/4/20 3:45 PM, Maxime Ripard wrote:
> On Wed, Nov 04, 2020 at 01:38:08PM -0300, Helen Koike wrote:
>>
>>
>> On 11/4/20 8:17 AM, Paul Kocialkowski wrote:
>>> Hi,
>>>
>>> On Mon 02 Nov 20, 10:21, Maxime Ripard wrote:
On Fri, Oct 30, 2020 at 07:45:18PM -0300, Helen Koike wrote:
> On
05.11.2020 04:45, Michał Mirosław пишет:
> On Thu, Nov 05, 2020 at 02:43:57AM +0300, Dmitry Osipenko wrote:
>> Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs, which reduces
>> power consumption and heating of the Tegra chips. Tegra SoC has multiple
>> hardware units which belong to a
Hi Martin,
On 12/09/2020 16:30, Martin Cerveny wrote:
> First patch extends cedrus capability to all decoders
> because V3s missing MPEG2 decoder.
>
> Next two patches add system control node (SRAM C1) and
> next three patches add support for Cedrus VPU.
>
> Tested on "Lichee Zero" V3s
On Thu, 5 Nov 2020 at 12:13, Viresh Kumar wrote:
>
> On 05-11-20, 11:56, Ulf Hansson wrote:
> > On Thu, 5 Nov 2020 at 11:40, Viresh Kumar wrote:
> > > Btw, how do we identify if it is a power domain or a regulator ?
>
> To be honest, I was a bit afraid and embarrassed to ask this question,
> and
On 05-11-20, 11:56, Ulf Hansson wrote:
> On Thu, 5 Nov 2020 at 11:40, Viresh Kumar wrote:
> > Btw, how do we identify if it is a power domain or a regulator ?
To be honest, I was a bit afraid and embarrassed to ask this question,
and was hoping people to make fun of me in return :)
> Good
On Thu, 5 Nov 2020 at 11:40, Viresh Kumar wrote:
>
> On 05-11-20, 11:34, Ulf Hansson wrote:
> > I am not objecting about scaling the voltage through a regulator,
> > that's fine to me. However, encoding a power domain as a regulator
> > (even if it may seem like a regulator) isn't. Well, unless
On Thu, 5 Nov 2020 at 11:06, Viresh Kumar wrote:
>
> On 05-11-20, 10:45, Ulf Hansson wrote:
> > + Viresh
>
> Thanks Ulf. I found a bug in OPP core because you cc'd me here :)
Happy to help. :-)
>
> > On Thu, 5 Nov 2020 at 00:44, Dmitry Osipenko wrote:
> > I need some more time to review this,
On Wed, Nov 04, 2020 at 12:39:11PM +0100, Hans Verkuil wrote:
> On 02/11/2020 15:18, Maxime Ripard wrote:
> > On Mon, Nov 02, 2020 at 10:26:22PM +0800, Zhang Qilong wrote:
> >> pm_runtime_get_sync will increment pm usage counter even it
> >> failed. Forgetting to pm_runtime_put_noidle will result
On 05-11-20, 11:34, Ulf Hansson wrote:
> I am not objecting about scaling the voltage through a regulator,
> that's fine to me. However, encoding a power domain as a regulator
> (even if it may seem like a regulator) isn't. Well, unless Mark Brown
> has changed his mind about this.
>
> In this
On 05-11-20, 10:45, Ulf Hansson wrote:
> + Viresh
Thanks Ulf. I found a bug in OPP core because you cc'd me here :)
> On Thu, 5 Nov 2020 at 00:44, Dmitry Osipenko wrote:
> I need some more time to review this, but just a quick check found a
> few potential issues...
>
> The "core-supply", that
On Thu, Nov 5, 2020 at 5:15 AM Dmitry Osipenko wrote:
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> +static void sdhci_tegra_deinit_opp_table(void *data)
> +{
> + struct device *dev = data;
> + struct opp_table *opp_table;
> +
> + opp_table =
+ Viresh
On Thu, 5 Nov 2020 at 00:44, Dmitry Osipenko wrote:
>
> Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs, which reduces
> power consumption and heating of the Tegra chips. Tegra SoC has multiple
> hardware units which belong to a core power domain of the SoC and share
> the
On Thu, Nov 5, 2020 at 10:28 AM Nicolas Saenz Julienne
wrote:
>
> Hi Bartosz, thanks for the review.
>
> On Thu, 2020-11-05 at 10:13 +0100, Bartosz Golaszewski wrote:
> > > +/**
> > > + * devm_rpi_firmware_get - Get pointer to rpi_firmware structure.
> > > + * @firmware_node:Pointer to the
Hi Bartosz, thanks for the review.
On Thu, 2020-11-05 at 10:13 +0100, Bartosz Golaszewski wrote:
> > +/**
> > + * devm_rpi_firmware_get - Get pointer to rpi_firmware structure.
> > + * @firmware_node:Pointer to the firmware Device Tree node.
> > + *
> > + * Returns NULL is the firmware device
On Wed, Nov 4, 2020 at 11:39 AM Nicolas Saenz Julienne
wrote:
>
> When unbinding the firmware device we need to make sure it has no
> consumers left. Otherwise we'd leave them with a firmware handle
> pointing at freed memory.
>
> Keep a reference count of all consumers and introduce
>
On Wed, Nov 4, 2020 at 11:39 AM Nicolas Saenz Julienne
wrote:
>
> Use devm_rpi_firmware_get() so as to make sure we release RPi's firmware
> interface when unbinding the device.
>
> Signed-off-by: Nicolas Saenz Julienne
>
> ---
>
> Changes since v2:
> - Use devm_rpi_firmware_get(), instead of
On Wednesday 4 November 2020 20:15:54 CET Rob Herring wrote:
> On Wed, 04 Nov 2020 16:51:45 +0100, Jerome Pouiller wrote:
> > From: Jérôme Pouiller
> >
> > Signed-off-by: Jérôme Pouiller
> > ---
> > .../bindings/net/wireless/silabs,wfx.yaml | 131 ++
> > 1 file changed, 131
Hi Paul,
On Fri, Oct 23, 2020 at 07:45:43PM +0200, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the A83T MIPI CSI-2
> controller.
>
> Signed-off-by: Paul Kocialkowski
> ---
> .../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 158 ++
> 1 file changed,
Hi Paul,
On Fri, Oct 23, 2020 at 07:45:40PM +0200, Paul Kocialkowski wrote:
> The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 controller
> found on Allwinner SoCs such as the A31 and V3/V3s.
>
> It is a standalone block, connected to the CSI controller on one side
> and to the MIPI D-PHY
> On 02/11/2020 15:18, Maxime Ripard wrote:
> > On Mon, Nov 02, 2020 at 10:26:22PM +0800, Zhang Qilong wrote:
> >> pm_runtime_get_sync will increment pm usage counter even it failed.
> >> Forgetting to pm_runtime_put_noidle will result in reference leak in
> >> cedrus_start_streaming. We should
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