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Re: [PATCH v9 03/13] media: hantro: Use syscon instead of 'ctrl' register
Hi Benjamin, On Mon, 2021-06-28 at 15:35 +0200, Benjamin Gaignard wrote: > > Le 16/04/2021 à 12:54, Lucas Stach a écrit : > > Am Mittwoch, dem 07.04.2021 um 09:35 +0200 schrieb Benjamin Gaignard: > > > In order to be able to share the control hardware block between > > > VPUs use a syscon instead a ioremap it in the driver. > > > To keep the compatibility with older DT if 'nxp,imx8mq-vpu-ctrl' > > > phandle is not found look at 'ctrl' reg-name. > > > With the method it becomes useless to provide a list of register > > > names so remove it. > > Sorry for putting a spoke in the wheel after many iterations of the > > series. > > > > We just discussed a way forward on how to handle the clocks and resets > > provided by the blkctl block on i.MX8MM and later and it seems there is > > a consensus on trying to provide virtual power domains from a blkctl > > driver, controlling clocks and resets for the devices in the power > > domain. I would like to avoid introducing yet another way of handling > > the blkctl and thus would like to align the i.MX8MQ VPU blkctl with > > what we are planning to do on the later chip generations. > > > > CC'ing Jacky Bai and Peng Fan from NXP, as they were going to give this > > virtual power domain thing a shot. > > Hey guys, > > I may I have miss them but I haven't see patches about power domain for IMX8MQ > VPU control block ? > Is it something that you still plan to do ? > If not, I can resend my patches where I use syscon. > Please see "soc: imx: add i.MX BLK-CTL support" [1] sent by Peng a couple weeks ago. It adds the VPUMIX for i.MX8MM, so it seems the best way forward is to follow that design, extending it for i.MX8MQ. That's still under discussion, but hopefully it will be sorted out for v5.15. Speaking of i.MX8MM, I got a report that the Hantro G1 block mostly work, but needs to be restricted to 1920x1080. If you could add a new compatible and variant for that, maybe we can find someone to test it. [1] https://lore.kernel.org/linux-arm-kernel/7683ab0b-f905-dff1-aa4f-76ad638da...@oss.nxp.com/T/#mf73fe4a13aec0a8e633a14a5d9c2d5609799acb4 Kindly, Ezequiel ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v9 03/13] media: hantro: Use syscon instead of 'ctrl' register
Le 16/04/2021 à 12:54, Lucas Stach a écrit :
Am Mittwoch, dem 07.04.2021 um 09:35 +0200 schrieb Benjamin Gaignard:
In order to be able to share the control hardware block between
VPUs use a syscon instead a ioremap it in the driver.
To keep the compatibility with older DT if 'nxp,imx8mq-vpu-ctrl'
phandle is not found look at 'ctrl' reg-name.
With the method it becomes useless to provide a list of register
names so remove it.
Sorry for putting a spoke in the wheel after many iterations of the
series.
We just discussed a way forward on how to handle the clocks and resets
provided by the blkctl block on i.MX8MM and later and it seems there is
a consensus on trying to provide virtual power domains from a blkctl
driver, controlling clocks and resets for the devices in the power
domain. I would like to avoid introducing yet another way of handling
the blkctl and thus would like to align the i.MX8MQ VPU blkctl with
what we are planning to do on the later chip generations.
CC'ing Jacky Bai and Peng Fan from NXP, as they were going to give this
virtual power domain thing a shot.
Hey guys,
I may I have miss them but I haven't see patches about power domain for IMX8MQ
VPU control block ?
Is it something that you still plan to do ?
If not, I can resend my patches where I use syscon.
Regards,
Benjamin
Regards,
Lucas
Signed-off-by: Benjamin Gaignard
Reviewed-by: Philipp Zabel
---
version 9:
- Corrections in commit message
version 7:
- Add Philipp reviewed-by tag.
- Change syscon phandle name.
version 5:
- use syscon instead of VPU reset driver.
- if DT doesn't provide syscon keep backward compatibilty by using
'ctrl' reg-name.
drivers/staging/media/hantro/hantro.h | 5 +-
drivers/staging/media/hantro/imx8m_vpu_hw.c | 52 -
2 files changed, 34 insertions(+), 23 deletions(-)
diff --git a/drivers/staging/media/hantro/hantro.h
b/drivers/staging/media/hantro/hantro.h
index 6c1b888abe75..37b9ce04bd4e 100644
--- a/drivers/staging/media/hantro/hantro.h
+++ b/drivers/staging/media/hantro/hantro.h
@@ -13,6 +13,7 @@
#define HANTRO_H_
#include
+#include
#include
#include
#include
@@ -167,7 +168,7 @@ hantro_vdev_to_func(struct video_device *vdev)
* @reg_bases:Mapped addresses of VPU registers.
* @enc_base: Mapped address of VPU encoder register for convenience.
* @dec_base: Mapped address of VPU decoder register for convenience.
- * @ctrl_base: Mapped address of VPU control block.
+ * @ctrl_base: Regmap of VPU control block.
* @vpu_mutex:Mutex to synchronize V4L2 calls.
* @irqlock: Spinlock to synchronize access to data structures
*shared with interrupt handlers.
@@ -186,7 +187,7 @@ struct hantro_dev {
void __iomem **reg_bases;
void __iomem *enc_base;
void __iomem *dec_base;
- void __iomem *ctrl_base;
+ struct regmap *ctrl_base;
struct mutex vpu_mutex; /* video_device lock */
spinlock_t irqlock;
diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c
b/drivers/staging/media/hantro/imx8m_vpu_hw.c
index c222de075ef4..8d0c3425234b 100644
--- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
@@ -7,6 +7,7 @@
#include
#include
+#include
#include "hantro.h"
#include "hantro_jpeg.h"
@@ -24,30 +25,28 @@
#define CTRL_G1_PP_FUSE 0x0c
#define CTRL_G2_DEC_FUSE 0x10
+static const struct regmap_config ctrl_regmap_ctrl = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 0x14,
+};
+
static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits)
{
- u32 val;
-
/* Assert */
- val = readl(vpu->ctrl_base + CTRL_SOFT_RESET);
- val &= ~reset_bits;
- writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);
+ regmap_update_bits(vpu->ctrl_base, CTRL_SOFT_RESET, reset_bits, 0);
udelay(2);
/* Release */
- val = readl(vpu->ctrl_base + CTRL_SOFT_RESET);
- val |= reset_bits;
- writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);
+ regmap_update_bits(vpu->ctrl_base, CTRL_SOFT_RESET,
+ reset_bits, reset_bits);
}
static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits)
{
- u32 val;
-
- val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE);
- val |= clock_bits;
- writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE);
+ regmap_update_bits(vpu->ctrl_base, CTRL_CLOCK_ENABLE,
+ clock_bits, clock_bits);
}
static int imx8mq_runtime_resume(struct hantro_dev *vpu)
@@ -64,9 +63,9 @@ static int imx8mq_runtime_resume(struct hantro_dev *vpu)
imx8m_clk_enable(vpu, CLOCK_G1 | CLOCK_G2);
/* Set values of the fuse registers */
- writel(0x, vpu->ctrl_base + CTRL_G1_DEC_FUSE);
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