Video decoder, found on NVIDIA Tegra20 SoC, supports a standard set of
video formats like H.264 / MPEG-4 / WMV / VC1. Currently driver supports
decoding of CAVLC H.264 only.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
.../bindings/arm/tegra/nvidia,tegra20-vde.txt | 43 +
d
- Miscellaneous code cleanups
- Changed 'TODO'
- CC'd media maintainers for the review as per Greg K-H request,
v1 can be viewed at https://lkml.org/lkml/2017/9/25/606
Dmitry Osipenko (2):
staging: Introduce NVIDIA Tegra20 video decoder driver
ARM: dts: tegra20: Add video
Add a device node for the video decoder engine found on Tegra20.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
arch/arm/boot/dts/tegra20.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
to
> help improve the system]
>
> url:
> https://github.com/0day-ci/linux/commits/Dmitry-Osipenko/staging-Introduce-NVIDIA-Tegra20-video-decoder-driver/20171006-101015
> config: ia64-allmodconfig (attached as .config)
> compiler: ia64-linux-gcc (GCC) 6.2.0
On 12.10.2017 13:57, Jon Hunter wrote:
>
> On 12/10/17 11:51, Dmitry Osipenko wrote:
>> On 12.10.2017 11:49, Jon Hunter wrote:
>>>
>>> On 11/10/17 21:08, Dmitry Osipenko wrote:
>>>> Add a device node for the video decoder engine found on Tegra20.
>
On 12.10.2017 11:49, Jon Hunter wrote:
>
> On 11/10/17 21:08, Dmitry Osipenko wrote:
>> Add a device node for the video decoder engine found on Tegra20.
>>
>> Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
>> ---
>> arch/arm/boot/dts/tegra20.dtsi | 1
Hello Vladimir,
On 12.10.2017 10:43, Vladimir Zapolskiy wrote:
> Hello Dmitry,
>
> On 10/11/2017 11:08 PM, Dmitry Osipenko wrote:
>> Add a device node for the video decoder engine found on Tegra20.
>>
>> Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
>>
On 26.09.2017 02:01, Stephen Warren wrote:
> On 09/25/2017 04:15 PM, Dmitry Osipenko wrote:
>> Video decoder, found on NVIDIA Tegra20 SoC, supports a standard set of
>> video formats like H.264 / MPEG-4 / WMV / VC1. Currently driver supports
>> decoding of CAVLC H.264 only.
&g
interface, so any video player that supports VDPAU can provide
accelerated video decoding on Tegra20 on Linux.
[0] https://github.com/grate-driver/libvdpau-tegra
Dmitry Osipenko (2):
staging: Introduce NVIDIA Tegra20 video decoder driver
ARM: dts: tegra20: Add video decoder node
.../bindings
Video decoder, found on NVIDIA Tegra20 SoC, supports a standard set of
video formats like H.264 / MPEG-4 / WMV / VC1. Currently driver supports
decoding of CAVLC H.264 only.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
.../bindings/arm/tegra/nvidia,tegra20-vde.txt | 38 +
d
Add a device node for the video decoder engine found on Tegra20.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
arch/arm/boot/dts/tegra20.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
On 27.09.2017 00:35, Greg Kroah-Hartman wrote:
> On Tue, Sep 26, 2017 at 03:32:23PM +0300, Dmitry Osipenko wrote:
>> On 26.09.2017 09:54, Greg Kroah-Hartman wrote:
>>> On Tue, Sep 26, 2017 at 01:15:41AM +0300, Dmitry Osipenko wrote:
>>>> This driver provides accele
On 26.09.2017 09:54, Greg Kroah-Hartman wrote:
> On Tue, Sep 26, 2017 at 01:15:41AM +0300, Dmitry Osipenko wrote:
>> This driver provides accelerated video decoding to NVIDIA Tegra20 SoC's,
>> it is a result of reverse-engineering efforts. Driver has been tested on
>> Toshib
On 28.09.2017 10:23, Dan Carpenter wrote:
> On Thu, Sep 28, 2017 at 02:28:04AM +0300, Dmitry Osipenko wrote:
>>>> + if (is_baseline_profile)
>>>> + frame->aux_paddr = 0xF4DEAD00;
>>>
>>> The handling of is_baseline_profile is strange
On 27.09.2017 12:45, Dan Carpenter wrote:
>> --- /dev/null
>> +++ b/drivers/staging/tegra-vde/Kconfig
>> @@ -0,0 +1,6 @@
>> +config TEGRA_VDE
>> +tristate "NVIDIA Tegra20 video decoder driver"
>> +depends on ARCH_TEGRA_2x_SOC
>
> Could we get a || COMPILE_TEST here as well?
>
Good
much for the awesome review. I agree with the most of the
comments.
> On Tue, Sep 26, 2017 at 01:15:42AM +0300, Dmitry Osipenko wrote:
>> diff --git a/drivers/staging/tegra-vde/Kconfig
>> b/drivers/staging/tegra-vde/Kconfig
>> new file mode 100644
>> index 00
On 26.09.2017 08:11, Stephen Warren wrote:
> On 09/25/2017 05:45 PM, Dmitry Osipenko wrote:
>> On 26.09.2017 02:01, Stephen Warren wrote:
>>> On 09/25/2017 04:15 PM, Dmitry Osipenko wrote:
>>>> Video decoder, found on NVIDIA Tegra20 SoC, supports a standard set of
On 11.10.2017 23:47, Nicolas Dufresne wrote:
> Le mercredi 11 octobre 2017 à 23:08 +0300, Dmitry Osipenko a écrit :
>> diff --git a/drivers/staging/tegra-vde/TODO b/drivers/staging/tegra-
>> vde/TODO
>> new file mode 100644
>> index ..e98bbc7b3c19
>&g
Stephen Warren and Dan Carpenter
- Implemented runtime PM
- Miscellaneous code cleanups
- Changed 'TODO'
- CC'd media maintainers for the review as per Greg K-H request,
v1 can be viewed at https://lkml.org/lkml/2017/9/25/606
Dmitry Osipenko (2):
staging
Video decoder, found on NVIDIA Tegra20 SoC, supports a standard set of
video formats like H.264 / MPEG-4 / WMV / VC1. Currently driver supports
decoding of CAVLC H.264 only.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
.../bindings/arm/tegra/nvidia,tegra20-vde.txt | 44 +
d
Add a device node for the video decoder engine found on Tegra20.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
arch/arm/boot/dts/tegra20.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
On 12.10.2017 16:45, Jon Hunter wrote:
>
> On 12/10/17 14:25, Thierry Reding wrote:
>> * PGP Signed by an unknown key
>>
>> On Thu, Oct 12, 2017 at 03:06:17PM +0300, Dmitry Osipenko wrote:
>>> Hello Vladimir,
>>>
>>> On 12.10.2017
On 18.10.2017 00:13, Rob Herring wrote:
> On Tue, Oct 17, 2017 at 3:24 PM, Thierry Reding
> wrote:
>> On Tue, Oct 17, 2017 at 03:13:54PM -0500, Rob Herring wrote:
>> [...]
diff --git
a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-vde.txt
On 12.12.2017 03:26, Dmitry Osipenko wrote:
> VDE driver provides accelerated video decoding to NVIDIA Tegra SoC's,
> it is a result of reverse-engineering efforts. Driver has been tested on
> Toshiba AC100 and Acer A500, it should work on any Tegra20 device.
>
> In usersp
On 11.11.2017 17:06, Vladimir Zapolskiy wrote:
> Hi Dmitry,
>
> I'll add just a couple of minor comments, in general the code looks
> very good.
>
Thank you very much for the review!
> On 10/20/2017 12:34 AM, Dmitry Osipenko wrote:
>> NVIDIA Tegra20/30/114/124/132
On 11.11.2017 17:21, Vladimir Zapolskiy wrote:
> Hi Dmitry,
>
> On 10/20/2017 12:34 AM, Dmitry Osipenko wrote:
>> Add binding documentation for the Video Decoder Engine which is found
>> on NVIDIA Tegra20/30/114/124/132 SoC's.
>>
>> Signed-off-by:
On 11.11.2017 17:18, Vladimir Zapolskiy wrote:
> Hi Dmitry,
>
> On 10/20/2017 12:34 AM, Dmitry Osipenko wrote:
>> From: Vladimir Zapolskiy <v...@mleia.com>
>>
>> All Tegra SoCs contain 256KiB IRAM, which is used to store CPU resume code
>> and b
Hi Hans,
On 04.12.2017 17:04, Hans Verkuil wrote:
> Hi Dmitry,
>
> As you already mention in the TODO, this should become a v4l2 codec driver.
>
> Good existing examples are the coda, qcom/venus and mtk-vcodec drivers.
>
> One thing that is not clear from this code is if the tegra hardware is
On 10.12.2017 22:29, Nicolas Dufresne wrote:
> Le dimanche 10 décembre 2017 à 21:56 +0300, Dmitry Osipenko a écrit :
>>> I've CC-ed Maxime and Giulio as well: they are looking into adding support
>>> for
>>> the stateless allwinner codec based on thi
NVIDIA Tegra20/30/114/124/132 SoC's have video decoder engine that
supports standard set of video formats like H.264 / MPEG-4 / WMV / VC1.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
MAINTAINERS |9 +
drivers/staging/media/K
Add binding documentation for the Video Decoder Engine which is found
on NVIDIA Tegra20/30/114/124/132 SoC's.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
Acked-by: Rob Herring <r...@kernel.org>
---
.../devicetree/bindings/media/nvidia,tegra-vde.txt | 55 ++
Add Video Decoder Engine device node.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
arch/arm/boot/dts/tegra20.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 36909d
From: Vladimir Zapolskiy <v...@mleia.com>
All Tegra20 SoCs contain 256KiB IRAM, which is used to store
resume code and by a video decoder engine.
Signed-off-by: Vladimir Zapolskiy <v...@mleia.com>
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
arch/arm/boot/dt
TODO'
- CC'd media maintainers for the review as per Greg's K-H request,
v1 can be viewed at https://lkml.org/lkml/2017/9/25/606
Dmitry Osipenko (3):
media: dt: bindings: Add binding for NVIDIA Tegra Video Decoder Engine
staging: media: Introduce NVIDIA Tegra video decoder driver
DMA requests must be blocked before resetting VDE HW, otherwise it is
possible to get a memory corruption or a machine hang. Use the reset
control provided by the Memory Controller to block DMA before resetting
the VDE HW.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
drivers/s
Hook up Memory Client reset of the Video Decoder to the decoders DT node.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
arch/arm/boot/dts/tegra20.dtsi | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/t
Hook up Memory Client reset of the Video Decoder to the decoders DT node.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
arch/arm/boot/dts/tegra30.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra3
On 20.05.2018 16:48, Dmitry Osipenko wrote:
> DMA requests must be blocked before resetting VDE HW, otherwise it is
> possible to get a memory corruption or a machine hang. Use the reset
> control provided by the Memory Controller to block DMA before resetting
> the VDE HW.
>
DMA requests must be blocked before resetting VDE HW, otherwise it is
possible to get a memory corruption or a machine hang. Use the reset
control provided by the Memory Controller to block DMA before resetting
the VDE HW.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
Changelo
A failed memory client reset doesn't prevent VDE from resetting, hence
reset VDE regardless of preceding memory client resetting failure.
Signed-off-by: Dmitry Osipenko
---
drivers/staging/media/tegra-vde/tegra-vde.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff
On 29.05.2018 09:18, Hans Verkuil wrote:
> Hi Dmitry,
>
> On 05/26/2018 04:27 PM, Dmitry Osipenko wrote:
>> DMA requests must be blocked before resetting VDE HW, otherwise it is
>> possible to get a memory corruption or a machine hang. Use the reset
>> control provid
Compile Tegra VDE driver as a module.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
arch/arm/configs/tegra_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 6678f2929356..c931bd
From: Vladimir Zapolskiy
All Tegra SoCs contain 256KiB IRAM, which is used to store CPU resume code
and by hardware engines like a video decoder.
Signed-off-by: Vladimir Zapolskiy
---
arch/arm/boot/dts/tegra114.dtsi | 8
arch/arm/boot/dts/tegra124.dtsi
NVIDIA Tegra20/30/114/124/132 SoC's have video decoder engine that
supports standard set of video formats like H.264 / MPEG-4 / WMV / VC1.
Currently implemented decoding of CAVLC H.264 on Tegra20 only.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
drivers/staging/K
Add Video Decoder Engine device node.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
arch/arm/boot/dts/tegra20.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index aaf32f
Add binding documentation for the Video Decoder Engine which is found
on NVIDIA Tegra20/30/114/124/132 SoC's.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
.../devicetree/bindings/media/nvidia,tegra-vde.txt | 55 ++
1 file changed, 55 insertions(+)
create mode
CC'd media maintainers for the review as per Greg's K-H request,
v1 can be viewed at https://lkml.org/lkml/2017/9/25/606
Dmitry Osipenko (4):
media: dt: bindings: Add binding for NVIDIA Tegra Video Decoder Engine
staging: Introduce NVIDIA Tegra video decoder driver
ARM: dts: tegra20:
> config TEGRA_VDE
> tristate "NVIDIA Tegra Video Decoder Engine driver"
> depends on ARCH_TEGRA || COMPILE_TEST
> + select DMA_SHARED_BUFFER
> select SRAM
> help
> Say Y here to enable support for the NVIDIA Tegra
On Wednesday, 25 July 2018 04:20:29 MSK Dmitry Osipenko wrote:
> On Wednesday, 25 July 2018 03:37:33 MSK Mauro Carvalho Chehab wrote:
> > Em Wed, 25 Jul 2018 01:38:37 +0300
> >
> > Dmitry Osipenko escreveu:
> > > On Wednesday, 25 July 2018 01:06:52 MSK Mauro Carvalh
On Monday, 13 August 2018 17:50:14 MSK Thierry Reding wrote:
> From: Thierry Reding
>
> The BSEV clock has a separate gate bit and can not be assumed to be
> always enabled. Add explicit handling for the BSEV clock and reset.
>
> This fixes an issue on Tegra124 where the BSEV clock is not
On Tuesday, 14 August 2018 17:21:24 MSK Thierry Reding wrote:
> On Mon, Aug 13, 2018 at 06:09:46PM +0300, Dmitry Osipenko wrote:
> > On Monday, 13 August 2018 17:50:14 MSK Thierry Reding wrote:
> > > From: Thierry Reding
> > >
> > > The BSEV clock has a sepa
On Tuesday, 14 August 2018 18:05:51 MSK Dmitry Osipenko wrote:
> On Tuesday, 14 August 2018 17:21:24 MSK Thierry Reding wrote:
> > On Mon, Aug 13, 2018 at 06:09:46PM +0300, Dmitry Osipenko wrote:
> > > On Monday, 13 August 2018 17:50:14 MSK Thierry Reding wrote:
> >
On Monday, 13 August 2018 17:50:22 MSK Thierry Reding wrote:
> From: Thierry Reding
>
> Implement support for using an IOMMU to map physically discontiguous
> buffers into contiguous I/O virtual mappings that the VDE can use. This
> allows importing arbitrary DMA-BUFs for use by the VDE.
>
>
On Monday, 13 August 2018 17:50:23 MSK Thierry Reding wrote:
> From: Thierry Reding
>
> There is no point in keeping the VDE module out of reset when it is not
> in use. Reset it on runtime suspend.
>
> Signed-off-by: Thierry Reding
> ---
> drivers/staging/media/tegra-vde/tegra-vde.c | 1 +
>
On 13.08.2018 17:50, Thierry Reding wrote:
> From: Thierry Reding
>
> Implement support for using an IOMMU to map physically discontiguous
> buffers into contiguous I/O virtual mappings that the VDE can use. This
> allows importing arbitrary DMA-BUFs for use by the VDE.
>
> While at it, make
On 13.08.2018 17:50, Thierry Reding wrote:
> From: Thierry Reding
>
> Implement support for using an IOMMU to map physically discontiguous
> buffers into contiguous I/O virtual mappings that the VDE can use. This
> allows importing arbitrary DMA-BUFs for use by the VDE.
>
> While at it, make
On 13.08.2018 17:50, Thierry Reding wrote:
> From: Thierry Reding
>
> The pointer to the struct device is frequently used, so store it in
> struct tegra_vde. Also, pass around a pointer to a struct tegra_vde
> instead of struct device in some cases to prepare for subsequent
> patches referencing
dev_err(dev, "Invalid dmabuf FD: %d\n", fd);
> return PTR_ERR(dmabuf);
> }
Reviewed-by: Dmitry Osipenko
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
44
> --- a/arch/arm/boot/dts/tegra124.dtsi
> +++ b/arch/arm/boot/dts/tegra124.dtsi
> @@ -321,6 +321,8 @@
> resets = <_car 61>,
><_car 63>;
> reset-names = "vde", "bsev";
> +
> +
On Monday, 13 August 2018 17:50:24 MSK Thierry Reding wrote:
> From: Thierry Reding
>
> Signed-off-by: Thierry Reding
> ---
> arch/arm/boot/dts/tegra124.dtsi | 40 +
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm/boot/dts/tegra124.dtsi
>
value = 0;
> + value = 0x3f;
> }
>
> tegra_vde_setup_iram_entry(vde, num_ref_pics, 0, i, value,
Reviewed-by: Dmitry Osipenko
Tested-by: Dmitry Osipenko
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
mabufs(vde, _frames[i], dma_dir,
> ctx.baseline_profile);
> }
>
> @@ -1089,10 +1094,12 @@ static int tegra_vde_ioctl_decode_h264(struct
> tegra_vde *vde,
>
> release_bitstream_dmabuf:
> if (secure_attachment)
> -
On Monday, 13 August 2018 17:50:20 MSK Thierry Reding wrote:
> From: Thierry Reding
>
> Add some comments specifying what tables are being set up in VRAM.
>
> Signed-off-by: Thierry Reding
> ---
> drivers/staging/media/tegra-vde/tegra-vde.c | 19 +++
> 1 file changed, 19
On Monday, 13 August 2018 17:50:16 MSK Thierry Reding wrote:
> From: Thierry Reding
>
> The number of frames doubles when decoding interlaced content and the
> structures describing the frames double in size. Take that into account
> to prepare for interlacing support.
>
> Signed-off-by:
On Monday, 13 August 2018 17:50:15 MSK Thierry Reding wrote:
> From: Thierry Reding
>
> Tegra114 and Tegra124 support reference picture marking, which will
> cause BSEV to write picture marking data to SDRAM. Make sure there is
> a valid destination address for that data to avoid error messages
On Monday, 13 August 2018 17:50:17 MSK Thierry Reding wrote:
> From: Thierry Reding
>
> VDE on Tegra20 through Tegra114 supports reading and writing frames in
> 16x16 tiled layout. Similarily, the various block-linear layouts that
> are supported by the GPU on Tegra124 can also be read from and
On Wednesday, 25 July 2018 01:06:52 MSK Mauro Carvalho Chehab wrote:
> Em Sat, 7 Jul 2018 19:20:49 +0300
>
> Dmitry Osipenko escreveu:
> > Trace points are much more efficient than debug messages for extensive
> > tracing and could be conveniently enabled / disabled dynamic
On Wednesday, 25 July 2018 03:37:33 MSK Mauro Carvalho Chehab wrote:
> Em Wed, 25 Jul 2018 01:38:37 +0300
>
> Dmitry Osipenko escreveu:
> > On Wednesday, 25 July 2018 01:06:52 MSK Mauro Carvalho Chehab wrote:
> > > Em Sat, 7 Jul 2018 19:20:49 +0300
> > >
Trace points are much more efficient than debug messages for extensive
tracing and could be conveniently enabled / disabled dynamically, hence
let's replace debug messages with the trace points.
Signed-off-by: Dmitry Osipenko
---
Changelog:
v2:
- Use __assign_str() for copying of HW
On Sunday, 20 May 2018 16:48:44 MSK Dmitry Osipenko wrote:
> Hook up Memory Client reset of the Video Decoder to the decoders DT node.
>
> Signed-off-by: Dmitry Osipenko
Thierry, is there anything I could do in order to get these patche
Trace points are much more efficient than debug messages for extensive
tracing and could be conveniently enabled / disabled dynamically, hence
let's replace debug messages with the trace points.
Signed-off-by: Dmitry Osipenko
---
drivers/staging/media/tegra-vde/tegra-vde.c | 221
I've noticed that decoding fails sometime if size of bitstream buffer
isn't aligned to 16K, probably because HW fetches data from memory in
a 16K granularity and if the last chunk of data isn't aligned, HW reads
garbage data beyond the dmabuf and tries to parse it.
Signed-off-by: Dmitry Osipenko
This is Open Firmware driver, hence 'of_device.h' should be included
instead of 'platform_device.h'. Right now OF headers happen to be included
indirectly and this may break in the future, so let's correct the header.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
drivers/staging
is the best bet now for the
proper VDE reset. So here is a small patchset that addresses couple of
minor issues that I've spotted over time.
Dmitry Osipenko (5):
media: staging: tegra-vde: Align bitstream size to 16K
media: staging: tegra-vde: Silence some of checkpatch warnings
media: staging
Make all strings single line to make them grep'able and add a comment
to the memory barrier.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
drivers/staging/media/tegra-vde/tegra-vde.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/staging
Stride of U/V planes must be aligned to 16 bytes (2 macroblocks). This
needs to be taken into account, otherwise it is possible to get a silent
memory corruption if dmabuf size is less than the size of decoded video
frame.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
drivers/s
Do not handle interrupts if we haven't asked for them, potentially that
could happen if HW wasn't programmed properly.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
drivers/staging/media/tegra-vde/tegra-vde.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/staging
B_frame = %d\n",
> + "\tFrame %d: frame_num = %d B_frame = %lu\n",
> i + 1, frame->frame_num,
> (frame->flags & FLAG_B_FRAME));
> } else {
>
Tha
On 09.11.2018 17:32, Hans Verkuil wrote:
> On 11/08/18 12:02, Colin King wrote:
>> From: Colin Ian King
>>
>> The frame.flags & FLAG_B_FRAME is promoted to a long unsigned because
>> of the use of the BIT() macro when defining FLAG_B_FRAME and causing a
>> build warning. Fix this by using the %lu
On 07.11.2018 5:23, rafaelgoncal...@riseup.net wrote:
> From: Rafael Goncalves
>
> Correct the following warnings from checkpatch.pl:
>
> WARNING: __packed is preferred over __attribute__((packed))
> +} __attribute__((packed));
>
> WARNING: __packed is preferred over __attribute__((packed))
>
On 13.11.2018 19:52, Dmitry Osipenko wrote:
> On 09.11.2018 17:32, Hans Verkuil wrote:
>> On 11/08/18 12:02, Colin King wrote:
>>> From: Colin Ian King
>>>
>>> The frame.flags & FLAG_B_FRAME is promoted to a long unsigned because
>>> of the
Trace points are much more efficient than debug messages for intensive
tracing and could be conveniently enabled / disabled dynamically, hence
let's replace debug messages with the trace points. This also makes
code a bit cleaner.
Signed-off-by: Dmitry Osipenko
---
Changelog:
v3
Enable IOMMU support for the video decoder.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 934caa83c8db..ce162125e7bf 100644
--- a/arch/arm/boot/dts
and displaying without use of V4L.
Signed-off-by: Dmitry Osipenko
---
arch/arm/configs/tegra_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 8f5c6a5b444c..a27592d3b1fa 100644
--- a/arch/arm/configs/tegra_defconfig
on Tegra30+.
Dmitry Osipenko (4):
staging: media: tegra-vde: Remove BIT() macro from UAPI header
staging: media: tegra-vde: Manually pack UAPI structures
staging: media: tegra-vde: Add IOMMU support
staging: media: tegra-vde: Defer dmabuf's unmapping
drivers/staging/media/tegra-vde/Kconfig
All Tegra's could provide memory isolation for the video decoder
hardware using IOMMU, it is also required for Tegra30+ in order
to handle sparse dmabuf's which GPU exports in a default kernel
configuration.
Inspired-by: Thierry Reding
Signed-off-by: Dmitry Osipenko
---
drivers/staging/media
also benefit a tad from the caching since CPU cache maintenance
that happens on dmabuf's attaching takes some resources.
Signed-off-by: Dmitry Osipenko
---
drivers/staging/media/tegra-vde/Makefile | 2 +-
.../staging/media/tegra-vde/dmabuf-cache.c| 223 ++
drivers/staging
-by: Dmitry Osipenko
---
drivers/staging/media/tegra-vde/tegra-vde.c | 13 +-
drivers/staging/media/tegra-vde/uapi.h | 44 +++--
2 files changed, 34 insertions(+), 23 deletions(-)
diff --git a/drivers/staging/media/tegra-vde/tegra-vde.c
b/drivers/staging/media/tegra-vde
All NVIDIA Tegra SoC generations provide IOMMU support for the video
decoder engine. Document new optional device-tree property that connects
VDE with the IOMMU provider.
Signed-off-by: Dmitry Osipenko
---
Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt | 2 ++
1 file changed, 2
The BIT macro isn't available in userspace. Checkpatch complains about
shifts being used instead of the macro and people are starting to send
patches without realizing that it's a UAPI header file. Hence let's
replace the BIT macro with a hex values to make everyone happy.
Signed-off-by: Dmitry
17.06.2019 16:31, Hans Verkuil пишет:
> On 6/2/19 11:37 PM, Dmitry Osipenko wrote:
>> All Tegra's could provide memory isolation for the video decoder
>> hardware using IOMMU, it is also required for Tegra30+ in order
>> to handle sparse dmabuf's which GPU export
and displaying without use of V4L.
Signed-off-by: Dmitry Osipenko
---
arch/arm/configs/tegra_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 8f5c6a5b444c..a27592d3b1fa 100644
--- a/arch/arm/configs/tegra_defconfig
Enable IOMMU support for the video decoder.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 934caa83c8db..ce162125e7bf 100644
--- a/arch/arm/boot/dts
The BIT macro isn't available in userspace. Checkpatch complains about
shifts being used instead of the macro and people are starting to send
patches without realizing that it's a UAPI header file. Hence let's
replace the BIT macro with a hex values to make everyone happy.
Signed-off-by: Dmitry
All NVIDIA Tegra SoC generations provide IOMMU support for the video
decoder engine. Document new optional device-tree property that connects
VDE with the IOMMU provider.
Signed-off-by: Dmitry Osipenko
---
Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt | 2 ++
1 file changed, 2
kernel config).
- Made some extra minor changes, prettifying code a tad more.
Dmitry Osipenko (4):
staging: media: tegra-vde: Remove BIT() macro from UAPI header
staging: media: tegra-vde: Manually pack UAPI structures
staging: media: tegra-vde: Add IOMMU support
staging: media: tegra-vde
also benefit a tad from the caching since CPU cache maintenance
that happens on dmabuf's attaching takes some resources.
Signed-off-by: Dmitry Osipenko
---
drivers/staging/media/tegra-vde/Makefile | 2 +-
.../staging/media/tegra-vde/dmabuf-cache.c| 226 ++
drivers/staging
-by: Dmitry Osipenko
---
drivers/staging/media/tegra-vde/tegra-vde.c | 13 +-
drivers/staging/media/tegra-vde/uapi.h | 44 +++--
2 files changed, 34 insertions(+), 23 deletions(-)
diff --git a/drivers/staging/media/tegra-vde/tegra-vde.c
b/drivers/staging/media/tegra-vde
All Tegra's could provide memory isolation for the video decoder
hardware using IOMMU, it is also required for Tegra30+ in order
to handle sparse dmabuf's which GPU exports in a default kernel
configuration.
Inspired-by: Thierry Reding
Signed-off-by: Dmitry Osipenko
---
drivers/staging/media
17.06.2019 16:33, Hans Verkuil пишет:
> On 6/2/19 11:37 PM, Dmitry Osipenko wrote:
>> Frequent IOMMU remappings take about 50% of CPU usage because there is
>> quite a lot to remap. Defer dmabuf's unmapping by 5 seconds in order to
>> mitigate the mapping overhead which
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