Quoting Mauro Carvalho Chehab (2021-01-29 11:51:57)
> The Hisilicon 6421v600 SPMI driver is ready for mainstream.
>
> So, move it from staging.
>
> Signed-off-by: Mauro Carvalho Chehab
> ---
Acked-by: Stephen Boyd
Rob had some comments on the binding that don't look to
Quoting Sergio Paracuellos (2021-01-17 06:19:36)
> Hi all,
>
> On Sun, Dec 20, 2020 at 10:37 AM Sergio Paracuellos
> wrote:
> >
> > - Hardcode "xtal" as parent in FIXED macro.
> > - Change 'else if' clause into 'if' clause since a return statement was
> >being used in 'mt7621_xtal_recalc_ra
Quoting Sergio Paracuellos (2021-03-08 21:22:23)
> diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig
> new file mode 100644
> index ..3e3f5cb9ad88
> --- /dev/null
> +++ b/drivers/clk/ralink/Kconfig
> @@ -0,0 +1,15 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +#
> +
Quoting Sergio Paracuellos (2021-03-08 21:22:21)
> Adds dt binding header for 'mediatek,mt7621-clk' clocks.
>
> Acked-by: Rob Herring
> Signed-off-by: Sergio Paracuellos
> ---
Applied to clk-next
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Quoting Sergio Paracuellos (2021-03-08 21:22:22)
> Adds device tree binding documentation for clocks in the
> MT7621 SOC.
>
> Reviewed-by: Rob Herring
> Signed-off-by: Sergio Paracuellos
> ---
Applied to clk-next
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Quoting Sergio Paracuellos (2021-03-23 01:13:22)
> On Tue, Mar 9, 2021 at 6:22 AM Sergio Paracuellos
> wrote:
> >
> > Changes in v11:
> > - Collect Rob's Reviewed-by in bindings documentation patch.
> > - Fix MAINTAINERS patch using file 'mediatek,mt7621-sysc.yaml'
> >for documentation bindi
Quoting Sergio Paracuellos (2021-04-09 11:34:35)
> On Fri, Apr 9, 2021 at 8:14 PM Stephen Boyd wrote:
> >
> > Quoting Sergio Paracuellos (2021-03-08 21:22:23)
> > > diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
> > > new file mod
Quoting Michal Simek (2021-04-08 03:40:29)
>
>
> On 4/8/21 12:26 PM, Shubhrajyoti Datta wrote:
> > On Sun, Mar 7, 2021 at 1:50 AM Rob Herring wrote:
> >>
> >> On Wed, Feb 24, 2021 at 06:40:40PM +0530, Shubhrajyoti Datta wrote:
> >>> Add the devicetree binding for the xilinx clocking wizard.
> >>
Quoting Sergio Paracuellos (2021-04-09 22:50:56)
> The documentation for this SOC only talks about two
> registers regarding to the clocks:
> * SYSC_REG_CPLL_CLKCFG0 - provides some information about
> boostrapped refclock. PLL and dividers used for CPU and some
> sort of BUS.
> * SYSC_REG_CPLL_CLK
Quoting Sergio Paracuellos (2021-04-09 22:50:57)
> Clocks for SoC mt7621 have been properly integrated so there is
> no need to declare fixed clocks at all in the device tree. Remove
> all of them, add new device tree nodes for mt7621-clk and update
> the rest of the nodes to use them.
>
> Acked-b
Quoting Sergio Paracuellos (2021-04-09 22:50:58)
> Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml'
> contains 'mediatek' as a valid vendor string. Some nodes in the device
> tree are using an invalid vendor string vfor 'mtk' instead. Fix all of
> them in dts file. Update als
Quoting Sergio Paracuellos (2021-04-09 22:50:59)
> Adding myself as maintainer for mt7621 clock driver.
>
> Signed-off-by: Sergio Paracuellos
> ---
Applied to clk-next
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Quoting Shubhrajyoti Datta (2020-08-28 06:39:53)
> Currently the set rate granularity is to integral divisors.
> Add support for the fractional divisors.
> Only the first output0 is fractional in the hardware.
>
> Signed-off-by: Shubhrajyoti Datta
Getting closer.
> diff --git a/drivers/clk/clk-
Quoting Shubhrajyoti Datta (2020-08-28 06:39:50)
> Add clocking wizard driver to clk.
>
> Signed-off-by: Shubhrajyoti Datta
> ---
Can this be combined with patch #6? And then use git format-patch -C -M
when generating patches? I'm trying to see if anything changed from the
file in the staging tr
Quoting Stephen Boyd (2020-09-21 14:19:59)
> Quoting Shubhrajyoti Datta (2020-08-28 06:39:50)
> > Add clocking wizard driver to clk.
> >
> > Signed-off-by: Shubhrajyoti Datta
> > ---
>
> Can this be combined with p
Quoting Shubhrajyoti Datta (2020-08-28 06:39:52)
> The patch adds support for dynamic reconfiguration of clock output rate.
> Output clocks are registered as dividers and set rate callback function
> is used for dynamic reconfiguration.
>
> Based on the initial work from Chirag.
>
> Signed-off-by
Quoting Shubhrajyoti Datta (2020-09-23 23:23:11)
>
> > -Original Message-
> > From: Stephen Boyd
> > Sent: Tuesday, September 22, 2020 2:48 AM
> > > +}
> > > +
> > > +static long clk_wzrd_round_
Quoting Mauro Carvalho Chehab (2020-10-09 05:15:30)
> Several *.txt files got converted to yaml. Update their
> references at MAINTAINERS file accordingly.
>
> Signed-off-by: Mauro Carvalho Chehab
> ---
Acked-by: Stephen Boyd
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Quoting Krzysztof Kozlowski (2020-11-15 09:09:48)
> COMMON_CLK even though is a user-selectable symbol, is still selected by
> multiple other config options. COMMON_CLK should not be used when
> legacy clocks are provided by architecture, so it correctly depends on
> !HAVE_LEGACY_CLK.
>
> However
Quoting Krzysztof Kozlowski (2020-11-17 23:48:12)
> On Tue, Nov 17, 2020 at 11:41:57PM -0800, Stephen Boyd wrote:
> > Quoting Krzysztof Kozlowski (2020-11-15 09:09:48)
> > > COMMON_CLK even though is a user-selectable symbol, is still selected by
> > > multiple other
was enabled. Now that isn't necessary and any
user-selectable options should be moved to depends syntax.
Reviewed-by: Stephen Boyd
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Quoting Krzysztof Kozlowski (2020-11-25 06:15:05)
> On Tue, Nov 24, 2020 at 04:11:31PM -0800, Stephen Boyd wrote:
> >
> > Ok so this patch isn't necessary then?
>
> For this particular build failure - it is not necessary anymore.
>
> However there might more of s
Quoting Nicolas Saenz Julienne (2020-12-11 08:47:52)
> Use devm_rpi_firmware_get() so as to make sure we release RPi's firmware
> interface when unbinding the device.
>
> Signed-off-by: Nicolas Saenz Julienne
> Reviewed-by: Florian Fainelli
> ---
uce rpi_firmware_put()
> which will permit automatically decrease the reference count upon
> unbinding consumer drivers.
>
> Suggested-by: Uwe Kleine-König
> Signed-off-by: Nicolas Saenz Julienne
> Reviewed-by: Florian Fainelli
>
> ---
Reviewed-by: Stephen Boyd
_
Quoting Shubhrajyoti Datta (2020-11-04 07:06:40)
>
> Shubhrajyoti Datta (7):
> dt-bindings: add documentation of xilinx clocking wizard
Any chance to respond to Robs comments?
> clk: clock-wizard: Add the clockwizard to clk directory
Is it called 'wizard' anywhere in the documentation? I wo
Quoting Michal Simek (2020-12-15 01:13:46)
>
> Can you please take a look at this series?
>
I did, see
https://lore.kernel.org/r/16078386.1580929.1950826106627397...@swboyd.mtv.corp.google.com
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Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> Adds device tree binding documentation for clocks in the
> MT7621 SOC.
>
> Signed-off-by: Sergio Paracuellos
> ---
> .../bindings/clock/mediatek,mt7621-clk.yaml | 67 +++
> 1 file changed, 67 insertions(+)
> create mode 100644
Quoting Sergio Paracuellos (2020-11-22 01:55:53)
> The documentation for this SOC only talks about two
> registers regarding to the clocks:
> * SYSC_REG_CPLL_CLKCFG0 - provides some information about
> boostrapped refclock. PLL and dividers used for CPU and some
> sort of BUS.
> * SYSC_REG_CPLL_CLK
Quoting Sergio Paracuellos (2020-12-17 02:01:39)
>
> On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd wrote:
> >
> > Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> >
> > > diff --git
> > > a/Documentation/devicetree/bindings/clock/mediatek,mt7621-
Quoting Sergio Paracuellos (2020-12-17 01:54:18)
>
> On Thu, Dec 17, 2020 at 10:09 AM Stephen Boyd wrote:
> >
> > Quoting Sergio Paracuellos (2020-11-22 01:55:53)
> > > diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
> > > new file
Quoting Jonathan Cameron (2018-12-08 07:29:54)
> On Thu, 6 Dec 2018 11:10:51 +0200
> Mircea Caprioru wrote:
>
> > This patch adds a clock to the state structure of ad7192 for getting the
> > external clock frequency. This modifications is in accordance with clock
> > framework dt bindings documen
Quoting Jonathan Cameron (2018-12-16 02:07:41)
> Rob, Clk experts, questions for you below.
>
> Jonathan
>
>
> On Thu, 13 Dec 2018 17:39:22 -0800
> Stephen Boyd wrote:
>
> > Quoting Jonathan Cameron (2018-12-08 07:29:54)
> > > On Thu, 6 Dec 2018 11:1
The subject of this patch is confusing. Not sure what it has to do with
"MIPS:" so maybe remove that and prefix it "dt-bindings: clock:"
instead.
Quoting Chuanhong Guo (2019-07-09 11:20:14)
> This patch adds dt binding header for mediatek,mt7621-pll
>
> Signed-off-by: Weijie Gao
> Signed-off-by:
Quoting Chuanhong Guo (2019-07-09 11:20:15)
> For a long time the mt7621 uses a fixed cpu clock which causes a problem
> if the cpu frequency is not 880MHz.
>
> This patch fixes the cpu clock calculation and adds the cpu/bus clkdev
> which will be used in dts.
>
> Ported from OpenWrt:
> c7ca22429
Quoting Chuanhong Guo (2019-07-09 11:20:16)
> This commit adds device tree binding documentation for MT7621
> PLL controller.
>
> Signed-off-by: Chuanhong Guo
> ---
> .../bindings/clock/mediatek,mt7621-pll.txt| 19 +++
> 1 file changed, 19 insertions(+)
> create mode 100644
Kroah-Hartman
Cc: de...@driverdev.osuosl.org
Cc: Greg Kroah-Hartman
Signed-off-by: Stephen Boyd
---
Please apply directly to subsystem trees
drivers/staging/emxx_udc/emxx_udc.c | 4 +---
drivers/staging/goldfish/goldfish_audio.c| 4 +---
drivers/staging/media/alleg
Quoting Hans de Goede (2017-09-19 11:35:50)
> Hi,
>
> On 09/08/2017 05:54 PM, Peter Rosin wrote:
> > On 2017-09-08 17:45, Peter Rosin wrote:
> >> From: Stephen Boyd
> >>
> >> Sometimes drivers only use muxes under certain scenarios. For
> >> ex
Quoting Rui Miguel Silva (2018-04-23 06:47:38)
> Fix the mipi dphy root divider to mipi_dphy_pre_div, this would remove a
> orphan
> clock and set the correct parent.
>
> before:
> cat clk_orphan_summary
> enable prepare protect
>clock
Quoting Rui Miguel Silva (2018-05-17 05:50:24)
> Fix the mipi dphy root divider to mipi_dphy_pre_div, this would remove a
> orphan
> clock and set the correct parent.
>
> before:
> cat clk_orphan_summary
> enable prepare protect
>clock
Quoting Rui Miguel Silva (2018-05-22 07:52:36)
> Fix the mipi dphy root divider to mipi_dphy_pre_div, this would remove a
> orphan
> clock and set the correct parent.
>
> before:
> cat clk_orphan_summary
> enable prepare protect
>clock
Quoting Rui Miguel Silva (2018-05-22 07:52:37)
> To guarantee that we do not get Overflow in image FIFO the outer bandwidth has
> to be faster than inputer bandwidth. For that it must be possible to set a
> faster frequency clock. So set new parent to sys_pfd3 clock for the mipi csi
> block.
>
> A
Quoting shubhrajyoti.da...@gmail.com (2019-11-27 22:36:16)
> From: Shubhrajyoti Datta
>
> Delete the driver from the staging as it is in drivers/clk.
>
> Signed-off-by: Shubhrajyoti Datta
Can all these patches in this series apply to the staging paths and be
picked up by Greg? Then when the dr
Quoting shubhrajyoti.da...@gmail.com (2019-11-27 22:36:17)
> From: Shubhrajyoti Datta
>
> After 90b6c5c73 (clk: Remove CLK_IS_BASIC clk flag)
> The CLK_IS_BASIC is deleted. Adapt the driver for the same.
I don't see any CLK_IS_BASIC in the tree right now, so did it get
reintroduced by this patch
Quoting shubhrajyoti.da...@gmail.com (2019-11-27 22:36:10)
> From: Shubhrajyoti Datta
>
> Update description for the clocking wizard structure
>
> Signed-off-by: Shubhrajyoti Datta
> ---
Reviewed-by: Stephen Boyd
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Quoting shubhrajyoti.da...@gmail.com (2019-11-27 22:36:11)
> From: Shubhrajyoti Datta
>
> The patch adds support for dynamic reconfiguration of clock output rate.
> Output clocks are registered as dividers and set rate callback function
> is used for dynamic reconfiguration.
>
> Based on the ini
Quoting shubhrajyoti.da...@gmail.com (2019-11-27 22:36:13)
> diff --git a/drivers/clk/clk-xlnx-clock-wizard.c
> b/drivers/clk/clk-xlnx-clock-wizard.c
> index bc0354a..4c6155b 100644
> --- a/drivers/clk/clk-xlnx-clock-wizard.c
> +++ b/drivers/clk/clk-xlnx-clock-wizard.c
> @@ -493,6 +493,7 @@ static
Quoting shubhrajyoti.da...@gmail.com (2019-11-27 22:36:14)
> From: Shubhrajyoti Datta
>
> Update the fixed factor clock registration to register the divisors.
>
> Signed-off-by: Shubhrajyoti Datta
> ---
> drivers/clk/clk-xlnx-clock-wizard.c | 17 +++--
> 1 file changed, 11 insertio
Quoting Shubhrajyoti Datta (2020-01-05 20:17:16)
> On Mon, Jan 6, 2020 at 1:30 AM Stephen Boyd wrote:
> >
> > Quoting shubhrajyoti.da...@gmail.com (2019-11-27 22:36:14)
> > > From: Shubhrajyoti Datta
> > >
> > > Update the fixed factor c
Quoting Alex Riesen (2020-03-20 09:12:00)
> diff --git a/drivers/media/i2c/adv748x/adv748x-dai.c
> b/drivers/media/i2c/adv748x/adv748x-dai.c
> new file mode 100644
> index ..6fce7d000423
> --- /dev/null
> +++ b/drivers/media/i2c/adv748x/adv748x-dai.c
> @@ -0,0 +1,265 @@
> +// SPDX-Lice
On 10/06/2014 10:28 PM, Guenter Roeck wrote:
> Various drivers implement architecture and/or device specific means to
> remove power from the system. For the most part, those drivers set the
> global variable pm_power_off to point to a function within the driver.
>
> This mechanism has a number of
On 06/18/2015 08:30 AM, Guenter Roeck wrote:
> On Wed, Jun 17, 2015 at 06:04:54PM -0700, Stephen Boyd wrote:
> [ ... ]
>> What happened to this series? I want to add shutdown support to my
>> platform and I need to write a register on the PMIC in one driver to
>> configure
Quoting David Gow (2020-06-29 21:45:17)
> The Xilinx Clocking Wizard driver uses the devm_ioremap_resource
> function, but does not specify a dependency on IOMEM in Kconfig. This
> causes a build failure on architectures without IOMEM, for example, UML
> (notably with make allyesconfig).
>
> Fix t
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