Add setup item "Support DPC" to enable or disable PCIe DPC
(Downstream Port Containment).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 +
Silicon/Hisili
Main Changes since v3:
1 Break patch "Support DPC" into two seperate one;
2 Rename subject of patch "Fix access variable fail issue";
Code can also be found in github:
https://github.com/hisilicon/OpenPlatformPkg.git
branch: 1902-platforms-v4
Ming Huang (3):
Hisili
Drop some PCIe menus as these menus are not ready.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr | 194
1 file changed, 194 deletions(-)
diff --git a/Silicon/Hisilicon
BmcWdtEnable is a field of OemConfigData structure, need have
runtime service attribution if use it during exit boot service
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 +-
Silicon
On 3/21/2019 8:32 PM, Leif Lindholm wrote:
> Hi Ming,
>
> On Wed, Mar 20, 2019 at 04:08:24PM +0800, Ming Huang wrote:
>> Add setup item "Support DPC" to enable or disable PCIe DPC
>> (Downstream Port Containment).
>>
>> The pcie menu is suppressed
t;
> On Thu, Mar 21, 2019 at 05:52:18PM +, Leif Lindholm wrote:
>> I will update the subject line to reflect what is actually being
>> changed.
>>
>> Other than that,
>> Reviewed-by: Leif Lindholm
>>
>>
>> On Wed, Mar 20, 2019 at 04:08:16PM
Add setup item "Support DPC" to enable or disable PCIe DPC
(Downstream Port Containment).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Reviewed-by: Leif Lindholm
---
Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 232832 -> 226
Add some registers configuration in PcieRasInitDxe and add PCIe
local RAS interrupt handle in trusted firmware to support PCIe
local RAS.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Reviewed-by: Leif Lindholm
---
Platform/Hisilicon/D06/Drivers
Numa informations are acquired from HOB that build from memory
initialization module. Correct numa informations to match booting
from TA(Totem A or super cpu cluster A).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/MemoryInitPei
As interfaces exposed only by implementations in edk2-non-osi,
so move some header files from edk2-platforms to edk2-non-osi.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Include/Library/IpmiCmdLib.h | 110
As chip group suggestions, update Mbigen and gic RAS configuration
flow.
Add below flow:
1 Reset Mbigen;
2 Disable Mbigen clock;
3 Deassert reset Mbigen;
4 Enable Mbigen clock;
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/Drivers
In new flash layout, BIOS fd change from offset 1M to 8M in 16M
spi flash.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/CustomData.Fv | Bin 0
-> 65536 bytes
Platform/Hisilicon/D06/Libr
VICES_PROTOCOL. In a TianoCore context, this should be
'BSP'. So, Rename StartupAp() to StartUpBSP.
This patch applies to D0x PlatformSysCtrlLib.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Hi1610/Library/PlatformSysCtrlLibHi
SAS controller is always existed, so accessing SAS register don't
depend on PciBusDxe (pci enumeration). Modify SAS driver remove the
dependence on pci enumeration.
This patch is done to improve boot times.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming
Main Changes since v2 :
1 Move "Add some header files" patch to the first of this series;
Code can also be found in github:
https://github.com/hisilicon/OpenPlatformPkg.git
branch: 1902-non-osi-v3
Ming Huang (8):
Hisilicon/D0x: Add some header files
Hisilicon/D06: Remove PCI e
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Reviewed-by: Leif Lindholm
---
Platform/Hisilicon/D03/D03.dsc | 4 ++--
Platform/Hisilicon/D05/D05.dsc | 4 ++--
Platform/Hisilicon/D06/D06.dsc | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff
thod in USB pci bridge 3 and pci bridge 8 to
fix usb crash when usb device is present issue.
https://bugs.linaro.org/show_bug.cgi?id=4079
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1
As new IMP(Cortex-M7) firmware support self-adapte, so do not
need BIOS to implement some function, remove useless funtions
and report CPU0/CPU1 Nic NCL offset to IMP.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/Library/OemNicLib
SP805 watchdog is no used for D0x, so remove it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Reviewed-by: Leif Lindholm
---
Platform/Hisilicon/D03/D03.dsc | 3 ---
Platform/Hisilicon/D05/D05.dsc
ntribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 +
Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 -
Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 4 +
Silicon/Hisili
Add PCI_OSC_SUPPORT for remaining host bridges to remove fail
output in kernel:
[ 103.478893] acpi PNP0A08:01: _OSC failed (AE_NOT_FOUND);
Add PCI_OSC_SUPPORT_HOTPLUG to rewrite _OSC of PCI0 and PCI6.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Follow chip team suggestion, HCCS(Huawei Cache-Coherent System)
may be unstable while speed is 3.0G, so use 2.6G to avoid some
unstable stress issue.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06
ntribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/D06.fdf | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
index d495ad7f264c..f72b513352fb 100644
--- a/Platform/Hisilicon/D06/D06
VICES_PROTOCOL. In a TianoCore context, this should be 'BSP'.
So, Rename StartupAp() to StartUpBSP.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Reviewed-by: Leif Lindholm
---
Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c
As secure boot is not ready, remove SECURE_BOOT_ENABLE and
relative code.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Reviewed-by: Leif Lindholm
---
Platform/Hisilicon/D06/D06.dsc | 12
Platform/Hisilicon/D06/D06.fdf | 11 ---
2 files
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 24
++--
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt
From: xingjiang tang
Implementation OemGetCpuFreq() to get cpu frequency from cpld to
encapsulate project difference, for some projects don't support
get cpu frequency by this way.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilico
DriverHealthManagerDxe Collect driver health form of third party
drivers to repair no healthy card.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Reviewed-by: Leif Lindholm
---
Platform/Hisilicon/D03/D03.dsc | 1 +
Platform/Hisilicon/D05/D05.dsc | 1
xe in
edk2-non-osi has been applied.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/D06.fdf | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
index a937660
As some interfaces exposed only by implementations in edk2-non-osi,
so delete corresponding header files and modify code to make build.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf
From: Jason Zhang
BmcWdtEnable is a field of OemConfigData structure, need have
runtime service attribution if use it during exit boot service
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr
.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/D06.dsc
| 2 -
Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
| 2 +-
Silicon
Main Changes since v2 :
1 Move tidy and delete header file patch to the first of the series.
Code can also be found in github:
https://github.com/hisilicon/OpenPlatformPkg.git
branch: 1902-platforms-v3
Jason Zhang (1):
Hisilicon/D06: Fix access variable fail issue
Ming Huang (16
Since NVMe riser width is 6*X4, need add the related
port's INT-x support to match OS driver.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 37
+++-
1 file change
The Bugzilla tracker for this:
https://bugzilla.tianocore.org/show_bug.cgi?id=1631
Ming Huang (1):
MdeModulePkg/UefiBootManangerLib: Fix exception issue
MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c | 3 +++
1 file changed, 3 insertions(+)
--
2.9.5
e)
So, here need to judge the status after ASSERT_EFI_ERROR.
The Bugzilla tracker for this:
https://bugzilla.tianocore.org/show_bug.cgi?id=1631
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c | 3 +++
1
On 3/19/2019 1:56 PM, Wu, Hao A wrote:
>> -Original Message-
>> From: Ming Huang [mailto:ming.hu...@linaro.org]
>> Sent: Tuesday, March 19, 2019 12:14 PM
>> To: Wu, Hao A; Leif Lindholm
>> Cc: linaro-u...@lists.linaro.org; edk2-devel@lists.01.org; Zeng
On 3/19/2019 10:25 AM, Wu, Hao A wrote:
>> -Original Message-
>> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
>> Sent: Monday, March 18, 2019 8:43 PM
>> To: Ming Huang
>> Cc: linaro-u...@lists.linaro.org; edk2-devel@lists.01.org; Zeng, Star; Don
I found this issue with a USB CDROM emulated from a BMC.
I guess have the same symptom with physical USB CDROM.
Thanks
>
> On Mon, Feb 25, 2019 at 05:10:52PM +0800, Ming Huang wrote:
>> The system environment: virtual-CDROM(USB interface) via BMC, insert a
>> iso file to CDROM,
otSendCommand (Device Error)
UsbBootRequestSense: (Device Error) CmdResult=0x1
UsbBootDetectMedia: UsbBootIsUnitReady (Device Error)
---
Ming Huang (1):
MdeModulePkg/UefiBootManangerLib: Fix exception issue
MdeModulePkg/Library/UefiBootManagerLi
e)
So, here need to judge the status not using ASSERT_EFI_ERROR.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/MdeModulePkg/Library/Ue
On 2/21/2019 1:24 AM, Leif Lindholm wrote:
> Hi Ming,
>
> Thank you for this rework.
>
> However, can you move it first in the series, so that it's obvious
> this series contains no changes to these headers (because they have
> all happened in edk2-non-osi)?
Ok.
.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/D06.dsc
| 2 -
Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
| 2 +-
Silicon
As new IMP(Cortex-M7) firmware support self-adapte, so do not
need BIOS to implement some function, remove useless funtions
and report CPU0/CPU1 Nic NCL offset to IMP.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/Library/OemNicLib
ntribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/D06.fdf | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
index d495ad7f264c..f72b513352fb 100644
--- a/Platform/Hisilicon/D06/D06
As some interfaces exposed only by implementations in edk2-non-osi,
so delete corresponding header files and modify code to make build.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Reviewed-by: Leif Lindholm
---
Platform/Hisilicon/D03/D03.dsc | 4 ++--
Platform/Hisilicon/D05/D05.dsc | 4 ++--
Platform/Hisilicon/D06/D06.dsc | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff
As secure boot is not ready, remove SECURE_BOOT_ENABLE and
relative code.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Reviewed-by: Leif Lindholm
---
Platform/Hisilicon/D06/D06.dsc | 12
Platform/Hisilicon/D06/D06.fdf | 11 ---
2 files
thod in USB pci bridge 3 and pci bridge 8 to
fix usb crash when usb device is present issue.
https://bugs.linaro.org/show_bug.cgi?id=4079
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1
SP805 watchdog is no used for D0x, so remove it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Reviewed-by: Leif Lindholm
---
Platform/Hisilicon/D03/D03.dsc | 3 ---
Platform/Hisilicon/D05/D05.dsc
From: xingjiang tang
Implementation OemGetCpuFreq() to get cpu frequency from cpld to
encapsulate project difference, for some projects don't support
get cpu frequency by this way.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilico
ntribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 +
Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 -
Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 4 +
Silicon/Hisili
Add PCI_OSC_SUPPORT for remaining host bridges to remove fail
output in kernel:
[ 103.478893] acpi PNP0A08:01: _OSC failed (AE_NOT_FOUND);
Add PCI_OSC_SUPPORT_HOTPLUG to rewrite _OSC of PCI0 and PCI6.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
VICES_PROTOCOL. In a TianoCore context, this should be 'BSP'.
So, Rename StartupAp() to StartUpBSP.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Reviewed-by: Leif Lindholm
---
Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h | 2 +-
Since NVMe riser width is 6*X4, need add the related
port's INT-x support to match OS driver.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 37
+++-
1 file change
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 24
++--
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt
Follow chip team suggestion, HCCS(Huawei Cache-Coherent System)
may be unstable while speed is 3.0G, so use 2.6G to avoid some
unstable stress issue.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Include/Library/OemMiscLib.h
xe in
edk2-non-osi has been applied.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/D06.fdf | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
index a937660
iles to edk2-non-osi/;
Code can also be found in github:
https://github.com/hisilicon/OpenPlatformPkg.git
branch: 1902-platforms-v2
Jason Zhang (1):
Hisilicon/D06: Fix access variable fail issue
Ming Huang (16):
Hisilicon/D0x: Add DriverHealthManagerDxe
Hisilicon/D06: Optimize SAS driver fo
DriverHealthManagerDxe Collect driver health form of third party
drivers to repair no healthy card.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Reviewed-by: Leif Lindholm
---
Platform/Hisilicon/D03/D03.dsc | 1 +
Platform/Hisilicon/D05/D05.dsc | 1
From: Jason Zhang
BmcWdtEnable is a field of OemConfigData structure, need have
runtime service attribution if use it during exit boot service
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr
Add setup item "Support DPC" to enable or disable PCIe DPC
(Downstream Port Containment).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Reviewed-by: Leif Lindholm
---
Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 232832 -> 226
As interfaces exposed only by implementations in edk2-non-osi,
so move some header files from edk2-platforms to edk2-non-osi.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Include/Library/IpmiCmdLib.h | 110
Numa informations are acquired from HOB that build from memory
initialization module. Correct numa informations to match booting
from TA(Totem A or super cpu cluster A).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/MemoryInitPei
Main Changes since v1 :
1 Add some header files to edk2-non-osi;
Code can also be found in github:
https://github.com/hisilicon/OpenPlatformPkg.git
branch: 1902-non-osi-v2
Ming Huang (8):
Hisilicon/D06: Remove PCI enumeration dependency from SAS driver
Hisilicon/D0x: Update
As chip group suggestions, update Mbigen and gic RAS configuration
flow.
Add below flow:
1 Reset Mbigen;
2 Disable Mbigen clock;
3 Deassert reset Mbigen;
4 Enable Mbigen clock;
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/Drivers
In new flash layout, BIOS fd change from offset 1M to 8M in 16M
spi flash.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/CustomData.Fv | Bin 0
-> 65536 bytes
Platform/Hisilicon/D06/Libr
Add some registers configuration in PcieRasInitDxe and add PCIe
local RAS interrupt handle in trusted firmware to support PCIe
local RAS.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Reviewed-by: Leif Lindholm
---
Platform/Hisilicon/D06/Drivers
VICES_PROTOCOL. In a TianoCore context, this should be
'BSP'. So, Rename StartupAp() to StartUpBSP.
This patch applies to D0x PlatformSysCtrlLib.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Hi1610/Library/PlatformSysCtrlLibHi
SAS controller is always existed, so accessing SAS register don't
depend on PciBusDxe (pci enumeration). Modify SAS driver remove the
dependence on pci enumeration.
This patch is done to improve boot times.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming
Hi Leif,
Please have a look for several outstanding patches.
Thanks
On 2/1/2019 9:34 PM, Ming Huang wrote:
> Main Changes :
> 1 Use new flash layout;
> 2 Modify for M7 self-Adapte support;
> 3 Add PCI_OSC_SUPPORT for ACPI/DSDT;
> 4 Change HCCS speed from 30G to 26G;
>
On 2/13/2019 5:42 PM, Leif Lindholm wrote:
> On Wed, Feb 13, 2019 at 02:36:11PM +0800, Ming Huang wrote:
>>> Should it not then also delete #include from
>>> Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c,
>>> Platform/Hisilicon/D06/Library/Oem
On 2/12/2019 11:26 PM, Leif Lindholm wrote:
> On Fri, Feb 01, 2019 at 10:25:05PM +0800, Ming Huang wrote:
>> In new flash layout, BIOS fd change from offset 1M to 8M in 16M
>> spi flash.
>
> I think I covered all of the layout questions in the corresponding
&
On 2/13/2019 5:42 PM, Leif Lindholm wrote:
> On Wed, Feb 13, 2019 at 02:36:11PM +0800, Ming Huang wrote:
>>> Should it not then also delete #include from
>>> Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c,
>>> Platform/Hisilicon/D06/Library/Oem
On 2/11/2019 11:05 PM, Leif Lindholm wrote:
> On Fri, Feb 01, 2019 at 09:34:21PM +0800, Ming Huang wrote:
>> SerdesLib is useless for SmbiosMiscDxe and D06, so remove it.
>
> Should it not then also delete #include from
> Platform/Hisilicon/D06/Library/OemMiscLibD06
On 2/12/2019 11:12 PM, Leif Lindholm wrote:
> On Fri, Feb 01, 2019 at 09:34:23PM +0800, Ming Huang wrote:
>> SAS controller is always existed, so accessing SAS register don't
>> depend on PciBusDxe (pci enumeration).
>> Move the SAS module early in D06.fdf for dispa
On 2/12/2019 4:52 AM, Leif Lindholm wrote:
> On Fri, Feb 01, 2019 at 10:29:06PM +0800, Ming Huang wrote:
>> This patch is relative with "Add new API CalculateCrc16()" in edk2.
>
> The commit message should describe what the patch does.
> I don't mind keeping th
On 2/11/2019 10:54 PM, Leif Lindholm wrote:
> On Fri, Feb 01, 2019 at 09:34:32PM +0800, Ming Huang wrote:
>> In new flash layout, BIOS fd change from offset 1M to 8M in 16M
>> spi flash.
>
> This bit
>
>> Use the new CustomData.Fv which indicate the offset
>&g
On 2/12/2019 11:46 PM, Leif Lindholm wrote:
> On Tue, Feb 12, 2019 at 11:14:43PM +0800, Ming Huang wrote:
>>
>>
>> On 2/12/2019 3:28 AM, Leif Lindholm wrote:
>>> On Fri, Feb 01, 2019 at 09:34:30PM +0800, Ming Huang wrote:
>>>> As new M7(Cortex-M
On 2/12/2019 2:51 AM, Leif Lindholm wrote:
> On Fri, Feb 01, 2019 at 09:34:29PM +0800, Ming Huang wrote:
>> Add PCI_OSC_SUPPORT for remaining host bridges to remove fail
>> output in kernel:
>> [ 103.478893] acpi PNP0A08:01: _OSC failed (AE_NOT_FOUND);
>>
>
On 2/12/2019 1:15 AM, Leif Lindholm wrote:
> On Fri, Feb 01, 2019 at 09:34:26PM +0800, Ming Huang wrote:
>> From: xingjiang tang
>>
>> Implementation OemGetCpuFreq() to get cpu frequency from cpld to
>> encapsulate project difference, for some projects don't
On 2/12/2019 11:17 PM, Leif Lindholm wrote:
> On Fri, Feb 01, 2019 at 09:34:24PM +0800, Ming Huang wrote:
>> From: Jason Zhang
>>
>> BmcWdtEnable is a field of OemConfigData structure, need have
>> runtime service attribution if use it during exit boot service
&
On 2/12/2019 11:20 PM, Leif Lindholm wrote:
> Change the subject line to:
> Hisilicon/D06: remove PCI enumeration dependency from SAS driver
>
> On Fri, Feb 01, 2019 at 10:25:01PM +0800, Ming Huang wrote:
>> SAS controller is always existed, so accessing SAS register
On 2/12/2019 3:46 AM, Leif Lindholm wrote:
> On Fri, Feb 01, 2019 at 09:34:31PM +0800, Ming Huang wrote:
>> Add setup item "Support DPC" to enable or disable PCIe DPC
>> (Downstream Port Containment).
>
> This patch also seems to disable the SRIOV configuration a
On 2/12/2019 3:28 AM, Leif Lindholm wrote:
> On Fri, Feb 01, 2019 at 09:34:30PM +0800, Ming Huang wrote:
>> As new M7(Cortex-M7) firmware support self-adapte, so do not
>> need BIOS to implement some function, remove useless funtions
>> and report CPU0/CPU1 Nic NCL offse
On 2/12/2019 2:36 AM, Leif Lindholm wrote:
> On Fri, Feb 01, 2019 at 09:34:28PM +0800, Ming Huang wrote:
>> Follow chip team suggestion to change HCCS(Huawei Cache-Coherent
>> System) speed from 30G to 26G, this modification can avoid some
>> unstable stress issue.
&g
On 2/12/2019 1:05 AM, Leif Lindholm wrote:
> On Fri, Feb 01, 2019 at 09:34:25PM +0800, Ming Huang wrote:
>> From: Jason Zhang
>>
>> Since NVMe riser width is 6*X4, need add the related
>> port's INT-x support to match OS driver.
>>
>> Contributed
On 2/12/2019 8:17 PM, Leif Lindholm wrote:
> On Tue, Feb 12, 2019 at 08:07:52PM +0800, Ming Huang wrote:
>>>> For D06 library, we use the same source code to support all Hi1620
>>>> projects,
>>>> include product projects,so there are some modify f
3]
[0.00] ACPI: SRAT: Node 1 PXM 1 [mem 0x-0x7fff]
[0.00] ACPI: SRAT: Node 3 PXM 3 [mem 0xa20-0xa23]o
Thanks.
>
> /
> Leif
>
> On Fri, Feb 01, 2019 at 10:25:06PM +0800, Ming Huang wrote:
>> Numa informations are acquired
On 2/12/2019 6:44 PM, Leif Lindholm wrote:
> On Tue, Feb 12, 2019 at 04:05:50PM +0800, Ming Huang wrote:
>> On 2/12/2019 5:36 AM, Leif Lindholm wrote:
>>> On Fri, Feb 01, 2019 at 10:25:02PM +0800, Ming Huang wrote:
>>>> As suggestion of community, 'AP
On 2/12/2019 5:38 AM, Leif Lindholm wrote:
> On Fri, Feb 01, 2019 at 10:25:03PM +0800, Ming Huang wrote:
>> As chip group suggestions, update Mbigen and gic RAS configuration
>> flow.
>
> Update how?
Add below flow:
1 Reset Mbigen;
2 Disable Mbigen clock;
3 Deassert r
On 2/12/2019 5:36 AM, Leif Lindholm wrote:
> On Fri, Feb 01, 2019 at 10:25:02PM +0800, Ming Huang wrote:
>> As suggestion of community, 'AP' is a bit unfortunate to use in EDK2
>> context. PI specifies 'BSP' for Boot-strap Processor, as the one
>> exe
Liming,
Agree with you. There are no other usages now.
Thanks
On 2/11/2019 10:15 PM, Gao, Liming wrote:
> Ming:
> So, there is no common CRC16 algorithm in edk2. I suggest to collect all
> CRC16 request in the firmware code, then discussion how to add
> CalculateCrc16() AP
On 2/1/2019 8:25 PM, Gao, Liming wrote:
> Ming:
> What's usage model of new Crc16()? Can they use the same algorithm in
> DebugAgent?
It is used in check MAC read from eeprom. I think they cann't use the algorithm
in
DebugAgent.
Thanks.
>
> Thanks
> Lim
On 2/1/2019 5:56 PM, Ard Biesheuvel wrote:
> On Fri, 1 Feb 2019 at 08:11, Ming Huang wrote:
>>
>>
>>
>> On 2/1/2019 2:37 PM, Ni, Ray wrote:
>>> There is an CRC16 calculation implementation in
>>> SourceLevelDebugPkg/Library/DebugAgent/De
This patch is relative with "Add new API CalculateCrc16()" in edk2.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c | 69 ++--
1 file changed, 5 insertions(+), 64 deletions(-)
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D03/D03.dsc | 4 ++--
Platform/Hisilicon/D05/D05.dsc | 4 ++--
Platform/Hisilicon/D06/D06.dsc | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/Platform/Hisilicon/D03
Add setup item "Support DPC" to enable or disable PCIe DPC
(Downstream Port Containment).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 232832 -> 226784
bytes
1 file changed,
VICES_PROTOCOL. In a TianoCore context, this should be
'BSP'. So, Rename StartupAp() to StartUpBSP.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib
| Bin 29
As chip group suggestions, update Mbigen and gic RAS configuration
flow.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Platform/Hisilicon/D06/Drivers/RasInitDxe/RasInitDxe.efi | Bin 17984 -> 18720
bytes
1 file changed, 0 insertions(+), 0 deleti
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