On Tue, 2015-08-11 at 09:42 +0200, Ard Biesheuvel wrote:
> On 11 August 2015 at 09:11, Haojian Zhuang wrote:
> > The way of accessing PL061 GPIODATA register is wrong.
> >
> > The spec said in below.
> >
> > In order to write to GPIODATA, the corresponding bits in the mask,
> > resulting from the
On 11 August 2015 at 09:11, Haojian Zhuang wrote:
> The way of accessing PL061 GPIODATA register is wrong.
>
> The spec said in below.
>
> In order to write to GPIODATA, the corresponding bits in the mask,
> resulting from the address bus, PADDR[9:2], must be HIGH. Otherwise
> the bit values remai
The way of accessing PL061 GPIODATA register is wrong.
The spec said in below.
In order to write to GPIODATA, the corresponding bits in the mask,
resulting from the address bus, PADDR[9:2], must be HIGH. Otherwise
the bit values remain unchanged by the write.
Similarly, the values read from this
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