Update FSP to follow: https://firmware.intel.com/sites/default/files/FSP_EAS_v2.0_Draft%20External.pdf
Separate SecCore to SecCoreT, SecCoreM and SecCoreS for FSP-T, FSP-M, and FSP-S. Add NASM support. The FSP1.1 compatibility is NOT maintained. The new Intel platform will follow FSP2.0. The old platform can either use an old EDK branch, or move FSP1.1 support to platform directory. Cc: Giri P Mudusuru <giri.p.mudus...@intel.com> Cc: Maurice Ma <maurice...@intel.com> Cc: Ravi P Rangarajan <ravi.p.rangara...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen....@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudus...@intel.com> Reviewed-by: Maurice Ma <maurice...@intel.com> Reviewed-by: Ravi P Rangarajan <ravi.p.rangara...@intel.com> --- IntelFspPkg/FspSecCore/FspSecCore.inf | 79 -- IntelFspPkg/FspSecCore/FspSecCoreM.inf | 74 ++ IntelFspPkg/FspSecCore/FspSecCoreS.inf | 68 ++ IntelFspPkg/FspSecCore/FspSecCoreT.inf | 66 ++ IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm | 601 --------------- IntelFspPkg/FspSecCore/Ia32/FspApiEntry.s | 813 -------------------- IntelFspPkg/FspSecCore/Ia32/FspApiEntryCommon.nasm | 76 ++ IntelFspPkg/FspSecCore/Ia32/FspApiEntryM.nasm | 207 +++++ IntelFspPkg/FspSecCore/Ia32/FspApiEntryS.nasm | 62 ++ IntelFspPkg/FspSecCore/Ia32/FspApiEntryT.nasm | 469 +++++++++++ IntelFspPkg/FspSecCore/Ia32/FspHelper.asm | 73 -- IntelFspPkg/FspSecCore/Ia32/FspHelper.nasm | 35 + IntelFspPkg/FspSecCore/Ia32/FspHelper.s | 71 -- IntelFspPkg/FspSecCore/Ia32/InitializeFpu.asm | 79 -- IntelFspPkg/FspSecCore/Ia32/InitializeFpu.nasm | 78 ++ IntelFspPkg/FspSecCore/Ia32/InitializeFpu.s | 73 -- IntelFspPkg/FspSecCore/Ia32/MicrocodeLoad.inc | 49 -- IntelFspPkg/FspSecCore/Ia32/MicrocodeLoadNasm.inc | 16 + IntelFspPkg/FspSecCore/Ia32/ResetVec.asm16 | 103 --- IntelFspPkg/FspSecCore/Ia32/SaveRestoreSse.inc | 184 ----- IntelFspPkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc | 187 +++++ IntelFspPkg/FspSecCore/Ia32/Stack.asm | 82 -- IntelFspPkg/FspSecCore/Ia32/Stack.nasm | 78 ++ IntelFspPkg/FspSecCore/Ia32/Stacks.s | 86 --- IntelFspPkg/FspSecCore/SecFsp.c | 197 ++--- IntelFspPkg/FspSecCore/SecFsp.h | 4 +- IntelFspPkg/FspSecCore/SecFspApiChk.c | 97 +++ IntelFspPkg/FspSecCore/SecMain.c | 41 +- 28 files changed, 1595 insertions(+), 2453 deletions(-) diff --git a/IntelFspPkg/FspSecCore/FspSecCore.inf b/IntelFspPkg/FspSecCore/FspSecCore.inf deleted file mode 100644 index 8dd476a..0000000 --- a/IntelFspPkg/FspSecCore/FspSecCore.inf +++ /dev/null @@ -1,79 +0,0 @@ -## @file -# Sec Core for FSP -# -# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR> -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -## - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = FspSecCore - FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09 - MODULE_TYPE = SEC - VERSION_STRING = 1.0 - -# -# The following information is for reference only and not required by the build tools. -# -# VALID_ARCHITECTURES = IA32 -# - -[Sources] - SecMain.c - SecMain.h - SecFsp.c - SecFsp.h - -[Sources.IA32] - Ia32/ResetVec.asm16 | MSFT - Ia32/Stack.asm | MSFT - Ia32/InitializeFpu.asm | MSFT - Ia32/FspApiEntry.asm | MSFT - Ia32/FspHelper.asm | MSFT - - Ia32/Stacks.s | GCC - Ia32/InitializeFpu.s | GCC - Ia32/FspApiEntry.s | GCC - Ia32/FspHelper.s | GCC - -[Binaries.Ia32] - RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC - -[Packages] - MdePkg/MdePkg.dec - IntelFspPkg/IntelFspPkg.dec - -[LibraryClasses] - BaseMemoryLib - DebugLib - BaseLib - PciCf8Lib - SerialPortLib - FspSwitchStackLib - FspCommonLib - FspSecPlatformLib - -[Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## UNDEFINED - gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES - gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES - gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES - gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES - gIntelFspPkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase ## CONSUMES - gIntelFspPkgTokenSpaceGuid.PcdFspAreaBaseAddress ## CONSUMES - gIntelFspPkgTokenSpaceGuid.PcdFspAreaSize ## CONSUMES - -[FixedPcd] - gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES - gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry ## CONSUMES - -[Ppis] - gEfiTemporaryRamSupportPpiGuid ## PRODUCES - diff --git a/IntelFspPkg/FspSecCore/FspSecCoreM.inf b/IntelFspPkg/FspSecCore/FspSecCoreM.inf new file mode 100644 index 0000000..7fab5bc --- /dev/null +++ b/IntelFspPkg/FspSecCore/FspSecCoreM.inf @@ -0,0 +1,74 @@ +## @file +# Sec Core for FSP +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = FspSecCoreM + FILE_GUID = 9AC1FEA3-ADB4-4698-B565-CA5721FC88C7 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +[Sources] + SecMain.c + SecMain.h + SecFsp.c + SecFsp.h + SecFspApiChk.c + +[Sources.IA32] + Ia32/Stack.nasm + Ia32/InitializeFpu.nasm + Ia32/FspApiEntryM.nasm + Ia32/FspApiEntryCommon.nasm + Ia32/FspHelper.nasm + +[Binaries.Ia32] + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFspPkg/IntelFspPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + BaseLib + PciCf8Lib + SerialPortLib + FspSwitchStackLib + FspCommonLib + FspSecPlatformLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## UNDEFINED + gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES + gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES + gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES + gIntelFspPkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES + +[FixedPcd] + gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES + gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry ## CONSUMES + +[Ppis] + gEfiTemporaryRamSupportPpiGuid ## PRODUCES + diff --git a/IntelFspPkg/FspSecCore/FspSecCoreS.inf b/IntelFspPkg/FspSecCore/FspSecCoreS.inf new file mode 100644 index 0000000..936e4f1 --- /dev/null +++ b/IntelFspPkg/FspSecCore/FspSecCoreS.inf @@ -0,0 +1,68 @@ +## @file +# Sec Core for FSP +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = FspSecCoreS + FILE_GUID = 2CA48C2D-3165-4d8f-8197-BFCBECCD62CD + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +[Sources] + SecFspApiChk.c + +[Sources.IA32] + Ia32/Stack.nasm + Ia32/FspApiEntryS.nasm + Ia32/FspApiEntryCommon.nasm + Ia32/FspHelper.nasm + +[Binaries.Ia32] + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFspPkg/IntelFspPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + BaseLib + PciCf8Lib + SerialPortLib + FspSwitchStackLib + FspCommonLib + FspSecPlatformLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## UNDEFINED + gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES + gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES + gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES + +[FixedPcd] + gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES + gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry ## CONSUMES + +[Ppis] + gEfiTemporaryRamSupportPpiGuid ## PRODUCES + diff --git a/IntelFspPkg/FspSecCore/FspSecCoreT.inf b/IntelFspPkg/FspSecCore/FspSecCoreT.inf new file mode 100644 index 0000000..7bb0bd4 --- /dev/null +++ b/IntelFspPkg/FspSecCore/FspSecCoreT.inf @@ -0,0 +1,66 @@ +## @file +# Sec Core for FSP +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = FspSecCoreT + FILE_GUID = CD696AF9-F091-4d5d-BB66-8D2DC6C8D96B + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +[Sources] + + +[Sources.IA32] + Ia32/Stack.nasm + Ia32/InitializeFpu.nasm + Ia32/FspApiEntryT.nasm + Ia32/FspHelper.nasm + +[Binaries.Ia32] + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFspPkg/IntelFspPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + BaseLib + PciCf8Lib + SerialPortLib + FspSwitchStackLib + FspCommonLib + FspSecPlatformLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## UNDEFINED + gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES + gIntelFspPkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES + +[FixedPcd] + gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES + gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry ## CONSUMES + +[Ppis] + gEfiTemporaryRamSupportPpiGuid ## PRODUCES diff --git a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm b/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm deleted file mode 100644 index 71e3e5a..0000000 --- a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm +++ /dev/null @@ -1,601 +0,0 @@ -;; @file -; Provide FSP API entry points. -; -; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR> -; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -;; - - .586p - .model flat,C - .code - .xmm - -INCLUDE SaveRestoreSse.inc -INCLUDE MicrocodeLoad.inc - -; -; Following are fixed PCDs -; -EXTERN PcdGet32(PcdTemporaryRamBase):DWORD -EXTERN PcdGet32(PcdTemporaryRamSize):DWORD -EXTERN PcdGet32(PcdFspTemporaryRamSize):DWORD -EXTERN PcdGet32(PcdFspAreaSize):DWORD - -; -; Following functions will be provided in C -; - -EXTERN SecStartup:PROC -EXTERN FspApiCallingCheck:PROC - -; -; Following functions will be provided in PlatformSecLib -; -EXTERN AsmGetFspBaseAddress:PROC -EXTERN AsmGetFspInfoHeader:PROC -EXTERN GetBootFirmwareVolumeOffset:PROC -EXTERN Loader2PeiSwitchStack:PROC -EXTERN LoadMicrocode(LoadMicrocodeDefault):PROC -EXTERN SecPlatformInit(SecPlatformInitDefault):PROC -EXTERN SecCarInit:PROC - -; -; Define the data length that we saved on the stack top -; -DATA_LEN_OF_PER0 EQU 18h -DATA_LEN_OF_MCUD EQU 18h -DATA_LEN_AT_STACK_TOP EQU (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4) - -; -; Define SSE macros -; -LOAD_MMX_EXT MACRO ReturnAddress, MmxRegister - mov esi, ReturnAddress - movd MmxRegister, esi ; save ReturnAddress into MMX -ENDM - -CALL_MMX_EXT MACRO RoutineLabel, MmxRegister - local ReturnAddress - mov esi, offset ReturnAddress - movd MmxRegister, esi ; save ReturnAddress into MMX - jmp RoutineLabel -ReturnAddress: -ENDM - -RET_ESI_EXT MACRO MmxRegister - movd esi, MmxRegister ; move ReturnAddress from MMX to ESI - jmp esi -ENDM - -CALL_MMX MACRO RoutineLabel - CALL_MMX_EXT RoutineLabel, mm7 -ENDM - -RET_ESI MACRO - RET_ESI_EXT mm7 -ENDM - -;------------------------------------------------------------------------------ -SecPlatformInitDefault PROC NEAR PUBLIC - ; Inputs: - ; mm7 -> Return address - ; Outputs: - ; eax -> 0 - Successful, Non-zero - Failed. - ; Register Usage: - ; eax is cleared and ebp is used for return address. - ; All others reserved. - - ; Save return address to EBP - movd ebp, mm7 - - xor eax, eax -exit: - jmp ebp -SecPlatformInitDefault ENDP - -;------------------------------------------------------------------------------ -LoadMicrocodeDefault PROC NEAR PUBLIC - ; Inputs: - ; esp -> LoadMicrocodeParams pointer - ; Register Usage: - ; esp Preserved - ; All others destroyed - ; Assumptions: - ; No memory available, stack is hard-coded and used for return address - ; Executed by SBSP and NBSP - ; Beginning of microcode update region starts on paragraph boundary - - ; - ; - ; Save return address to EBP - movd ebp, mm7 - - cmp esp, 0 - jz paramerror - mov eax, dword ptr [esp + 4] ; Parameter pointer - cmp eax, 0 - jz paramerror - mov esp, eax - mov esi, [esp].LoadMicrocodeParams.MicrocodeCodeAddr - cmp esi, 0 - jnz check_main_header - -paramerror: - mov eax, 080000002h - jmp exit - - mov esi, [esp].LoadMicrocodeParams.MicrocodeCodeAddr - -check_main_header: - ; Get processor signature and platform ID from the installed processor - ; and save into registers for later use - ; ebx = processor signature - ; edx = platform ID - mov eax, 1 - cpuid - mov ebx, eax - mov ecx, MSR_IA32_PLATFORM_ID - rdmsr - mov ecx, edx - shr ecx, 50-32 ; shift (50d-32d=18d=0x12) bits - and ecx, 7h ; platform id at bit[52..50] - mov edx, 1 - shl edx, cl - - ; Current register usage - ; esp -> stack with paramters - ; esi -> microcode update to check - ; ebx = processor signature - ; edx = platform ID - - ; Check for valid microcode header - ; Minimal test checking for header version and loader version as 1 - mov eax, dword ptr 1 - cmp [esi].MicrocodeHdr.MicrocodeHdrVersion, eax - jne advance_fixed_size - cmp [esi].MicrocodeHdr.MicrocodeHdrLoader, eax - jne advance_fixed_size - - ; Check if signature and plaform ID match - cmp ebx, [esi].MicrocodeHdr.MicrocodeHdrProcessor - jne @f - test edx, [esi].MicrocodeHdr.MicrocodeHdrFlags - jnz load_check ; Jif signature and platform ID match - -@@: - ; Check if extended header exists - ; First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid - xor eax, eax - cmp [esi].MicrocodeHdr.MicrocodeHdrTotalSize, eax - je next_microcode - cmp [esi].MicrocodeHdr.MicrocodeHdrDataSize, eax - je next_microcode - - ; Then verify total size - sizeof header > data size - mov ecx, [esi].MicrocodeHdr.MicrocodeHdrTotalSize - sub ecx, sizeof MicrocodeHdr - cmp ecx, [esi].MicrocodeHdr.MicrocodeHdrDataSize - jng next_microcode ; Jif extended header does not exist - - ; Set edi -> extended header - mov edi, esi - add edi, sizeof MicrocodeHdr - add edi, [esi].MicrocodeHdr.MicrocodeHdrDataSize - - ; Get count of extended structures - mov ecx, [edi].ExtSigHdr.ExtSigHdrCount - - ; Move pointer to first signature structure - add edi, sizeof ExtSigHdr - -check_ext_sig: - ; Check if extended signature and platform ID match - cmp [edi].ExtSig.ExtSigProcessor, ebx - jne @f - test [edi].ExtSig.ExtSigFlags, edx - jnz load_check ; Jif signature and platform ID match -@@: - ; Check if any more extended signatures exist - add edi, sizeof ExtSig - loop check_ext_sig - -next_microcode: - ; Advance just after end of this microcode - xor eax, eax - cmp [esi].MicrocodeHdr.MicrocodeHdrTotalSize, eax - je @f - add esi, [esi].MicrocodeHdr.MicrocodeHdrTotalSize - jmp check_address -@@: - add esi, dword ptr 2048 - jmp check_address - -advance_fixed_size: - ; Advance by 4X dwords - add esi, dword ptr 1024 - -check_address: - ; Is valid Microcode start point ? - cmp dword ptr [esi].MicrocodeHdr.MicrocodeHdrVersion, 0ffffffffh - jz done - - ; Is automatic size detection ? - mov eax, [esp].LoadMicrocodeParams.MicrocodeCodeSize - cmp eax, 0ffffffffh - jz @f - - ; Address >= microcode region address + microcode region size? - add eax, [esp].LoadMicrocodeParams.MicrocodeCodeAddr - cmp esi, eax - jae done ;Jif address is outside of microcode region - jmp check_main_header - -@@: -load_check: - ; Get the revision of the current microcode update loaded - mov ecx, MSR_IA32_BIOS_SIGN_ID - xor eax, eax ; Clear EAX - xor edx, edx ; Clear EDX - wrmsr ; Load 0 to MSR at 8Bh - - mov eax, 1 - cpuid - mov ecx, MSR_IA32_BIOS_SIGN_ID - rdmsr ; Get current microcode signature - - ; Verify this microcode update is not already loaded - cmp [esi].MicrocodeHdr.MicrocodeHdrRevision, edx - je continue - -load_microcode: - ; EAX contains the linear address of the start of the Update Data - ; EDX contains zero - ; ECX contains 79h (IA32_BIOS_UPDT_TRIG) - ; Start microcode load with wrmsr - mov eax, esi - add eax, sizeof MicrocodeHdr - xor edx, edx - mov ecx, MSR_IA32_BIOS_UPDT_TRIG - wrmsr - mov eax, 1 - cpuid - -continue: - jmp next_microcode - -done: - mov eax, 1 - cpuid - mov ecx, MSR_IA32_BIOS_SIGN_ID - rdmsr ; Get current microcode signature - xor eax, eax - cmp edx, 0 - jnz exit - mov eax, 08000000Eh - -exit: - jmp ebp - -LoadMicrocodeDefault ENDP - -EstablishStackFsp PROC NEAR PRIVATE - ; - ; Save parameter pointer in edx - ; - mov edx, dword ptr [esp + 4] - - ; - ; Enable FSP STACK - ; - mov esp, PcdGet32 (PcdTemporaryRamBase) - add esp, PcdGet32 (PcdTemporaryRamSize) - - push DATA_LEN_OF_MCUD ; Size of the data region - push 4455434Dh ; Signature of the data region 'MCUD' - push dword ptr [edx + 12] ; Code size - push dword ptr [edx + 8] ; Code base - push dword ptr [edx + 4] ; Microcode size - push dword ptr [edx] ; Microcode base - - ; - ; Save API entry/exit timestamp into stack - ; - push DATA_LEN_OF_PER0 ; Size of the data region - push 30524550h ; Signature of the data region 'PER0' - LOAD_EDX - push edx - LOAD_EAX - push eax - rdtsc - push edx - push eax - - ; - ; Terminator for the data on stack - ; - push 0 - - ; - ; Set ECX/EDX to the BootLoader temporary memory range - ; - mov ecx, PcdGet32 (PcdTemporaryRamBase) - mov edx, ecx - add edx, PcdGet32 (PcdTemporaryRamSize) - sub edx, PcdGet32 (PcdFspTemporaryRamSize) - - xor eax, eax - - RET_ESI - -EstablishStackFsp ENDP - - -;---------------------------------------------------------------------------- -; TempRamInit API -; -; This FSP API will load the microcode update, enable code caching for the -; region specified by the boot loader and also setup a temporary stack to be -; used till main memory is initialized. -; -;---------------------------------------------------------------------------- -TempRamInitApi PROC NEAR PUBLIC - ; - ; Ensure SSE is enabled - ; - ENABLE_SSE - - ; - ; Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6 - ; - SAVE_REGS - - ; - ; Save timestamp into XMM6 - ; - rdtsc - SAVE_EAX - SAVE_EDX - - ; - ; Check Parameter - ; - mov eax, dword ptr [esp + 4] - cmp eax, 0 - mov eax, 80000002h - jz TempRamInitExit - - ; - ; Sec Platform Init - ; - CALL_MMX SecPlatformInit - cmp eax, 0 - jnz TempRamInitExit - - ; Load microcode - LOAD_ESP - CALL_MMX LoadMicrocode - SXMMN xmm6, 3, eax ;Save microcode return status in ECX-SLOT 3 in xmm6. - ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot. - - ; Call Sec CAR Init - LOAD_ESP - CALL_MMX SecCarInit - cmp eax, 0 - jnz TempRamInitExit - - LOAD_ESP - CALL_MMX EstablishStackFsp - - LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6. - -TempRamInitExit: - ; - ; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6 - ; - LOAD_REGS - ret -TempRamInitApi ENDP - -;---------------------------------------------------------------------------- -; FspInit API -; -; This FSP API will perform the processor and chipset initialization. -; This API will not return. Instead, it transfers the control to the -; ContinuationFunc provided in the parameter. -; -;---------------------------------------------------------------------------- -FspInitApi PROC NEAR PUBLIC - mov eax, 1 - jmp FspApiCommon - FspInitApi ENDP - -;---------------------------------------------------------------------------- -; NotifyPhase API -; -; This FSP API will notify the FSP about the different phases in the boot -; process -; -;---------------------------------------------------------------------------- -NotifyPhaseApi PROC C PUBLIC - mov eax, 2 - jmp FspApiCommon -NotifyPhaseApi ENDP - -;---------------------------------------------------------------------------- -; FspMemoryInit API -; -; This FSP API is called after TempRamInit and initializes the memory. -; -;---------------------------------------------------------------------------- -FspMemoryInitApi PROC NEAR PUBLIC - mov eax, 3 - jmp FspApiCommon -FspMemoryInitApi ENDP - - -;---------------------------------------------------------------------------- -; TempRamExitApi API -; -; This API tears down temporary RAM -; -;---------------------------------------------------------------------------- -TempRamExitApi PROC C PUBLIC - mov eax, 4 - jmp FspApiCommon -TempRamExitApi ENDP - - -;---------------------------------------------------------------------------- -; FspSiliconInit API -; -; This FSP API initializes the CPU and the chipset including the IO -; controllers in the chipset to enable normal operation of these devices. -; -;---------------------------------------------------------------------------- -FspSiliconInitApi PROC C PUBLIC - mov eax, 5 - jmp FspApiCommon -FspSiliconInitApi ENDP - -;---------------------------------------------------------------------------- -; FspApiCommon API -; -; This is the FSP API common entry point to resume the FSP execution -; -;---------------------------------------------------------------------------- -FspApiCommon PROC C PUBLIC - ; - ; EAX holds the API index - ; - - ; - ; Stack must be ready - ; - push eax - add esp, 4 - cmp eax, dword ptr [esp - 4] - jz @F - mov eax, 080000003h - jmp exit - -@@: - ; - ; Verify the calling condition - ; - pushad - push [esp + 4 * 8 + 4] ; push ApiParam - push eax ; push ApiIdx - call FspApiCallingCheck - add esp, 8 - cmp eax, 0 - jz @F - mov dword ptr [esp + 4 * 7], eax - popad - ret - -@@: - popad - cmp eax, 1 ; FspInit API - jz @F - cmp eax, 3 ; FspMemoryInit API - jz @F - - call AsmGetFspInfoHeader - jmp Loader2PeiSwitchStack - -@@: - ; - ; FspInit and FspMemoryInit APIs, setup the initial stack frame - ; - - ; - ; Place holder to store the FspInfoHeader pointer - ; - push eax - - ; - ; Update the FspInfoHeader pointer - ; - push eax - call AsmGetFspInfoHeader - mov [esp + 4], eax - pop eax - - ; - ; Create a Task Frame in the stack for the Boot Loader - ; - pushfd ; 2 pushf for 4 byte alignment - cli - pushad - - ; Reserve 8 bytes for IDT save/restore - sub esp, 8 - sidt fword ptr [esp] - - ; - ; Setup new FSP stack - ; - mov edi, esp - mov esp, PcdGet32(PcdTemporaryRamBase) - add esp, PcdGet32(PcdTemporaryRamSize) - sub esp, (DATA_LEN_AT_STACK_TOP + 40h) - - ; - ; Pass the API Idx to SecStartup - ; - push eax - - ; - ; Pass the BootLoader stack to SecStartup - ; - push edi - - ; - ; Pass entry point of the PEI core - ; - call AsmGetFspBaseAddress - mov edi, eax - add edi, PcdGet32 (PcdFspAreaSize) - sub edi, 20h - add eax, DWORD PTR ds:[edi] - push eax - - ; - ; Pass BFV into the PEI Core - ; It uses relative address to calucate the actual boot FV base - ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and - ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs, - ; they are different. The code below can handle both cases. - ; - call AsmGetFspBaseAddress - mov edi, eax - call GetBootFirmwareVolumeOffset - add eax, edi - push eax - - ; - ; Pass stack base and size into the PEI Core - ; - mov eax, PcdGet32(PcdTemporaryRamBase) - add eax, PcdGet32(PcdTemporaryRamSize) - sub eax, PcdGet32(PcdFspTemporaryRamSize) - push eax - push PcdGet32(PcdFspTemporaryRamSize) - - ; - ; Pass Control into the PEI Core - ; - call SecStartup - add esp, 4 -exit: - ret - -FspApiCommon ENDP - -END diff --git a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.s b/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.s deleted file mode 100644 index d9cfcc3..0000000 --- a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.s +++ /dev/null @@ -1,813 +0,0 @@ -#------------------------------------------------------------------------------ -# -# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR> -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# Abstract: -# -# Provide FSP API entry points. -# -#------------------------------------------------------------------------------ - - -.equ MSR_IA32_PLATFORM_ID, 0x00000017 -.equ MSR_IA32_BIOS_UPDT_TRIG, 0x00000079 -.equ MSR_IA32_BIOS_SIGN_ID, 0x0000008b - - -MicrocodeHdr: -.equ MicrocodeHdrVersion, 0x0000 -.equ MicrocodeHdrRevision, 0x0004 -.equ MicrocodeHdrDate, 0x0008 -.equ MicrocodeHdrProcessor, 0x000c -.equ MicrocodeHdrChecksum, 0x0010 -.equ MicrocodeHdrLoader, 0x0014 -.equ MicrocodeHdrFlags, 0x0018 -.equ MicrocodeHdrDataSize, 0x001C -.equ MicrocodeHdrTotalSize, 0x0020 -.equ MicrocodeHdrRsvd, 0x0024 -MicrocodeHdrEnd: -.equ MicrocodeHdrLength, 0x0030 # MicrocodeHdrLength = MicrocodeHdrEnd - MicrocodeHdr - - -ExtSigHdr: -.equ ExtSigHdrCount, 0x0000 -.equ ExtSigHdrChecksum, 0x0004 -.equ ExtSigHdrRsvd, 0x0008 -ExtSigHdrEnd: -.equ ExtSigHdrLength, 0x0014 #ExtSigHdrLength = ExtSigHdrEnd - ExtSigHdr - -ExtSig: -.equ ExtSigProcessor, 0x0000 -.equ ExtSigFlags, 0x0004 -.equ ExtSigChecksum, 0x0008 -ExtSigEnd: -.equ ExtSigLength, 0x000C #ExtSigLength = ExtSigEnd - ExtSig - -LoadMicrocodeParams: -.equ MicrocodeCodeAddr, 0x0000 -.equ MicrocodeCodeSize, 0x0004 -LoadMicrocodeParamsEnd: - - - -.macro SAVE_REGS - pinsrw $0x00, %ebp, %xmm7 - ror $0x10, %ebp - pinsrw $0x01, %ebp, %xmm7 - ror $0x10, %ebp -# - pinsrw $0x02, %ebx, %xmm7 - ror $0x10, %ebx - pinsrw $0x03, %ebx, %xmm7 - ror $0x10, %ebx -# - pinsrw $0x04, %esi, %xmm7 - ror $0x10, %esi - pinsrw $0x05, %esi, %xmm7 - ror $0x10, %esi -# - pinsrw $0x06, %edi, %xmm7 - ror $0x10, %edi - pinsrw $0x07, %edi, %xmm7 - ror $0x10, %edi -# - pinsrw $0x00, %esp, %xmm6 - ror $0x10, %esp - pinsrw $0x01, %esp, %xmm6 - ror $0x10, %esp -.endm - -.macro LOAD_REGS - pshufd $0xe4, %xmm7, %xmm7 - movd %xmm7, %ebp - pshufd $0xe4, %xmm7, %xmm7 -# - pshufd $0x39, %xmm7, %xmm7 - movd %xmm7, %ebx - pshufd $0x93, %xmm7, %xmm7 -# - pshufd $0x4e, %xmm7, %xmm7 - movd %xmm7, %esi - pshufd $0x4e, %xmm7, %xmm7 -# - pshufd $0x93, %xmm7, %xmm7 - movd %xmm7, %edi - pshufd $0x39, %xmm7, %xmm7 -# - movd %xmm6, %esp -.endm - -.macro LOAD_EAX - pshufd $0x39, %xmm6, %xmm6 - movd %xmm6, %eax - pshufd $0x93, %xmm6, %xmm6 -.endm - -.macro LOAD_EDX - pshufd $0xe4, %xmm6, %xmm6 - movd %xmm6, %edx - pshufd $0xe4, %xmm6, %xmm6 -.endm - -.macro SAVE_EAX - pinsrw $0x02, %eax, %xmm6 - ror $0x10, %eax - pinsrw $0x03, %eax, %xmm6 - ror $0x10, %eax -.endm - -.macro SAVE_EDX - pinsrw $0x04, %edx, %xmm6 - ror $0x10, %edx - pinsrw $0x05, %edx, %xmm6 - ror $0x10, %edx -.endm - -.macro LOAD_ESP - movd %xmm6, %esp -.endm - -.macro ENABLE_SSE - jmp NextAddress -.align 4 - # - # Float control word initial value: - # all exceptions masked, double-precision, round-to-nearest - # -ASM_PFX(mFpuControlWord): .word 0x027F - # - # Multimedia-extensions control word: - # all exceptions masked, round-to-nearest, flush to zero for masked underflow - # -ASM_PFX(mMmxControlWord): .long 0x01F80 -SseError: - # - # Processor has to support SSE - # - jmp SseError -NextAddress: - # - # Initialize floating point units - # - finit - fldcw ASM_PFX(mFpuControlWord) - - # - # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test - # whether the processor supports SSE instruction. - # - movl $1, %eax - cpuid - btl $25, %edx - jnc SseError - - # - # Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10) - # - movl %cr4, %eax - orl $BIT9, %eax - movl %eax, %cr4 - - # - # The processor should support SSE instruction and we can use - # ldmxcsr instruction - # - ldmxcsr ASM_PFX(mMmxControlWord) -.endm - -#Save in ECX-SLOT 3 in xmm6. -.macro SAVE_EAX_MICROCODE_RET_STATUS - pinsrw $0x6, %eax, %xmm6 - ror $0x10, %eax - pinsrw $0x7, %eax, %xmm6 - rol $0x10, %eax -.endm - -#Restore from ECX-SLOT 3 in xmm6. -.macro LOAD_EAX_MICROCODE_RET_STATUS - pshufd $0x93, %xmm6, %xmm6 - movd %xmm6, %eax - pshufd $0x39, %xmm6, %xmm6 -.endm - - - -# -# Following are fixed PCDs -# -ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase) -ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize) -ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize) - -# -# Following functions will be provided in C -# -ASM_GLOBAL ASM_PFX(SecStartup) -ASM_GLOBAL ASM_PFX(FspApiCallingCheck) - -# -# Following functions will be provided in PlatformSecLib -# -ASM_GLOBAL ASM_PFX(AsmGetFspBaseAddress) -ASM_GLOBAL ASM_PFX(AsmGetFspInfoHeader) -ASM_GLOBAL ASM_PFX(GetBootFirmwareVolumeOffset) -ASM_GLOBAL ASM_PFX(Loader2PeiSwitchStack) - - -# -# Define the data length that we saved on the stack top -# -.equ DATA_LEN_OF_PER0, 0x018 -.equ DATA_LEN_OF_MCUD, 0x018 -.equ DATA_LEN_AT_STACK_TOP, (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4) - -#------------------------------------------------------------------------------ -# SecPlatformInitDefault -# Inputs: -# mm7 -> Return address -# Outputs: -# eax -> 0 - Successful, Non-zero - Failed. -# Register Usage: -# eax is cleared and ebp is used for return address. -# All others reserved. -#------------------------------------------------------------------------------ -ASM_GLOBAL ASM_PFX(SecPlatformInitDefault) -ASM_PFX(SecPlatformInitDefault): - # - # Save return address to EBP - # - movd %mm7, %ebp - xorl %eax, %eax - -SecPlatformInitDefaultExit: - jmp *%ebp - - -#------------------------------------------------------------------------------ -# LoadMicrocodeDefault -# -# Inputs: -# esp -> LoadMicrocodeParams pointer -# Register Usage: -# esp Preserved -# All others destroyed -# Assumptions: -# No memory available, stack is hard-coded and used for return address -# Executed by SBSP and NBSP -# Beginning of microcode update region starts on paragraph boundary -#------------------------------------------------------------------------------ -ASM_GLOBAL ASM_PFX(LoadMicrocodeDefault) -ASM_PFX(LoadMicrocodeDefault): - # - # Save return address to EBP - # - movd %mm7, %ebp - - cmpl $0x00, %esp - jz ParamError - movl 4(%esp), %eax #dword ptr [] Parameter pointer - cmpl $0x00, %eax - jz ParamError - movl %eax, %esp - movl MicrocodeCodeAddr(%esp), %esi - cmpl $0x00, %esi - jnz CheckMainHeader - -ParamError: - movl $0x080000002, %eax - jmp LoadMicrocodeExit - -CheckMainHeader: - # - # Get processor signature and platform ID from the installed processor - # and save into registers for later use - # ebx = processor signature - # edx = platform ID - # - movl $0x01, %eax - cpuid - movl %eax, %ebx - movl $MSR_IA32_PLATFORM_ID, %ecx - rdmsr - movl %edx, %ecx - shrl $0x12, %ecx # shift (50d-32d=18d=0x12) bits - andl $0x07, %ecx # platform id at bit[52..50] - movl $0x01, %edx - shll %cl,%edx - - # - # Current register usage - # esp -> stack with paramters - # esi -> microcode update to check - # ebx = processor signature - # edx = platform ID - # - - # - # Check for valid microcode header - # Minimal test checking for header version and loader version as 1 - # - movl $0x01, %eax - cmpl %eax, MicrocodeHdrVersion(%esi) - jne AdvanceFixedSize - cmpl %eax, MicrocodeHdrLoader(%esi) - jne AdvanceFixedSize - - # - # Check if signature and plaform ID match - # - cmpl MicrocodeHdrProcessor(%esi), %ebx - jne LoadMicrocodeL0 - testl MicrocodeHdrFlags(%esi), %edx - jnz LoadCheck #Jif signature and platform ID match - -LoadMicrocodeL0: - # - # Check if extended header exists - # First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid - # - xorl %eax, %eax - cmpl %eax, MicrocodeHdrTotalSize(%esi) - je NextMicrocode - cmpl %eax, MicrocodeHdrDataSize(%esi) - je NextMicrocode - - # - # Then verify total size - sizeof header > data size - # - movl MicrocodeHdrTotalSize(%esi), %ecx - subl $MicrocodeHdrLength, %ecx - cmpl MicrocodeHdrDataSize(%esi), %ecx - jle NextMicrocode - - # - # Set edi -> extended header - # - movl %esi, %edi - addl $MicrocodeHdrLength, %edi - addl MicrocodeHdrDataSize(%esi), %edi - - # - # Get count of extended structures - # - movl ExtSigHdrCount(%edi), %ecx - - # - # Move pointer to first signature structure - # - addl ExtSigHdrLength, %edi - -CheckExtSig: - # - # Check if extended signature and platform ID match - # - cmpl %ebx, ExtSigProcessor(%edi) - jne LoadMicrocodeL1 - test %edx, ExtSigFlags(%edi) - jnz LoadCheck # Jif signature and platform ID match -LoadMicrocodeL1: - # - # Check if any more extended signatures exist - # - addl $ExtSigLength, %edi - loop CheckExtSig - -NextMicrocode: - # - # Advance just after end of this microcode - # - xorl %eax, %eax - cmpl %eax, MicrocodeHdrTotalSize(%esi) - je LoadMicrocodeL2 - addl MicrocodeHdrTotalSize(%esi), %esi - jmp CheckAddress -LoadMicrocodeL2: - addl $0x800, %esi #add esi, dword ptr 2048 - jmp CheckAddress - -AdvanceFixedSize: - # - # Advance by 4X dwords - # - addl $0x400, %esi #add esi, dword ptr 1024 - -CheckAddress: - # - # Is valid Microcode start point ? - # - cmpl $0x0ffffffff, MicrocodeHdrVersion(%esi) - - # - # Is automatic size detection ? - # - movl MicrocodeCodeSize(%esp), %eax - cmpl $0x0ffffffff, %eax - jz LoadMicrocodeL3 - # - # Address >= microcode region address + microcode region size? - # - addl MicrocodeCodeAddr(%esp), %eax - - cmpl %eax, %esi - jae Done #Jif address is outside of microcode region - jmp CheckMainHeader - -LoadMicrocodeL3: -LoadCheck: - # - # Get the revision of the current microcode update loaded - # - movl $MSR_IA32_BIOS_SIGN_ID, %ecx - xorl %eax, %eax # Clear EAX - xorl %edx, %edx # Clear EDX - wrmsr # Load 0 to MSR at 8Bh - - movl $0x01, %eax - cpuid - movl $MSR_IA32_BIOS_SIGN_ID, %ecx - rdmsr # Get current microcode signature - - # - # Verify this microcode update is not already loaded - # - cmpl %edx, MicrocodeHdrRevision(%esi) - je Continue - -LoadMicrocode0: - # - # EAX contains the linear address of the start of the Update Data - # EDX contains zero - # ECX contains 79h (IA32_BIOS_UPDT_TRIG) - # Start microcode load with wrmsr - # - movl %esi, %eax - addl $MicrocodeHdrLength, %eax - xorl %edx, %edx - movl $MSR_IA32_BIOS_UPDT_TRIG, %ecx - wrmsr - movl $0x01, %eax - cpuid - -Continue: - jmp NextMicrocode - -Done: - movl $0x01, %eax - cpuid - movl $MSR_IA32_BIOS_SIGN_ID, %ecx - rdmsr # Get current microcode signature - xorl %eax, %eax - cmpl $0x00, %edx - jnz LoadMicrocodeExit - movl $0x08000000E, %eax - -LoadMicrocodeExit: - jmp *%ebp - - -#---------------------------------------------------------------------------- -# EstablishStackFsp -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(EstablishStackFsp) -ASM_PFX(EstablishStackFsp): - # - # Save parameter pointer in edx - # - movl 4(%esp), %edx - - # - # Enable FSP STACK - # - movl PcdGet32(PcdTemporaryRamBase), %esp - addl PcdGet32(PcdTemporaryRamSize), %esp - - pushl $DATA_LEN_OF_MCUD # Size of the data region - pushl $0x4455434D # Signature of the data region 'MCUD' - pushl 12(%edx) # Code size - pushl 8(%edx) # Code base - pushl 4(%edx) # Microcode size - pushl (%edx) # Microcode base - - # - # Save API entry/exit timestamp into stack - # - pushl $DATA_LEN_OF_PER0 # Size of the data region - pushl $0x30524550 # Signature of the data region 'PER0' - LOAD_EDX - pushl %edx - LOAD_EAX - pushl %eax - rdtsc - pushl %edx - pushl %eax - - # - # Terminator for the data on stack - # - push $0x00 - - # - # Set ECX/EDX to the BootLoader temporary memory range - # - movl PcdGet32 (PcdTemporaryRamBase), %ecx - movl %ecx, %edx - addl PcdGet32 (PcdTemporaryRamSize), %edx - subl PcdGet32 (PcdFspTemporaryRamSize), %edx - - xorl %eax, %eax - - movd %mm7, %esi #RET_ESI - jmp *%esi - -#---------------------------------------------------------------------------- -# TempRamInit API -# -# This FSP API will load the microcode update, enable code caching for the -# region specified by the boot loader and also setup a temporary stack to be -# used till main memory is initialized. -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(TempRamInitApi) -ASM_PFX(TempRamInitApi): - # - # Ensure SSE is enabled - # - ENABLE_SSE - - # - # Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6 - # - SAVE_REGS - - # - # Save timestamp into XMM6 - # - rdtsc - SAVE_EAX - SAVE_EDX - - # - # Check Parameter - # - movl 4(%esp), %eax - cmpl $0x00, %eax - movl $0x80000002, %eax - jz NemInitExit - - # - # Sec Platform Init - # - movl $TempRamInitApiL1, %esi #CALL_MMX SecPlatformInit - movd %esi, %mm7 - .weak ASM_PFX(SecPlatformInit) - .set ASM_PFX(SecPlatformInit), ASM_PFX(SecPlatformInitDefault) - jmp ASM_PFX(SecPlatformInit) -TempRamInitApiL1: - cmpl $0x00, %eax - jnz NemInitExit - - # - # Load microcode - # - LOAD_ESP - movl $TempRamInitApiL2, %esi #CALL_MMX LoadMicrocode - movd %esi, %mm7 - .weak ASM_PFX(LoadMicrocode) - .set ASM_PFX(LoadMicrocode), ASM_PFX(LoadMicrocodeDefault) - jmp ASM_PFX(LoadMicrocode) -TempRamInitApiL2: - SAVE_EAX_MICROCODE_RET_STATUS #Save microcode return status in ECX-SLOT 3 in xmm6. - #@note If return value eax is not 0, microcode did not load, but continue and attempt to boot from ECX-SLOT 3 in xmm6. - - # - # Call Sec CAR Init - # - LOAD_ESP - movl $TempRamInitApiL3, %esi #CALL_MMX SecCarInit - movd %esi, %mm7 - jmp ASM_PFX(SecCarInit) -TempRamInitApiL3: - cmpl $0x00, %eax - jnz NemInitExit - - # - # EstablishStackFsp - # - LOAD_ESP - movl $TempRamInitApiL4, %esi #CALL_MMX EstablishStackFsp - movd %esi, %mm7 - jmp ASM_PFX(EstablishStackFsp) -TempRamInitApiL4: - - LOAD_EAX_MICROCODE_RET_STATUS #Restore microcode status if no CAR init error. - -NemInitExit: - # - # Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6 - # - LOAD_REGS - ret - - -#---------------------------------------------------------------------------- -# FspInit API -# -# This FSP API will perform the processor and chipset initialization. -# This API will not return. Instead, it transfers the control to the -# ContinuationFunc provided in the parameter. -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(FspInitApi) -ASM_PFX(FspInitApi): - movl $0x01, %eax - jmp FspApiCommon - -#---------------------------------------------------------------------------- -# NotifyPhase API -# -# This FSP API will notify the FSP about the different phases in the boot -# process -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(NotifyPhaseApi) -ASM_PFX(NotifyPhaseApi): - movl $0x02, %eax - jmp FspApiCommon - -#---------------------------------------------------------------------------- -# FspMemoryInit API -# -# This FSP API is called after TempRamInit and initializes the memory. -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(FspMemoryInitApi) -ASM_PFX(FspMemoryInitApi): - movl $0x03, %eax - jmp FspApiCommon - -#---------------------------------------------------------------------------- -# TempRamExitApi API -# -# This API tears down temporary RAM -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(TempRamExitApi) -ASM_PFX(TempRamExitApi): - movl $0x04, %eax - jmp FspApiCommon - -#---------------------------------------------------------------------------- -# FspSiliconInit API -# -# This FSP API initializes the CPU and the chipset including the IO -# controllers in the chipset to enable normal operation of these devices. -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(FspSiliconInitApi) -ASM_PFX(FspSiliconInitApi): - movl $0x05, %eax - jmp FspApiCommon - -#---------------------------------------------------------------------------- -# FspApiCommon API -# -# This is the FSP API common entry point to resume the FSP execution -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(FspApiCommon) -ASM_PFX(FspApiCommon): - # - # EAX holds the API index - # - - # - # Stack must be ready - # - pushl %eax - addl $0x04, %esp - cmpl -4(%esp), %eax - jz FspApiCommonL0 - movl $0x080000003, %eax - jmp FspApiCommonExit - -FspApiCommonL0: - # - # Verify the calling condition - # - pushal - pushl 36(%esp) #push ApiParam [esp + 4 * 8 + 4] - pushl %eax #push ApiIdx - call ASM_PFX(FspApiCallingCheck) - addl $0x08, %esp - cmpl $0x00, %eax - jz FspApiCommonL1 - movl %eax, 0x1C(%esp) # mov dword ptr [esp + 4 * 7], eax - popal - ret - -FspApiCommonL1: - popal - cmpl $0x01, %eax # FspInit API - jz FspApiCommonL2 - cmpl $0x03, %eax # FspMemoryInit API - jz FspApiCommonL2 - call ASM_PFX(AsmGetFspInfoHeader) - jmp Loader2PeiSwitchStack - -FspApiCommonL2: - # - # FspInit and FspMemoryInit APIs, setup the initial stack frame - # - - # - # Place holder to store the FspInfoHeader pointer - # - pushl %eax - - # - # Update the FspInfoHeader pointer - # - pushl %eax - call ASM_PFX(AsmGetFspInfoHeader) - movl %eax, 4(%esp) - popl %eax - - # - # Create a Task Frame in the stack for the Boot Loader - # - pushfl # 2 pushf for 4 byte alignment - cli - pushal - - # - # Reserve 8 bytes for IDT save/restore - # - subl $0x08, %esp - sidt (%esp) - - # - # Setup new FSP stack - # - movl %esp, %edi - movl PcdGet32(PcdTemporaryRamBase), %esp - addl PcdGet32(PcdTemporaryRamSize), %esp - subl $(DATA_LEN_AT_STACK_TOP + 0x40), %esp - - # - # Pass the API Idx to SecStartup - # - pushl %eax - - # - # Pass the BootLoader stack to SecStartup - # - pushl %edi - - # - # Pass entry point of the PEI core - # - call ASM_PFX(AsmGetFspBaseAddress) - movl %eax, %edi - addl PcdGet32(PcdFspAreaSize), %edi - subl $0x20, %edi - addl %ds:(%edi), %eax - pushl %eax - - # - # Pass BFV into the PEI Core - # It uses relative address to calucate the actual boot FV base - # For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and - # PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs, - # they are different. The code below can handle both cases. - # - call ASM_PFX(AsmGetFspBaseAddress) - movl %eax, %edi - call ASM_PFX(GetBootFirmwareVolumeOffset) - addl %edi, %eax - pushl %eax - - # - # Pass stack base and size into the PEI Core - # - movl PcdGet32(PcdTemporaryRamBase), %eax - addl PcdGet32(PcdTemporaryRamSize), %eax - subl PcdGet32(PcdFspTemporaryRamSize), %eax - pushl %eax - pushl PcdGet32(PcdFspTemporaryRamSize) - - # - # Pass Control into the PEI Core - # - call ASM_PFX(SecStartup) - addl $4, %esp -FspApiCommonExit: - ret - diff --git a/IntelFspPkg/FspSecCore/Ia32/FspApiEntryCommon.nasm b/IntelFspPkg/FspSecCore/Ia32/FspApiEntryCommon.nasm new file mode 100644 index 0000000..c48a956 --- /dev/null +++ b/IntelFspPkg/FspSecCore/Ia32/FspApiEntryCommon.nasm @@ -0,0 +1,76 @@ +;; @file +; Provide FSP API entry points. +; +; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +;; + + SECTION .text + +; +; Following functions will be provided in C +; +extern ASM_PFX(Loader2PeiSwitchStack) +extern ASM_PFX(FspApiCallingCheck) + +; +; Following functions will be provided in ASM +; +extern ASM_PFX(FspApiCommonContinue) +extern ASM_PFX(AsmGetFspInfoHeader) + +;---------------------------------------------------------------------------- +; FspApiCommon API +; +; This is the FSP API common entry point to resume the FSP execution +; +;---------------------------------------------------------------------------- +global ASM_PFX(FspApiCommon) +ASM_PFX(FspApiCommon): + ; + ; EAX holds the API index + ; + + ; + ; Stack must be ready + ; + push eax + add esp, 4 + cmp eax, dword [esp - 4] + jz FspApiCommon1 + mov eax, 080000003h + jmp exit + +FspApiCommon1: + ; + ; Verify the calling condition + ; + pushad + push DWORD [esp + (4 * 8 + 4)] ; push ApiParam + push eax ; push ApiIdx + call ASM_PFX(FspApiCallingCheck) + add esp, 8 + cmp eax, 0 + jz FspApiCommon2 + mov dword [esp + (4 * 7)], eax + popad +exit: + ret + +FspApiCommon2: + popad + cmp eax, 3 ; FspMemoryInit API + jz FspApiCommon3 + + call ASM_PFX(AsmGetFspInfoHeader) + jmp ASM_PFX(Loader2PeiSwitchStack) + +FspApiCommon3: + jmp ASM_PFX(FspApiCommonContinue) + diff --git a/IntelFspPkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFspPkg/FspSecCore/Ia32/FspApiEntryM.nasm new file mode 100644 index 0000000..edbed23 --- /dev/null +++ b/IntelFspPkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -0,0 +1,207 @@ +;; @file +; Provide FSP API entry points. +; +; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +;; + + SECTION .text + +; +; Following are fixed PCDs +; +extern ASM_PFX(PcdGet32(PcdTemporaryRamBase)) +extern ASM_PFX(PcdGet32(PcdTemporaryRamSize)) +extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize)) + +; +; Following functions will be provided in C +; +extern ASM_PFX(SecStartup) +extern ASM_PFX(FspApiCommon) + +; +; Following functions will be provided in PlatformSecLib +; +extern ASM_PFX(AsmGetFspBaseAddress) +extern ASM_PFX(AsmGetFspInfoHeader) + +; +; Define the data length that we saved on the stack top +; +DATA_LEN_OF_PER0 EQU 18h +DATA_LEN_OF_MCUD EQU 18h +DATA_LEN_AT_STACK_TOP EQU (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4) + +API_PARAM_OFFSET EQU 34h + +;---------------------------------------------------------------------------- +; FspMemoryInit API +; +; This FSP API is called after TempRamInit and initializes the memory. +; +;---------------------------------------------------------------------------- +global ASM_PFX(FspMemoryInitApi) +ASM_PFX(FspMemoryInitApi): + mov eax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex + jmp ASM_PFX(FspApiCommon) + +;---------------------------------------------------------------------------- +; TempRamExitApi API +; +; This API tears down temporary RAM +; +;---------------------------------------------------------------------------- +global ASM_PFX(TempRamExitApi) +ASM_PFX(TempRamExitApi): + mov eax, 4 ; FSP_API_INDEX.TempRamExitApiIndex + jmp ASM_PFX(FspApiCommon) + +;---------------------------------------------------------------------------- +; FspApiCommonContinue API +; +; This is the FSP API common entry point to resume the FSP execution +; +;---------------------------------------------------------------------------- +global ASM_PFX(FspApiCommonContinue) +ASM_PFX(FspApiCommonContinue): + ; + ; EAX holds the API index + ; + + ; + ; FspMemoryInit API setup the initial stack frame + ; + + ; + ; Place holder to store the FspInfoHeader pointer + ; + push eax + + ; + ; Update the FspInfoHeader pointer + ; + push eax + call ASM_PFX(AsmGetFspInfoHeader) + mov [esp + 4], eax + pop eax + + ; + ; Create a Task Frame in the stack for the Boot Loader + ; + pushfd ; 2 pushf for 4 byte alignment + cli + pushad + + ; Reserve 8 bytes for IDT save/restore + sub esp, 8 + sidt [esp] + + ; + ; Get CAR region + ; + push edx + push ecx + push ebx + push eax ; eax holds the API index + + ; + ; Temporary set stack top pointer for C code usage by reading MTRR + ; + ; AsmReadMsr32 (0x200) & ~(0x6) + mov ecx, 200h ; Load the MTRR index: MTRR_PHYS_BASE_0 + xor edx, edx ; clear upper dword + rdmsr ; Read the value in MTRR_PHYS_BASE_0 + and eax, 0xFFFFFFF9 ; not MTRR_MEMORY_TYPE_WB + mov ebx, eax ; Car Base + ; ~(AsmReadMsr32(0x201) & ~(0x800)) + 1 + mov ecx, 201h ; For proper addressing above 4GB: MTRR_PHYS_MASK_0 + xor edx, edx ; clear upper dword + rdmsr ; Read the value in MTRR_PHYS_MASK_0 + and eax, 0xFFFFF7FF ; MTRR_PHYS_MASK_VALID + not eax + inc eax ; Car Size + add ebx, eax ; Car Base + Size + mov edi, ebx + + pop eax + pop ebx + pop ecx + pop edx + + ; + ; Setup new FSP stack + ; + xchg edi, esp ; Exchange edi and esp, edi will be assigned to the current esp pointer and esp will be CAR base + CAR size + mov ebx, esp ; Put CAR base + CAR size in ebx + sub esp, (DATA_LEN_AT_STACK_TOP + 0x40) + + ; + ; Pass the API Idx to SecStartup + ; + push eax + + ; + ; Pass the BootLoader stack to SecStartup + ; + push edi + + ; + ; Pass entry point of the PEI core + ; + call ASM_PFX(AsmGetFspBaseAddress) + mov edi, eax + call ASM_PFX(AsmGetPeiCoreOffset) + add edi, eax + push edi + + ; + ; Pass BFV into the PEI Core + ; It uses relative address to calucate the actual boot FV base + ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and + ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs, + ; they are different. The code below can handle both cases. + ; + call ASM_PFX(AsmGetFspBaseAddress) + push eax + + ; + ; Pass stack base and size into the PEI Core + ; + mov eax, ebx ; eax = CAR base + CAR size + sub eax, DWORD [ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))] + push eax + push DWORD [ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))] + + ; + ; Pass Control into the PEI Core + ; + call ASM_PFX(SecStartup) + add esp, 4 +exit: + ret + +global ASM_PFX(FspPeiCoreEntryOff) +ASM_PFX(FspPeiCoreEntryOff): + ; + ; This value will be pached by the build script + ; + DD 0x12345678 + +global ASM_PFX(AsmGetPeiCoreOffset) +ASM_PFX(AsmGetPeiCoreOffset): + mov eax, dword [ASM_PFX(FspPeiCoreEntryOff)] + ret + +;---------------------------------------------------------------------------- +; Module Entrypoint API +;---------------------------------------------------------------------------- +global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + jmp $ diff --git a/IntelFspPkg/FspSecCore/Ia32/FspApiEntryS.nasm b/IntelFspPkg/FspSecCore/Ia32/FspApiEntryS.nasm new file mode 100644 index 0000000..cdc1149 --- /dev/null +++ b/IntelFspPkg/FspSecCore/Ia32/FspApiEntryS.nasm @@ -0,0 +1,62 @@ +;; @file +; Provide FSP API entry points. +; +; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +;; + + SECTION .text + +; +; Following functions will be provided in C +; +extern ASM_PFX(FspApiCommon) + +;---------------------------------------------------------------------------- +; NotifyPhase API +; +; This FSP API will notify the FSP about the different phases in the boot +; process +; +;---------------------------------------------------------------------------- +global ASM_PFX(NotifyPhaseApi) +ASM_PFX(NotifyPhaseApi): + mov eax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex + jmp ASM_PFX(FspApiCommon) + +;---------------------------------------------------------------------------- +; FspSiliconInit API +; +; This FSP API initializes the CPU and the chipset including the IO +; controllers in the chipset to enable normal operation of these devices. +; +;---------------------------------------------------------------------------- +global ASM_PFX(FspSiliconInitApi) +ASM_PFX(FspSiliconInitApi): + mov eax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex + jmp ASM_PFX(FspApiCommon) + +;---------------------------------------------------------------------------- +; FspApiCommonContinue API +; +; This is the FSP API common entry point to resume the FSP execution +; +;---------------------------------------------------------------------------- +global ASM_PFX(FspApiCommonContinue) +ASM_PFX(FspApiCommonContinue): + jmp $ + ret + +;---------------------------------------------------------------------------- +; Module Entrypoint API +;---------------------------------------------------------------------------- +global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + jmp $ + diff --git a/IntelFspPkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFspPkg/FspSecCore/Ia32/FspApiEntryT.nasm new file mode 100644 index 0000000..3c912ec --- /dev/null +++ b/IntelFspPkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -0,0 +1,469 @@ +;; @file +; Provide FSP API entry points. +; +; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +;; + + SECTION .text + +%include "SaveRestoreSseNasm.inc" +%include "MicrocodeLoadNasm.inc" + +; +; Following are fixed PCDs +; +extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase)) +extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) +extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize)) + +; +; Following functions will be provided in PlatformSecLib +; +extern ASM_PFX(AsmGetFspBaseAddress) +extern ASM_PFX(AsmGetFspInfoHeader) +;extern ASM_PFX(LoadMicrocode) ; @todo: needs a weak implementation +extern ASM_PFX(SecPlatformInit) ; @todo: needs a weak implementation +extern ASM_PFX(SecCarInit) + +; +; Define the data length that we saved on the stack top +; +DATA_LEN_OF_PER0 EQU 18h +DATA_LEN_OF_MCUD EQU 18h +DATA_LEN_AT_STACK_TOP EQU (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4) + +; +; @todo: These structures are moved from MicrocodeLoadNasm.inc to avoid +; build error. This needs to be fixed later on. +; +struc MicrocodeHdr + .MicrocodeHdrVersion: resd 1 + .MicrocodeHdrRevision: resd 1 + .MicrocodeHdrDate: resd 1 + .MicrocodeHdrProcessor: resd 1 + .MicrocodeHdrChecksum: resd 1 + .MicrocodeHdrLoader: resd 1 + .MicrocodeHdrFlags: resd 1 + .MicrocodeHdrDataSize: resd 1 + .MicrocodeHdrTotalSize: resd 1 + .MicrocodeHdrRsvd: resd 3 + .size: +endstruc + +struc ExtSigHdr + .ExtSigHdrCount: resd 1 + .ExtSigHdrChecksum: resd 1 + .ExtSigHdrRsvd: resd 3 + .size: +endstruc + +struc ExtSig + .ExtSigProcessor: resd 1 + .ExtSigFlags: resd 1 + .ExtSigChecksum: resd 1 + .size: +endstruc + +struc LoadMicrocodeParams + ; FSP_UPD_HEADER { + .FspUpdHeader: resd 8 + ; } + ; FSPT_CORE_UPD { + .MicrocodeCodeAddr: resd 1 + .MicrocodeCodeSize: resd 1 + .CodeRegionBase: resd 1 + .CodeRegionSize: resd 1 + ; } + .size: +endstruc + + +; +; Define SSE macros +; +; +;args 1: ReturnAddress 2:MmxRegister +; +%macro LOAD_MMX_EXT 2 + mov esi, %1 + movd %2, esi ; save ReturnAddress into MMX +%endmacro + +; +;args 1: RoutineLabel 2:MmxRegister +; +%macro CALL_MMX_EXT 2 + mov esi, %%ReturnAddress + movd %2, esi ; save ReturnAddress into MMX + jmp %1 +%%ReturnAddress: +%endmacro + +; +;arg 1:MmxRegister +; +%macro RET_ESI_EXT 1 + movd esi, %1 ; move ReturnAddress from MMX to ESI + jmp esi +%endmacro + +; +;arg 1:RoutineLabel +; +%macro CALL_MMX 1 + CALL_MMX_EXT %1, mm7 +%endmacro + +%macro RET_ESI 0 + RET_ESI_EXT mm7 +%endmacro + +; +; @todo: The strong/weak implementation does not work. +; This needs to be reviewed later. +; +;------------------------------------------------------------------------------ +; +;;global ASM_PFX(SecPlatformInitDefault) +;ASM_PFX(SecPlatformInitDefault): +; ; Inputs: +; ; mm7 -> Return address +; ; Outputs: +; ; eax -> 0 - Successful, Non-zero - Failed. +; ; Register Usage: +; ; eax is cleared and ebp is used for return address. +; ; All others reserved. +; +; ; Save return address to EBP +; movd ebp, mm7 +; +; xor eax, eax +;Exit1: +; jmp ebp + +;------------------------------------------------------------------------------ +global ASM_PFX(LoadMicrocodeDefault) +ASM_PFX(LoadMicrocodeDefault): + ; Inputs: + ; esp -> LoadMicrocodeParams pointer + ; Register Usage: + ; esp Preserved + ; All others destroyed + ; Assumptions: + ; No memory available, stack is hard-coded and used for return address + ; Executed by SBSP and NBSP + ; Beginning of microcode update region starts on paragraph boundary + + ; + ; + ; Save return address to EBP + movd ebp, mm7 + + cmp esp, 0 + jz ParamError + mov eax, dword [esp + 4] ; Parameter pointer + cmp eax, 0 + jz ParamError + mov esp, eax + + mov esi, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr] + cmp esi, 0 + jnz CheckMainHeader + +ParamError: + mov eax, 080000002h + jmp Exit2 + +CheckMainHeader: + ; Get processor signature and platform ID from the installed processor + ; and save into registers for later use + ; ebx = processor signature + ; edx = platform ID + mov eax, 1 + cpuid + mov ebx, eax + mov ecx, MSR_IA32_PLATFORM_ID + rdmsr + mov ecx, edx + shr ecx, 50-32 ; shift (50d-32d=18d=0x12) bits + and ecx, 7h ; platform id at bit[52..50] + mov edx, 1 + shl edx, cl + + ; Current register usage + ; esp -> stack with paramters + ; esi -> microcode update to check + ; ebx = processor signature + ; edx = platform ID + + ; Check for valid microcode header + ; Minimal test checking for header version and loader version as 1 + mov eax, dword 1 + cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], eax + jne AdvanceFixedSize + cmp dword [esi + MicrocodeHdr.MicrocodeHdrLoader], eax + jne AdvanceFixedSize + + ; Check if signature and plaform ID match + cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor] + jne LoadMicrocodeDefault1 + test edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ] + jnz LoadCheck ; Jif signature and platform ID match + +LoadMicrocodeDefault1: + ; Check if extended header exists + ; First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid + xor eax, eax + cmp dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax + je NextMicrocode + cmp dword [esi + MicrocodeHdr.MicrocodeHdrDataSize], eax + je NextMicrocode + + ; Then verify total size - sizeof header > data size + mov ecx, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize] + sub ecx, MicrocodeHdr.size + cmp ecx, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize] + jng NextMicrocode ; Jif extended header does not exist + + ; Set edi -> extended header + mov edi, esi + add edi, MicrocodeHdr.size + add edi, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize] + + ; Get count of extended structures + mov ecx, dword [edi + ExtSigHdr.ExtSigHdrCount] + + ; Move pointer to first signature structure + add edi, ExtSigHdr.size + +CheckExtSig: + ; Check if extended signature and platform ID match + cmp dword [edi + ExtSig.ExtSigProcessor], ebx + jne LoadMicrocodeDefault2 + test dword [edi + ExtSig.ExtSigFlags], edx + jnz LoadCheck ; Jif signature and platform ID match +LoadMicrocodeDefault2: + ; Check if any more extended signatures exist + add edi, ExtSig.size + loop CheckExtSig + +NextMicrocode: + ; Advance just after end of this microcode + xor eax, eax + cmp dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax + je LoadMicrocodeDefault3 + add esi, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize] + jmp CheckAddress +LoadMicrocodeDefault3: + add esi, dword 2048 + jmp CheckAddress + +AdvanceFixedSize: + ; Advance by 4X dwords + add esi, dword 1024 + +CheckAddress: + ; Is valid Microcode start point ? + cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh + jz Done + + ; Is automatic size detection ? + mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize] + cmp eax, 0ffffffffh + jz LoadMicrocodeDefault4 + + ; Address >= microcode region address + microcode region size? + add eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr] + cmp esi, eax + jae Done ;Jif address is outside of microcode region + jmp CheckMainHeader + +LoadMicrocodeDefault4: +LoadCheck: + ; Get the revision of the current microcode update loaded + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr ; Load 0 to MSR at 8Bh + + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + + ; Verify this microcode update is not already loaded + cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx + je Continue + +LoadMicrocode: + ; EAX contains the linear address of the start of the Update Data + ; EDX contains zero + ; ECX contains 79h (IA32_BIOS_UPDT_TRIG) + ; Start microcode load with wrmsr + mov eax, esi + add eax, MicrocodeHdr.size + xor edx, edx + mov ecx, MSR_IA32_BIOS_UPDT_TRIG + wrmsr + mov eax, 1 + cpuid + +Continue: + jmp NextMicrocode + +Done: + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + xor eax, eax + cmp edx, 0 + jnz Exit2 + mov eax, 08000000Eh + +Exit2: + jmp ebp + + +global ASM_PFX(EstablishStackFsp) +ASM_PFX(EstablishStackFsp): + ; + ; Save parameter pointer in edx + ; + mov edx, dword [esp + 4] + + ; + ; Enable FSP STACK + ; + mov esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))] + add esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))] + + push DATA_LEN_OF_MCUD ; Size of the data region + push 4455434Dh ; Signature of the data region 'MCUD' + push dword [edx + 2Ch] ; Code size sizeof(FSPT_UPD_COMMON) + 12 + push dword [edx + 28h] ; Code base sizeof(FSPT_UPD_COMMON) + 8 + push dword [edx + 24h] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4 + push dword [edx + 20h] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0 + + ; + ; Save API entry/exit timestamp into stack + ; + push DATA_LEN_OF_PER0 ; Size of the data region + push 30524550h ; Signature of the data region 'PER0' + rdtsc + push edx + push eax + LOAD_EDX + push edx + LOAD_EAX + push eax + + ; + ; Terminator for the data on stack + ; + push 0 + + ; + ; Set ECX/EDX to the BootLoader temporary memory range + ; + mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))] + mov edx, ecx + add edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))] + sub edx, [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))] + + cmp ecx, edx ;If PcdFspReservedBufferSize >= PcdTemporaryRamSize, then error. + jb EstablishStackFspSuccess + mov eax, 80000003h ;EFI_UNSUPPORTED + jmp EstablishStackFspExit +EstablishStackFspSuccess: + xor eax, eax + +EstablishStackFspExit: + RET_ESI + +;---------------------------------------------------------------------------- +; TempRamInit API +; +; This FSP API will load the microcode update, enable code caching for the +; region specified by the boot loader and also setup a temporary stack to be +; used till main memory is initialized. +; +;---------------------------------------------------------------------------- +global ASM_PFX(TempRamInitApi) +ASM_PFX(TempRamInitApi): + ; + ; Ensure SSE is enabled + ; + ENABLE_SSE + + ; + ; Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6 + ; + SAVE_REGS + + ; + ; Save timestamp into XMM6 + ; + rdtsc + SAVE_EAX + SAVE_EDX + + ; + ; Check Parameter + ; + mov eax, dword [esp + 4] + cmp eax, 0 + mov eax, 80000002h + jz TempRamInitExit + + ; + ; Sec Platform Init + ; + CALL_MMX ASM_PFX(SecPlatformInit) + cmp eax, 0 + jnz TempRamInitExit + + ; Load microcode + LOAD_ESP + CALL_MMX ASM_PFX(LoadMicrocodeDefault) + SXMMN xmm6, 3, eax ;Save microcode return status in ECX-SLOT 3 in xmm6. + ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot. + + ; Call Sec CAR Init + LOAD_ESP + CALL_MMX ASM_PFX(SecCarInit) + cmp eax, 0 + jnz TempRamInitExit + + LOAD_ESP + CALL_MMX ASM_PFX(EstablishStackFsp) + cmp eax, 0 + jnz TempRamInitExit + + LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6. + +TempRamInitExit: + mov bl, al ; save al data in bl + mov al, 07Fh ; API exit postcode 7f + out 080h, al + mov al, bl ; restore al data from bl + + ; + ; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6 + ; + LOAD_REGS + ret + +;---------------------------------------------------------------------------- +; Module Entrypoint API +;---------------------------------------------------------------------------- +global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + jmp $ diff --git a/IntelFspPkg/FspSecCore/Ia32/FspHelper.asm b/IntelFspPkg/FspSecCore/Ia32/FspHelper.asm deleted file mode 100644 index b991386..0000000 --- a/IntelFspPkg/FspSecCore/Ia32/FspHelper.asm +++ /dev/null @@ -1,73 +0,0 @@ -;; @file -; Provide FSP helper function. -; -; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> -; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -;; - - .586p - .model flat,C - .code - -; -; FspInfoHeaderRelativeOff is patched during build process and initialized to offset of the AsmGetFspBaseAddress -; from the FSP Info header. -; -FspInfoHeaderRelativeOff PROC NEAR PUBLIC - ; - ; This value will be pached by the build script - ; - DD 012345678h -FspInfoHeaderRelativeOff ENDP - -; -; Returns FSP Base Address. -; -; This function gets the FSP Info Header using relative addressing and returns the FSP Base from the header structure -; -AsmGetFspBaseAddress PROC NEAR PUBLIC - mov eax, AsmGetFspBaseAddress - sub eax, dword ptr [FspInfoHeaderRelativeOff] - add eax, 01Ch - mov eax, dword ptr [eax] - ret -AsmGetFspBaseAddress ENDP - -; -; No stack counter part of AsmGetFspBaseAddress. Return address is in edi. -; -AsmGetFspBaseAddressNoStack PROC NEAR PUBLIC - mov eax, AsmGetFspBaseAddress - sub eax, dword ptr [FspInfoHeaderRelativeOff] - add eax, 01Ch - mov eax, dword ptr [eax] - jmp edi -AsmGetFspBaseAddressNoStack ENDP - -; -; Returns FSP Info Header. -; -; This function gets the FSP Info Header using relative addressing and returns it -; -AsmGetFspInfoHeader PROC NEAR PUBLIC - mov eax, AsmGetFspBaseAddress - sub eax, dword ptr [FspInfoHeaderRelativeOff] - ret -AsmGetFspInfoHeader ENDP - -; -; No stack counter part of AsmGetFspInfoHeader. Return address is in edi. -; -AsmGetFspInfoHeaderNoStack PROC NEAR PUBLIC - mov eax, AsmGetFspBaseAddress - sub eax, dword ptr [FspInfoHeaderRelativeOff] - jmp edi -AsmGetFspInfoHeaderNoStack ENDP - - END \ No newline at end of file diff --git a/IntelFspPkg/FspSecCore/Ia32/FspHelper.nasm b/IntelFspPkg/FspSecCore/Ia32/FspHelper.nasm new file mode 100644 index 0000000..00e953b --- /dev/null +++ b/IntelFspPkg/FspSecCore/Ia32/FspHelper.nasm @@ -0,0 +1,35 @@ +;; @file +; Provide FSP helper function. +; +; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR> +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +;; + + SECTION .text + +global ASM_PFX(FspInfoHeaderRelativeOff) +ASM_PFX(FspInfoHeaderRelativeOff): + ; + ; This value will be pached by the build script + ; + DD 0x12345678 + +global ASM_PFX(AsmGetFspBaseAddress) +ASM_PFX(AsmGetFspBaseAddress): + mov eax, ASM_PFX(AsmGetFspInfoHeader) + sub eax, dword [ASM_PFX(FspInfoHeaderRelativeOff)] + add eax, 0x1C + mov eax, dword [eax] + ret + +global ASM_PFX(AsmGetFspInfoHeader) +ASM_PFX(AsmGetFspInfoHeader): + mov eax, ASM_PFX(AsmGetFspInfoHeader) + sub eax, dword [ASM_PFX(FspInfoHeaderRelativeOff)] + ret diff --git a/IntelFspPkg/FspSecCore/Ia32/FspHelper.s b/IntelFspPkg/FspSecCore/Ia32/FspHelper.s deleted file mode 100644 index 55d8ae7..0000000 --- a/IntelFspPkg/FspSecCore/Ia32/FspHelper.s +++ /dev/null @@ -1,71 +0,0 @@ -#------------------------------------------------------------------------------ -# -# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# Abstract: -# -# Provide FSP helper function. -# -#------------------------------------------------------------------------------ - -# -# FspInfoHeaderRelativeOff is patched during build process and initialized to offset of the AsmGetFspBaseAddress -# from the FSP Info header. -# -ASM_GLOBAL ASM_PFX(FspInfoHeaderRelativeOff) -ASM_PFX(FspInfoHeaderRelativeOff): - # - # This value will be pached by the build script - # - .long 0x012345678 - -# -# Returns FSP Base Address. -# -# This function gets the FSP Info Header using relative addressing and returns the FSP Base from the header structure -# -ASM_GLOBAL ASM_PFX(AsmGetFspBaseAddress) -ASM_PFX(AsmGetFspBaseAddress): - mov $AsmGetFspBaseAddress, %eax - sub FspInfoHeaderRelativeOff, %eax - add $0x01C, %eax - mov (%eax), %eax - ret - -# -# No stack counter part of AsmGetFspBaseAddress. Return address is in edi. -# -ASM_GLOBAL ASM_PFX(AsmGetFspBaseAddressNoStack) -ASM_PFX(AsmGetFspBaseAddressNoStack): - mov $AsmGetFspBaseAddress, %eax - sub FspInfoHeaderRelativeOff, %eax - add $0x01C, %eax - mov (%eax), %eax - jmp *%edi - -# -# Returns FSP Info Header. -# -# This function gets the FSP Info Header using relative addressing and returns it -# -ASM_GLOBAL ASM_PFX(AsmGetFspInfoHeader) -ASM_PFX(AsmGetFspInfoHeader): - mov $AsmGetFspBaseAddress, %eax - sub FspInfoHeaderRelativeOff, %eax - ret - -# -# No stack counter part of AsmGetFspInfoHeader. Return address is in edi. -# -ASM_GLOBAL ASM_PFX(AsmGetFspInfoHeaderNoStack) -ASM_PFX(AsmGetFspInfoHeaderNoStack): - mov $AsmGetFspBaseAddress, %eax - sub FspInfoHeaderRelativeOff, %eax - jmp *%edi diff --git a/IntelFspPkg/FspSecCore/Ia32/InitializeFpu.asm b/IntelFspPkg/FspSecCore/Ia32/InitializeFpu.asm deleted file mode 100644 index 07f504d..0000000 --- a/IntelFspPkg/FspSecCore/Ia32/InitializeFpu.asm +++ /dev/null @@ -1,79 +0,0 @@ -;------------------------------------------------------------------------------ -; -; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR> -; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -; -; Abstract: -; -;------------------------------------------------------------------------------ - - .686 - .model flat,C - .const -; -; Float control word initial value: -; all exceptions masked, double-precision, round-to-nearest -; -mFpuControlWord DW 027Fh -; -; Multimedia-extensions control word: -; all exceptions masked, round-to-nearest, flush to zero for masked underflow -; -mMmxControlWord DD 01F80h - - .xmm - .code - -; -; Initializes floating point units for requirement of UEFI specification. -; -; This function initializes floating-point control word to 0x027F (all exceptions -; masked,double-precision, round-to-nearest) and multimedia-extensions control word -; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero -; for masked underflow). -; -InitializeFloatingPointUnits PROC PUBLIC - - push ebx - - ; - ; Initialize floating point units - ; - finit - fldcw mFpuControlWord - - ; - ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test - ; whether the processor supports SSE instruction. - ; - mov eax, 1 - cpuid - bt edx, 25 - jnc Done - - ; - ; Set OSFXSR bit 9 in CR4 - ; - mov eax, cr4 - or eax, BIT9 - mov cr4, eax - - ; - ; The processor should support SSE instruction and we can use - ; ldmxcsr instruction - ; - ldmxcsr mMmxControlWord -Done: - pop ebx - - ret - -InitializeFloatingPointUnits ENDP - -END diff --git a/IntelFspPkg/FspSecCore/Ia32/InitializeFpu.nasm b/IntelFspPkg/FspSecCore/Ia32/InitializeFpu.nasm new file mode 100644 index 0000000..cc87e89 --- /dev/null +++ b/IntelFspPkg/FspSecCore/Ia32/InitializeFpu.nasm @@ -0,0 +1,78 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +; Abstract: +; +;------------------------------------------------------------------------------ + + +SECTION .data +; +; Float control word initial value: +; all exceptions masked, double-precision, round-to-nearest +; +ASM_PFX(mFpuControlWord): + dw 0x027F +; +; Multimedia-extensions control word: +; all exceptions masked, round-to-nearest, flush to zero for masked underflow +; +ASM_PFX(mMmxControlWord): + dd 0x01F80 + +SECTION .text + +; +; Initializes floating point units for requirement of UEFI specification. +; +; This function initializes floating-point control word to 0x027F (all exceptions +; masked,double-precision, round-to-nearest) and multimedia-extensions control word +; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero +; for masked underflow). +; + +global ASM_PFX(InitializeFloatingPointUnits) +ASM_PFX(InitializeFloatingPointUnits): + + + push ebx + + ; + ; Initialize floating point units + ; + finit + fldcw [ASM_PFX(mFpuControlWord)] + + ; + ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test + ; whether the processor supports SSE instruction. + ; + mov eax, 1 + cpuid + bt edx, 25 + jnc Done + + ; + ; Set OSFXSR bit 9 in CR4 + ; + mov eax, cr4 + or eax, BIT9 + mov cr4, eax + + ; + ; The processor should support SSE instruction and we can use + ; ldmxcsr instruction + ; + ldmxcsr [ASM_PFX(mMmxControlWord)] +Done: + pop ebx + + ret diff --git a/IntelFspPkg/FspSecCore/Ia32/InitializeFpu.s b/IntelFspPkg/FspSecCore/Ia32/InitializeFpu.s deleted file mode 100644 index ed1ce0e..0000000 --- a/IntelFspPkg/FspSecCore/Ia32/InitializeFpu.s +++ /dev/null @@ -1,73 +0,0 @@ -#------------------------------------------------------------------------------ -# -# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR> -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# Abstract: -# -#------------------------------------------------------------------------------ - -# -# Float control word initial value: -# all exceptions masked, double-precision, round-to-nearest -# -ASM_PFX(mFpuControlWord): .word 0x027F -# -# Multimedia-extensions control word: -# all exceptions masked, round-to-nearest, flush to zero for masked underflow -# -ASM_PFX(mMmxControlWord): .long 0x01F80 - - - -# -# Initializes floating point units for requirement of UEFI specification. -# -# This function initializes floating-point control word to 0x027F (all exceptions -# masked,double-precision, round-to-nearest) and multimedia-extensions control word -# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero -# for masked underflow). -# -ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits) -ASM_PFX(InitializeFloatingPointUnits): - - pushl %ebx - - # - # Initialize floating point units - # - finit - fldcw ASM_PFX(mFpuControlWord) - - # - # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test - # whether the processor supports SSE instruction. - # - movl $1, %eax - cpuid - btl $25, %edx - jnc Done - - # - # Set OSFXSR bit 9 in CR4 - # - movl %cr4, %eax - orl $BIT9, %eax - movl %eax, %cr4 - - # - # The processor should support SSE instruction and we can use - # ldmxcsr instruction - # - ldmxcsr ASM_PFX(mMmxControlWord) - -Done: - popl %ebx - - ret diff --git a/IntelFspPkg/FspSecCore/Ia32/MicrocodeLoad.inc b/IntelFspPkg/FspSecCore/Ia32/MicrocodeLoad.inc deleted file mode 100644 index 6fbf430..0000000 --- a/IntelFspPkg/FspSecCore/Ia32/MicrocodeLoad.inc +++ /dev/null @@ -1,49 +0,0 @@ -;------------------------------------------------------------------------------ -; -; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR> -; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -; -; Abstract: -; -;------------------------------------------------------------------------------ - -MSR_IA32_PLATFORM_ID EQU 000000017h -MSR_IA32_BIOS_UPDT_TRIG EQU 000000079h -MSR_IA32_BIOS_SIGN_ID EQU 00000008bh - - -MicrocodeHdr STRUCT 1t - MicrocodeHdrVersion DWORD ? - MicrocodeHdrRevision DWORD ? - MicrocodeHdrDate DWORD ? - MicrocodeHdrProcessor DWORD ? - MicrocodeHdrChecksum DWORD ? - MicrocodeHdrLoader DWORD ? - MicrocodeHdrFlags DWORD ? - MicrocodeHdrDataSize DWORD ? - MicrocodeHdrTotalSize DWORD ? - MicrocodeHdrRsvd DWORD 3t DUP (?) -MicrocodeHdr ENDS - -ExtSigHdr STRUCT 1t - ExtSigHdrCount DWORD ? - ExtSigHdrChecksum DWORD ? - ExtSigHdrRsvd DWORD 3t DUP (?) -ExtSigHdr ENDS - -ExtSig STRUCT 1t - ExtSigProcessor DWORD ? - ExtSigFlags DWORD ? - ExtSigChecksum DWORD ? -ExtSig ENDS - -LoadMicrocodeParams STRUCT 1t - MicrocodeCodeAddr DWORD ? - MicrocodeCodeSize DWORD ? -LoadMicrocodeParams ENDS diff --git a/IntelFspPkg/FspSecCore/Ia32/MicrocodeLoadNasm.inc b/IntelFspPkg/FspSecCore/Ia32/MicrocodeLoadNasm.inc new file mode 100644 index 0000000..1663a85 --- /dev/null +++ b/IntelFspPkg/FspSecCore/Ia32/MicrocodeLoadNasm.inc @@ -0,0 +1,16 @@ +;; @file +; +;@copyright +; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR> +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +;; + +MSR_IA32_PLATFORM_ID equ 000000017h +MSR_IA32_BIOS_UPDT_TRIG equ 000000079h +MSR_IA32_BIOS_SIGN_ID equ 00000008bh \ No newline at end of file diff --git a/IntelFspPkg/FspSecCore/Ia32/ResetVec.asm16 b/IntelFspPkg/FspSecCore/Ia32/ResetVec.asm16 deleted file mode 100644 index f77c9a4..0000000 --- a/IntelFspPkg/FspSecCore/Ia32/ResetVec.asm16 +++ /dev/null @@ -1,103 +0,0 @@ -;------------------------------------------------------------------------------ -; -; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR> -; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -; -; Abstract: -; -; Reset Vector Data structure -; This structure is located at 0xFFFFFFC0 -; -;------------------------------------------------------------------------------ - - .model tiny - .686p - .stack 0h - .code - -; -; The layout of this file is fixed. The build tool makes assumption of the layout. -; - - ORG 0h -; -; Reserved -; -ReservedData DD 0eeeeeeeeh, 0eeeeeeeeh - - ORG 10h -; -; This is located at 0xFFFFFFD0h -; - mov di, "AP" - jmp ApStartup - - ORG 20h -; -; Pointer to the entry point of the PEI core -; It is located at 0xFFFFFFE0, and is fixed up by some build tool -; So if the value 8..1 appears in the final FD image, tool failure occurs. -; -PeiCoreEntryPoint DD 12345678h - -; -; This is the handler for all kinds of exceptions. Since it's for debugging -; purpose only, nothing except a deadloop would be done here. Developers could -; analyze the cause of the exception if a debugger had been attached. -; -InterruptHandler PROC - jmp $ - iret -InterruptHandler ENDP - - ORG 30h -; -; For IA32, the reset vector must be at 0xFFFFFFF0, i.e., 4G-16 byte -; Execution starts here upon power-on/platform-reset. -; -ResetHandler: - nop - nop - -ApStartup: - ; - ; Jmp Rel16 instruction - ; Use machine code directly in case of the assembler optimization - ; SEC entry point relatvie address will be fixed up by some build tool. - ; - ; Typically, SEC entry point is the function _ModuleEntryPoint() defined in - ; SecEntry.asm - ; - DB 0e9h - DW -3 - - - ORG 38h -; -; Ap reset vector segment address is at 0xFFFFFFF8 -; This will be fixed up by some build tool, -; so if the value 1..8 appears in the final FD image, -; tool failure occurs -; -ApSegAddress dd 12345678h - - ORG 3ch -; -; BFV Base is at 0xFFFFFFFC -; This will be fixed up by some build tool, -; so if the value 1..8 appears in the final FD image, -; tool failure occurs. -; -BfvBase DD 12345678h - -; -; Nothing can go here, otherwise the layout of this file would change. -; - - END diff --git a/IntelFspPkg/FspSecCore/Ia32/SaveRestoreSse.inc b/IntelFspPkg/FspSecCore/Ia32/SaveRestoreSse.inc deleted file mode 100644 index afc3ce0..0000000 --- a/IntelFspPkg/FspSecCore/Ia32/SaveRestoreSse.inc +++ /dev/null @@ -1,184 +0,0 @@ -;------------------------------------------------------------------------------ -; -; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR> -; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -; -; Abstract: -; -; Provide macro for register save/restore using SSE registers -; -;------------------------------------------------------------------------------ - -; -; Define SSE instruction set -; -IFDEF USE_SSE41_FLAG -; -; Define SSE macros using SSE 4.1 instructions -; -SXMMN MACRO XMM, IDX, REG - pinsrd XMM, REG, (IDX AND 3) - ENDM - -LXMMN MACRO XMM, REG, IDX - pextrd REG, XMM, (IDX AND 3) - ENDM -ELSE -; -; Define SSE macros using SSE 2 instructions -; -SXMMN MACRO XMM, IDX, REG - pinsrw XMM, REG, (IDX AND 3) * 2 - ror REG, 16 - pinsrw XMM, REG, (IDX AND 3) * 2 + 1 - rol REG, 16 - ENDM - -LXMMN MACRO XMM, REG, IDX - pshufd XMM, XMM, (0E4E4E4h SHR (IDX * 2)) AND 0FFh - movd REG, XMM - pshufd XMM, XMM, (0E4E4E4h SHR (IDX * 2 + (IDX AND 1) * 4)) AND 0FFh - ENDM -ENDIF - -; -; XMM7 to save/restore EBP, EBX, ESI, EDI -; -SAVE_REGS MACRO - SXMMN xmm7, 0, ebp - SXMMN xmm7, 1, ebx - SXMMN xmm7, 2, esi - SXMMN xmm7, 3, edi - SAVE_ESP - ENDM - -LOAD_REGS MACRO - LXMMN xmm7, ebp, 0 - LXMMN xmm7, ebx, 1 - LXMMN xmm7, esi, 2 - LXMMN xmm7, edi, 3 - LOAD_ESP - ENDM - -; -; XMM6 to save/restore EAX, EDX, ECX, ESP -; -LOAD_EAX MACRO - LXMMN xmm6, eax, 1 - ENDM - -SAVE_EAX MACRO - SXMMN xmm6, 1, eax - ENDM - -LOAD_EDX MACRO - LXMMN xmm6, edx, 2 - ENDM - -SAVE_EDX MACRO - SXMMN xmm6, 2, edx - ENDM - -SAVE_ECX MACRO - SXMMN xmm6, 3, ecx - ENDM - -LOAD_ECX MACRO - LXMMN xmm6, ecx, 3 - ENDM - -SAVE_ESP MACRO - SXMMN xmm6, 0, esp - ENDM - -LOAD_ESP MACRO - movd esp, xmm6 - ENDM - -; -; XMM5 for calling stack -; -CALL_XMM MACRO Entry - local ReturnAddress - mov esi, offset ReturnAddress - pslldq xmm5, 4 -IFDEF USE_SSE41_FLAG - pinsrd xmm5, esi, 0 -ELSE - pinsrw xmm5, esi, 0 - ror esi, 16 - pinsrw xmm5, esi, 1 -ENDIF - mov esi, Entry - jmp esi -ReturnAddress: - ENDM - -RET_XMM MACRO - movd esi, xmm5 - psrldq xmm5, 4 - jmp esi - ENDM - -ENABLE_SSE MACRO - ; - ; Initialize floating point units - ; - local NextAddress - jmp NextAddress -ALIGN 4 - ; - ; Float control word initial value: - ; all exceptions masked, double-precision, round-to-nearest - ; -FpuControlWord DW 027Fh - ; - ; Multimedia-extensions control word: - ; all exceptions masked, round-to-nearest, flush to zero for masked underflow - ; -MmxControlWord DD 01F80h -SseError: - ; - ; Processor has to support SSE - ; - jmp SseError -NextAddress: - finit - fldcw FpuControlWord - - ; - ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test - ; whether the processor supports SSE instruction. - ; - mov eax, 1 - cpuid - bt edx, 25 - jnc SseError - -IFDEF USE_SSE41_FLAG - ; - ; SSE 4.1 support - ; - bt ecx, 19 - jnc SseError -ENDIF - - ; - ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10) - ; - mov eax, cr4 - or eax, 00000600h - mov cr4, eax - - ; - ; The processor should support SSE instruction and we can use - ; ldmxcsr instruction - ; - ldmxcsr MmxControlWord - ENDM diff --git a/IntelFspPkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFspPkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc new file mode 100644 index 0000000..ae0a93d --- /dev/null +++ b/IntelFspPkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -0,0 +1,187 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +; Abstract: +; +; Provide macro for register save/restore using SSE registers +; +;------------------------------------------------------------------------------ + +; +; Define SSE instruction set +; +%ifdef USE_SSE41_FLAG +; +; Define SSE macros using SSE 4.1 instructions +; args 1:XMM, 2:IDX, 3:REG +%macro SXMMN 3 + pinsrd %1, %3, (%2 & 3) + %endmacro + +; +;args 1:XMM, 2:REG, 3:IDX +; +%macro LXMMN 3 + pextrd %2, %1, (%3 & 3) + %endmacro +%else +; +; Define SSE macros using SSE 2 instructions +; args 1:XMM, 2:IDX, 3:REG +%macro SXMMN 3 + pinsrw %1, %3, (%2 & 3) * 2 + ror %3, 16 + pinsrw %1, %3, (%2 & 3) * 2 + 1 + rol %3, 16 + %endmacro + +; +;args 1:XMM, 2:REG, 3:IDX +; +%macro LXMMN 3 + pshufd %1, %1, ((0E4E4E4h >> (%3 * 2)) & 0FFh) + movd %2, %1 + pshufd %1, %1, ((0E4E4E4h >> (%3 * 2 + (%3 & 1) * 4)) & 0FFh) + %endmacro +%endif + +; +; XMM7 to save/restore EBP, EBX, ESI, EDI +; +%macro SAVE_REGS 0 + SXMMN xmm7, 0, ebp + SXMMN xmm7, 1, ebx + SXMMN xmm7, 2, esi + SXMMN xmm7, 3, edi + SAVE_ESP + %endmacro + +%macro LOAD_REGS 0 + LXMMN xmm7, ebp, 0 + LXMMN xmm7, ebx, 1 + LXMMN xmm7, esi, 2 + LXMMN xmm7, edi, 3 + LOAD_ESP + %endmacro + +; +; XMM6 to save/restore EAX, EDX, ECX, ESP +; +%macro LOAD_EAX 0 + LXMMN xmm6, eax, 1 + %endmacro + +%macro SAVE_EAX 0 + SXMMN xmm6, 1, eax + %endmacro + +%macro LOAD_EDX 0 + LXMMN xmm6, edx, 2 + %endmacro + +%macro SAVE_EDX 0 + SXMMN xmm6, 2, edx + %endmacro + +%macro SAVE_ECX 0 + SXMMN xmm6, 3, ecx + %endmacro + +%macro LOAD_ECX 0 + LXMMN xmm6, ecx, 3 + %endmacro + +%macro SAVE_ESP 0 + SXMMN xmm6, 0, esp + %endmacro + +%macro LOAD_ESP 0 + movd esp, xmm6 + %endmacro +; +; XMM5 for calling stack +; arg 1:Entry +%macro CALL_XMM 1 + mov esi, %%ReturnAddress + pslldq xmm5, 4 +%ifdef USE_SSE41_FLAG + pinsrd xmm5, esi, 0 +%else + pinsrw xmm5, esi, 0 + ror esi, 16 + pinsrw xmm5, esi, 1 +%endif + mov esi, %1 + jmp esi +%%ReturnAddress: + %endmacro + +%macro RET_XMM 0 + movd esi, xmm5 + psrldq xmm5, 4 + jmp esi + %endmacro + +%macro ENABLE_SSE 0 + ; + ; Initialize floating point units + ; + jmp NextAddress +align 4 + ; + ; Float control word initial value: + ; all exceptions masked, double-precision, round-to-nearest + ; +FpuControlWord DW 027Fh + ; + ; Multimedia-extensions control word: + ; all exceptions masked, round-to-nearest, flush to zero for masked underflow + ; +MmxControlWord DD 01F80h +SseError: + ; + ; Processor has to support SSE + ; + jmp SseError +NextAddress: + finit + fldcw [FpuControlWord] + + ; + ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test + ; whether the processor supports SSE instruction. + ; + mov eax, 1 + cpuid + bt edx, 25 + jnc SseError + +%ifdef USE_SSE41_FLAG + ; + ; SSE 4.1 support + ; + bt ecx, 19 + jnc SseError +%endif + + ; + ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10) + ; + mov eax, cr4 + or eax, 00000600h + mov cr4, eax + + ; + ; The processor should support SSE instruction and we can use + ; ldmxcsr instruction + ; + ldmxcsr [MmxControlWord] + %endmacro diff --git a/IntelFspPkg/FspSecCore/Ia32/Stack.asm b/IntelFspPkg/FspSecCore/Ia32/Stack.asm deleted file mode 100644 index f96a55f..0000000 --- a/IntelFspPkg/FspSecCore/Ia32/Stack.asm +++ /dev/null @@ -1,82 +0,0 @@ -;------------------------------------------------------------------------------ -; -; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR> -; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -; -; Abstract: -; -; Switch the stack from temporary memory to permenent memory. -; -;------------------------------------------------------------------------------ - - .586p - .model flat,C - .code - -;------------------------------------------------------------------------------ -; VOID -; EFIAPI -; SecSwitchStack ( -; UINT32 TemporaryMemoryBase, -; UINT32 PermenentMemoryBase -; ); -;------------------------------------------------------------------------------ -SecSwitchStack PROC - ; - ; Save three register: eax, ebx, ecx - ; - push eax - push ebx - push ecx - push edx - - ; - ; !!CAUTION!! this function address's is pushed into stack after - ; migration of whole temporary memory, so need save it to permenent - ; memory at first! - ; - - mov ebx, [esp + 20] ; Save the first parameter - mov ecx, [esp + 24] ; Save the second parameter - - ; - ; Save this function's return address into permenent memory at first. - ; Then, Fixup the esp point to permenent memory - ; - mov eax, esp - sub eax, ebx - add eax, ecx - mov edx, dword ptr [esp] ; copy pushed register's value to permenent memory - mov dword ptr [eax], edx - mov edx, dword ptr [esp + 4] - mov dword ptr [eax + 4], edx - mov edx, dword ptr [esp + 8] - mov dword ptr [eax + 8], edx - mov edx, dword ptr [esp + 12] - mov dword ptr [eax + 12], edx - mov edx, dword ptr [esp + 16] ; Update this function's return address into permenent memory - mov dword ptr [eax + 16], edx - mov esp, eax ; From now, esp is pointed to permenent memory - - ; - ; Fixup the ebp point to permenent memory - ; - mov eax, ebp - sub eax, ebx - add eax, ecx - mov ebp, eax ; From now, ebp is pointed to permenent memory - - pop edx - pop ecx - pop ebx - pop eax - ret -SecSwitchStack ENDP - - END diff --git a/IntelFspPkg/FspSecCore/Ia32/Stack.nasm b/IntelFspPkg/FspSecCore/Ia32/Stack.nasm new file mode 100644 index 0000000..338e700 --- /dev/null +++ b/IntelFspPkg/FspSecCore/Ia32/Stack.nasm @@ -0,0 +1,78 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +; Abstract: +; +; Switch the stack from temporary memory to permanent memory. +; +;------------------------------------------------------------------------------ + +SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; SecSwitchStack ( +; UINT32 TemporaryMemoryBase, +; UINT32 PermenentMemoryBase +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(SecSwitchStack) +ASM_PFX(SecSwitchStack): + ; + ; Save three register: eax, ebx, ecx + ; + push eax + push ebx + push ecx + push edx + + ; + ; !!CAUTION!! this function address's is pushed into stack after + ; migration of whole temporary memory, so need save it to permanent + ; memory at first! + ; + + mov ebx, [esp + 20] ; Save the first parameter + mov ecx, [esp + 24] ; Save the second parameter + + ; + ; Save this function's return address into permanent memory at first. + ; Then, Fixup the esp point to permanent memory + ; + mov eax, esp + sub eax, ebx + add eax, ecx + mov edx, dword [esp] ; copy pushed register's value to permanent memory + mov dword [eax], edx + mov edx, dword [esp + 4] + mov dword [eax + 4], edx + mov edx, dword [esp + 8] + mov dword [eax + 8], edx + mov edx, dword [esp + 12] + mov dword [eax + 12], edx + mov edx, dword [esp + 16] ; Update this function's return address into permanent memory + mov dword [eax + 16], edx + mov esp, eax ; From now, esp is pointed to permanent memory + + ; + ; Fixup the ebp point to permenent memory + ; + mov eax, ebp + sub eax, ebx + add eax, ecx + mov ebp, eax ; From now, ebp is pointed to permanent memory + + pop edx + pop ecx + pop ebx + pop eax + ret diff --git a/IntelFspPkg/FspSecCore/Ia32/Stacks.s b/IntelFspPkg/FspSecCore/Ia32/Stacks.s deleted file mode 100644 index 0ab214d..0000000 --- a/IntelFspPkg/FspSecCore/Ia32/Stacks.s +++ /dev/null @@ -1,86 +0,0 @@ -#------------------------------------------------------------------------------ -# -# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR> -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# Abstract: -# -# Switch the stack from temporary memory to permenent memory. -# -#------------------------------------------------------------------------------ - -ASM_GLOBAL ASM_PFX(SecSwitchStack) - -#------------------------------------------------------------------------------ -# VOID -# EFIAPI -# SecSwitchStack ( -# UINT32 TemporaryMemoryBase, -# UINT32 PermenentMemoryBase -# ) -#------------------------------------------------------------------------------ -ASM_GLOBAL ASM_PFX(SecSwitchStack) -ASM_PFX(SecSwitchStack): -# -# Save four registers: eax, ebx, ecx, edx -# - pushl %eax - pushl %ebx - pushl %ecx - pushl %edx - -# -# !!CAUTION!! this function address's is pushed into stack after -# migration of whole temporary memory, so need save it to permenent -# memory at first! -# - - movl 20(%esp), %ebx # Save the first parameter - movl 24(%esp), %ecx # Save the second parameter - -# -# Save this function's return address into permenent memory at first. -# Then, Fixup the esp point to permenent memory -# - - movl %esp, %eax - subl %ebx, %eax - addl %ecx, %eax - movl (%esp), %edx # copy pushed register's value to permenent memory - movl %edx, (%eax) - movl 4(%esp), %edx - movl %edx, 4(%eax) - movl 8(%esp), %edx - movl %edx, 8(%eax) - movl 12(%esp), %edx - movl %edx, 12(%eax) - movl 16(%esp), %edx # Update this function's return address into permenent memory - movl %edx, 16(%eax) - movl %eax, %esp # From now, esp is pointed to permenent memory - -# -# Fixup the ebp point to permenent memory -# - movl %ebp, %eax - subl %ebx, %eax - addl %ecx, %eax - movl %eax, %ebp # From now, ebp is pointed to permenent memory - -# -# Fixup callee's ebp point for PeiDispatch -# -# movl %ebp, %eax -# subl %ebx, %eax -# addl %ecx, %eax -# movl %eax, %ebp # From now, ebp is pointed to permenent memory - popl %edx - popl %ecx - popl %ebx - popl %eax - ret \ No newline at end of file diff --git a/IntelFspPkg/FspSecCore/SecFsp.c b/IntelFspPkg/FspSecCore/SecFsp.c index 07aed1c..a7948b1 100644 --- a/IntelFspPkg/FspSecCore/SecFsp.c +++ b/IntelFspPkg/FspSecCore/SecFsp.c @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -94,7 +94,6 @@ SecGetPlatformData ( // The entries of platform information, together with the number of them, // reside in the bottom of stack, left untouched by normal stack operation. // - TopOfCar = PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamSize); FspPlatformData->DataPtr = NULL; FspPlatformData->MicrocodeRegionBase = 0; @@ -105,29 +104,34 @@ SecGetPlatformData ( // // Pointer to the size field // - StackPtr = (UINT32 *)(TopOfCar - sizeof(UINT32)); - - while (*StackPtr != 0) { - if (*(StackPtr - 1) == FSP_MCUD_SIGNATURE) { - // - // This following data was pushed onto stack after TempRamInit API - // - DwordSize = 4; - StackPtr = StackPtr - 1 - DwordSize; - CopyMem (&(FspPlatformData->MicrocodeRegionBase), StackPtr, (DwordSize << 2)); - StackPtr--; - } else if (*(StackPtr - 1) == FSP_PER0_SIGNATURE) { - // - // This is the performance data for InitTempMemory API entry/exit - // - DwordSize = 4; - StackPtr = StackPtr - 1 - DwordSize; - CopyMem (FspData->PerfData, StackPtr, (DwordSize << 2)); - ((UINT8 *)(&FspData->PerfData[0]))[7] = FSP_PERF_ID_API_TMPRAMINIT_ENTRY; - ((UINT8 *)(&FspData->PerfData[1]))[7] = FSP_PERF_ID_API_TMPRAMINIT_EXIT; - StackPtr--; - } else { - StackPtr -= (*StackPtr); + TopOfCar = FspPlatformData->CarBase + FspPlatformData->CarSize; + StackPtr = (UINT32 *)(TopOfCar - sizeof (UINT32)); + + if (*(StackPtr - 1) == FSP_MCUD_SIGNATURE) { + while (*StackPtr != 0) { + if (*(StackPtr - 1) == FSP_MCUD_SIGNATURE) { + // + // This following data was pushed onto stack after TempRamInit API + // + DwordSize = 4; + StackPtr = StackPtr - 1 - DwordSize; + CopyMem (&(FspPlatformData->MicrocodeRegionBase), StackPtr, (DwordSize << 2)); + StackPtr--; + } else if (*(StackPtr - 1) == FSP_PER0_SIGNATURE) { + // + // This is the performance data for InitTempMemory API entry/exit + // + DwordSize = 4; + StackPtr = StackPtr - 1 - DwordSize; + CopyMem (FspData->PerfData, StackPtr, (DwordSize << 2)); + + ((UINT8 *)(&FspData->PerfData[0]))[7] = FSP_PERF_ID_API_TEMPRAMINIT_ENTRY; + ((UINT8 *)(&FspData->PerfData[1]))[7] = FSP_PERF_ID_API_TEMPRAMINIT_EXIT; + + StackPtr--; + } else { + StackPtr -= (*StackPtr); + } } } } @@ -149,8 +153,7 @@ FspGlobalDataInit ( IN UINT8 ApiIdx ) { - VOID *UpdDataRgnPtr; - FSP_INIT_PARAMS *FspInitParams; + VOID *FspmUpdDataPtr; CHAR8 ImageId[9]; UINTN Idx; @@ -161,9 +164,13 @@ FspGlobalDataInit ( SetFspGlobalDataPointer (PeiFspData); ZeroMem ((VOID *)PeiFspData, sizeof(FSP_GLOBAL_DATA)); - PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE; - PeiFspData->CoreStack = BootLoaderStack; - PeiFspData->PerfIdx = 2; + PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE; + PeiFspData->Version = 0; + PeiFspData->CoreStack = BootLoaderStack; + PeiFspData->PerfIdx = 2; + PeiFspData->PerfSig = FSP_PERFORMANCE_DATA_SIGNATURE; + PeiFspData->PlatformData.CarBase = AsmReadMsr32 (0x200) & ~(0x6); + PeiFspData->PlatformData.CarSize = ~(AsmReadMsr32(0x201) & ~(0x800)) + 1; SetFspMeasurePoint (FSP_PERF_ID_API_FSPINIT_ENTRY); @@ -174,20 +181,11 @@ FspGlobalDataInit ( PeiFspData->FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader(); SecGetPlatformData (PeiFspData); - // - // Set API calling mode - // - SetFspApiCallingMode (ApiIdx == 1 ? 0 : 1); - - // - // Initialize UPD pointer. - // - FspInitParams = (FSP_INIT_PARAMS *)GetFspApiParameter (); - UpdDataRgnPtr = ((FSP_INIT_RT_COMMON_BUFFER *)FspInitParams->RtBufferPtr)->UpdDataRgnPtr; - if (UpdDataRgnPtr == NULL) { - UpdDataRgnPtr = (VOID *)(PeiFspData->FspInfoHeader->ImageBase + GetFspUpdRegionOffset()); + FspmUpdDataPtr = (VOID *) GetFspApiParameter (); + if (FspmUpdDataPtr == NULL) { + FspmUpdDataPtr = (VOID *)(PeiFspData->FspInfoHeader->ImageBase + GetFspUpdRegionOffset()); } - SetFspUpdDataPointer (UpdDataRgnPtr); + SetFspUpdDataPointer (FspmUpdDataPtr); // // Initialize serial port @@ -207,14 +205,15 @@ FspGlobalDataInit ( } ImageId[Idx] = 0; - DEBUG ((DEBUG_INFO | DEBUG_INIT, "\n============= PEIM FSP v1.%x (%a v%x.%x.%x.%x) =============\n", \ - PeiFspData->FspInfoHeader->HeaderRevision - 1, \ + DEBUG ((DEBUG_INFO | DEBUG_INIT, "\n============= FSP Spec v%d.%d Header Revision v%x (%a v%x.%x.%x.%x) =============\n", \ + (PeiFspData->FspInfoHeader->SpecVersion >> 4) & 0xF, \ + PeiFspData->FspInfoHeader->SpecVersion & 0xF, \ + PeiFspData->FspInfoHeader->HeaderRevision, \ ImageId, \ - (PeiFspData->FspInfoHeader->ImageRevision >> 24) & 0xff, \ - (PeiFspData->FspInfoHeader->ImageRevision >> 16) & 0xff, \ - (PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xff, \ - (PeiFspData->FspInfoHeader->ImageRevision >> 0) & 0xff)); - + (PeiFspData->FspInfoHeader->ImageRevision >> 24) & 0xFF, \ + (PeiFspData->FspInfoHeader->ImageRevision >> 16) & 0xFF, \ + (PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xFF, \ + PeiFspData->FspInfoHeader->ImageRevision & 0xFF)); } /** @@ -234,101 +233,3 @@ FspDataPointerFixUp ( NewFspData = (FSP_GLOBAL_DATA *)((UINTN)GetFspGlobalDataPointer() + (UINTN)OffsetGap); SetFspGlobalDataPointer (NewFspData); } - -/** - This function check the FSP API calling condition. - - @param[in] ApiIdx Internal index of the FSP API. - @param[in] ApiParam Parameter of the FSP API. - -**/ -EFI_STATUS -EFIAPI -FspApiCallingCheck ( - IN UINT32 ApiIdx, - IN VOID *ApiParam - ) -{ - EFI_STATUS Status; - FSP_GLOBAL_DATA *FspData; - FSP_INIT_PARAMS *FspInitParams; - FSP_INIT_RT_COMMON_BUFFER *FspRtBuffer; - - FspInitParams = (FSP_INIT_PARAMS *) ApiParam; - FspRtBuffer = ((FSP_INIT_RT_COMMON_BUFFER *)FspInitParams->RtBufferPtr); - - Status = EFI_SUCCESS; - FspData = GetFspGlobalDataPointer (); - if (ApiIdx == 1) { - // - // FspInit check - // - if ((UINT32)FspData != 0xFFFFFFFF) { - Status = EFI_UNSUPPORTED; - } else if ((FspRtBuffer == NULL) || ((FspRtBuffer->BootLoaderTolumSize % EFI_PAGE_SIZE) != 0) || (EFI_ERROR(FspUpdSignatureCheck(ApiIdx, ApiParam)))) { - Status = EFI_INVALID_PARAMETER; - } - } else if (ApiIdx == 2) { - // - // NotifyPhase check - // - if ((FspData == NULL) || ((UINT32)FspData == 0xFFFFFFFF)) { - Status = EFI_UNSUPPORTED; - } else { - if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) { - Status = EFI_UNSUPPORTED; - } - } - } else if (ApiIdx == 3) { - // - // FspMemoryInit check - // - if ((UINT32)FspData != 0xFFFFFFFF) { - Status = EFI_UNSUPPORTED; - } else if ((FspRtBuffer == NULL) || ((FspRtBuffer->BootLoaderTolumSize % EFI_PAGE_SIZE) != 0) || (EFI_ERROR(FspUpdSignatureCheck(ApiIdx, ApiParam)))) { - Status = EFI_INVALID_PARAMETER; - } - } else if (ApiIdx == 4) { - // - // TempRamExit check - // - if ((FspData == NULL) || ((UINT32)FspData == 0xFFFFFFFF)) { - Status = EFI_UNSUPPORTED; - } else { - if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) { - Status = EFI_UNSUPPORTED; - } - } - } else if (ApiIdx == 5) { - // - // FspSiliconInit check - // - if ((FspData == NULL) || ((UINT32)FspData == 0xFFFFFFFF)) { - Status = EFI_UNSUPPORTED; - } else { - if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) { - Status = EFI_UNSUPPORTED; - } else if (EFI_ERROR(FspUpdSignatureCheck(ApiIdx, ApiParam))) { - Status = EFI_INVALID_PARAMETER; - } - } - } else { - Status = EFI_UNSUPPORTED; - } - - return Status; -} - -/** - This function gets the boot FV offset in FSP. - @return the boot firmware volumen offset inside FSP binary - -**/ -UINT32 -EFIAPI -GetBootFirmwareVolumeOffset ( - VOID - ) -{ - return PcdGet32 (PcdFspBootFirmwareVolumeBase) - PcdGet32 (PcdFspAreaBaseAddress); -} diff --git a/IntelFspPkg/FspSecCore/SecFsp.h b/IntelFspPkg/FspSecCore/SecFsp.h index 4dceebc..c4198d0 100644 --- a/IntelFspPkg/FspSecCore/SecFsp.h +++ b/IntelFspPkg/FspSecCore/SecFsp.h @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -12,7 +12,7 @@ **/ #ifndef _SEC_FSP_H_ -#define _SEC_FSPE_H_ +#define _SEC_FSP_H_ #include <PiPei.h> #include <FspApi.h> diff --git a/IntelFspPkg/FspSecCore/SecFspApiChk.c b/IntelFspPkg/FspSecCore/SecFspApiChk.c new file mode 100644 index 0000000..bace5ec --- /dev/null +++ b/IntelFspPkg/FspSecCore/SecFspApiChk.c @@ -0,0 +1,97 @@ +/** @file + + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "SecFsp.h" + + +/** + This function check the FSP API calling condition. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + +**/ +EFI_STATUS +EFIAPI +FspApiCallingCheck ( + IN UINT8 ApiIdx, + IN VOID *ApiParam + ) +{ + EFI_STATUS Status; + FSP_GLOBAL_DATA *FspData; + + Status = EFI_SUCCESS; + FspData = GetFspGlobalDataPointer (); + + if (ApiIdx == NotifyPhaseApiIndex) { + // + // NotifyPhase check + // + if ((FspData == NULL) || ((UINT32)FspData == 0xFFFFFFFF)) { + Status = EFI_UNSUPPORTED; + } else { + if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) { + Status = EFI_UNSUPPORTED; + } + } + } else if (ApiIdx == FspMemoryInitApiIndex) { + // + // FspMemoryInit check + // + if ((UINT32)FspData != 0xFFFFFFFF) { + Status = EFI_UNSUPPORTED; + } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) { + Status = EFI_INVALID_PARAMETER; + } + } else if (ApiIdx == TempRamExitApiIndex) { + // + // TempRamExit check + // + if ((FspData == NULL) || ((UINT32)FspData == 0xFFFFFFFF)) { + Status = EFI_UNSUPPORTED; + } else { + if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) { + Status = EFI_UNSUPPORTED; + } + } + } else if (ApiIdx == FspSiliconInitApiIndex) { + // + // FspSiliconInit check + // + if ((FspData == NULL) || ((UINT32)FspData == 0xFFFFFFFF)) { + Status = EFI_UNSUPPORTED; + } else { + if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) { + Status = EFI_UNSUPPORTED; + } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) { + Status = EFI_INVALID_PARAMETER; + } + } + } else { + Status = EFI_UNSUPPORTED; + } + + if (!EFI_ERROR (Status)) { + if ((ApiIdx != FspMemoryInitApiIndex)) { + // + // For FspMemoryInit, the global data is not valid yet + // The API index will be updated by SecCore after the global data + // is initialized + // + SetFspApiCallingIndex (ApiIdx); + } + } + + return Status; +} diff --git a/IntelFspPkg/FspSecCore/SecMain.c b/IntelFspPkg/FspSecCore/SecMain.c index 99acefa..40e0a01 100644 --- a/IntelFspPkg/FspSecCore/SecMain.c +++ b/IntelFspPkg/FspSecCore/SecMain.c @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -65,6 +65,7 @@ SecStartup ( UINT32 Index; FSP_GLOBAL_DATA PeiFspData; UINT64 ExceptionHandler; + FSPM_UPD_COMMON *FspmUpdCommon; // // Process all libraries constructor function linked to SecCore. @@ -111,15 +112,30 @@ SecStartup ( // // Update the base address and length of Pei temporary memory // + FspmUpdCommon = (FSPM_UPD_COMMON *) GetFspApiParameter (); SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF); SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume; SecCoreData.BootFirmwareVolumeSize = (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *)BootFirmwareVolume)->FvLength; - SecCoreData.TemporaryRamBase = (VOID*)(UINTN) TempRamBase; - SecCoreData.TemporaryRamSize = SizeOfRam; + + SecCoreData.TemporaryRamBase = FspmUpdCommon->FspmArchUpd.StackBase; + SecCoreData.TemporaryRamSize = FspmUpdCommon->FspmArchUpd.StackSize; + if (SecCoreData.TemporaryRamBase == NULL) { + SecCoreData.TemporaryRamBase = (VOID*)(UINTN) TempRamBase; + SecCoreData.TemporaryRamSize = SizeOfRam; + } SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase; - SecCoreData.PeiTemporaryRamSize = SizeOfRam >> 1; - SecCoreData.StackBase = (VOID*)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize); - SecCoreData.StackSize = SizeOfRam >> 1; + SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize * PcdGet8 (PcdFspHeapSizePercentage) / 100; + SecCoreData.StackBase = (VOID*)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize); + SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize; + + DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeBase - 0x%x\n", SecCoreData.BootFirmwareVolumeBase)); + DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeSize - 0x%x\n", SecCoreData.BootFirmwareVolumeSize)); + DEBUG ((DEBUG_INFO, "Fsp TemporaryRamBase - 0x%x\n", SecCoreData.TemporaryRamBase)); + DEBUG ((DEBUG_INFO, "Fsp TemporaryRamSize - 0x%x\n", SecCoreData.TemporaryRamSize)); + DEBUG ((DEBUG_INFO, "Fsp PeiTemporaryRamBase - 0x%x\n", SecCoreData.PeiTemporaryRamBase)); + DEBUG ((DEBUG_INFO, "Fsp PeiTemporaryRamSize - 0x%x\n", SecCoreData.PeiTemporaryRamSize)); + DEBUG ((DEBUG_INFO, "Fsp StackBase - 0x%x\n", SecCoreData.StackBase)); + DEBUG ((DEBUG_INFO, "Fsp StackSize - 0x%x\n", SecCoreData.StackSize)); // // Call PeiCore Entry @@ -162,22 +178,27 @@ SecTemporaryRamSupport ( VOID* NewHeap; VOID* OldStack; VOID* NewStack; + UINTN HeapSize; + UINTN StackSize; + HeapSize = CopySize * PcdGet8 (PcdFspHeapSizePercentage) / 100 ; + StackSize = CopySize - HeapSize; + OldHeap = (VOID*)(UINTN)TemporaryMemoryBase; - NewHeap = (VOID*)((UINTN)PermanentMemoryBase + CopySize / 2); + NewHeap = (VOID*)((UINTN)PermanentMemoryBase + StackSize); - OldStack = (VOID*)((UINTN)TemporaryMemoryBase + CopySize / 2); + OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize); NewStack = (VOID*)(UINTN)PermanentMemoryBase; // // Migrate Heap // - CopyMem (NewHeap, OldHeap, CopySize / 2); + CopyMem (NewHeap, OldHeap, HeapSize); // // Migrate Stack // - CopyMem (NewStack, OldStack, CopySize / 2); + CopyMem (NewStack, OldStack, StackSize); // -- 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
