On 22 June 2018 at 14:58, gary guo wrote:
> Sure. A little busy these days; I'll do that ASAP.
>
No worries.
BTW I noticed that we still have a problem with option ROMs when using
the new MMIO translation code. Did you look into that at all?
> On Thu, Jun 07, 2018 at 01:11:59PM +0200, Ard
Sure. A little busy these days; I'll do that ASAP.
Thanks,
Heyi
On Thu, Jun 07, 2018 at 01:11:59PM +0200, Ard Biesheuvel wrote:
> On 17 April 2018 at 03:20, Guo Heyi wrote:
> > Hi Ard,
> >
> > I tested mm -io on D05, for root bridge 4 with CPU IO address starting from
> > 0x8_abff, and it
On 17 April 2018 at 03:20, Guo Heyi wrote:
> Hi Ard,
>
> I tested mm -io on D05, for root bridge 4 with CPU IO address starting from
> 0x8_abff, and it worked; both mm -io 0x8abff and mm 0x8abff
> provided
> the same output. It seems there is no other limit for 64bit IO address after
Hi Ard,
Have you returned from vocation? If so, could you help to continue reviewing
this patch series?
Thanks,
Heyi
On Tue, Apr 17, 2018 at 09:44:46AM +0800, Guo Heyi wrote:
> BTW, there is actually a bug with ATU configuration which will cause IO access
> failure, and we need to apply an
BTW, there is actually a bug with ATU configuration which will cause IO access
failure, and we need to apply an additional patch (this patch is generated after
PCI host bridge patch series) as attached to fix this.
Regards,
Heyi
On Tue, Apr 17, 2018 at 09:20:44AM +0800, Guo Heyi wrote:
> Hi Ard,
Hi Ard,
I tested mm -io on D05, for root bridge 4 with CPU IO address starting from
0x8_abff, and it worked; both mm -io 0x8abff and mm 0x8abff provided
the same output. It seems there is no other limit for 64bit IO address after you
fixed the issue in EFI shell mm command.
Thanks
Thanks, I will test mm command and let you know the result.
Regards,
Heyi
On Fri, Apr 13, 2018 at 09:19:53AM +0200, Ard Biesheuvel wrote:
> On 13 April 2018 at 04:05, Guo Heyi wrote:
> > Hi Ard,
> >
> > Any comments?
> >
>
> Apologies for the delay. I have been travelling
On 13 April 2018 at 04:05, Guo Heyi wrote:
> Hi Ard,
>
> Any comments?
>
Apologies for the delay. I have been travelling and am behind on email.
> Anyway we can modify the code if you insist on using an intermediate CPU IO
> address space.
>
I have not made up my mind yet,
Hi Ard,
Any comments?
Anyway we can modify the code if you insist on using an intermediate CPU IO
address space.
Thanks,
Heyi
On Sat, Mar 31, 2018 at 09:37:47AM +0800, Guo Heyi wrote:
> Hi Ard,
>
> Thanks for your time of reviewing the patches.
> Please see my opinions below.
>
> On Fri,
Hi Ard,
Thanks for your time of reviewing the patches.
Please see my opinions below.
On Fri, Mar 30, 2018 at 05:40:20PM +0200, Ard Biesheuvel wrote:
> On 29 March 2018 at 02:20, Guo Heyi wrote:
> > On Wed, Mar 28, 2018 at 10:43:41AM +0100, Ard Biesheuvel wrote:
> >> On 28
On 29 March 2018 at 02:20, Guo Heyi wrote:
> On Wed, Mar 28, 2018 at 10:43:41AM +0100, Ard Biesheuvel wrote:
>> On 28 March 2018 at 02:05, Guo Heyi wrote:
>> > Hi Leif, Ard,
>> >
>> > Any comments for this series of patches?
>> >
>>
>> Hello Heyi,
>>
>>
On Wed, Mar 28, 2018 at 10:43:41AM +0100, Ard Biesheuvel wrote:
> On 28 March 2018 at 02:05, Guo Heyi wrote:
> > Hi Leif, Ard,
> >
> > Any comments for this series of patches?
> >
>
> Hello Heyi,
>
> Thanks for sending these patches. Leif is at the plugfest, but I will
>
On 28 March 2018 at 02:05, Guo Heyi wrote:
> Hi Leif, Ard,
>
> Any comments for this series of patches?
>
Hello Heyi,
Thanks for sending these patches. Leif is at the plugfest, but I will
look at these before the end of the week.
Hi Leif, Ard,
Any comments for this series of patches?
Thanks,
Heyi
On Wed, Mar 21, 2018 at 09:03:06AM +0800, Heyi Guo wrote:
> For BAR address translation support was added to edk2 generic PciHostBridge by
> commit 74d0a33, now we can also use it for D03/D05 platforms.
> This series of patches
For BAR address translation support was added to edk2 generic PciHostBridge by
commit 74d0a33, now we can also use it for D03/D05 platforms.
This series of patches include 3 parts of change:
- Preparation for the switch, moving platform specific code out of PciHostBridge
driver.
- Add depending
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