Up until SVN r18540, GenFw created invalid PE/COFF binaries for the ARM architecture, by allowing PE/COFF .data sections to appear at offsets that were not aligned to the global PE/COFF section alignment. The reason for this was that the relocation metadata emitted by RVCT's armlink only contains dynamic absolute relocations, so it is impossible to recalculate relative relocations between .text and .data, and so the relative offset between the two needs to be preserved.
Since r18540, we do align .data to the PE/COFF section alignment, resulting in potentially corrupt PE/COFF binaries unless .data happens to appear at a 32-byte aligned offset. So let's introduce a RVCT scatter file that sets this alignment for the ELF .data section (and subsequent .bss section). At the same time, set the start offset to 0x220 bytes (which is the size of our 32-bit PE/COFF header) so that the memory layouts are identical between ELF and PE/COFF. Also add a 4 KB aligned version that can be used to build DXE_RUNTIME_DRIVER modules with runtime memory protection enabled. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org> Reviewed-by: Eugene Cohen <eug...@hp.com> Reviewed-by: Liming Gao <liming....@intel.com> --- BaseTools/Conf/tools_def.template | 2 +- BaseTools/Scripts/Rvct-Align32.sct | 25 ++++++++++++++++++++ BaseTools/Scripts/Rvct-Align4K.sct | 25 ++++++++++++++++++++ 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template index db08e252d2b9..4449ddf1b6ec 100644 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -6617,7 +6617,7 @@ RELEASE_XCODE5_X64_CC_FLAGS = -target x86_64-pc-win32-macho -c -Os -W DEFINE RVCT_ALL_ASM_FLAGS = --diag_suppress=1786 --diag_error=warning --apcs /interwork DEFINE RVCT_ALL_CC_FLAGS = --c90 -c --no_autoinline --asm --gnu --apcs /interwork --signed_chars --no_unaligned_access --split_sections --enum_is_int --preinclude AutoGen.h --diag_suppress=186 --diag_warning 167 --diag_error=warning --diag_style=ide --protect_stack -DEFINE RVCT_ALL_DLINK_FLAGS = --ro-base 0 --no_scanlib --reloc --no_exceptions --datacompressor off --strict --symbols --diag_style=ide --no_legacyalign +DEFINE RVCT_ALL_DLINK_FLAGS = --no_scanlib --no_exceptions --datacompressor off --strict --symbols --diag_style=ide --no_legacyalign --scatter $(EDK_TOOLS_PATH)/Scripts/Rvct-Align32.sct #################################################################################### # diff --git a/BaseTools/Scripts/Rvct-Align32.sct b/BaseTools/Scripts/Rvct-Align32.sct new file mode 100644 index 000000000000..4f29ad416b82 --- /dev/null +++ b/BaseTools/Scripts/Rvct-Align32.sct @@ -0,0 +1,25 @@ +/** @file + + Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR> + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +REGION 0x220 RELOC { + ER_RO +0 ALIGN 32 { + * (+RO) + } + ER_RW +0 ALIGN 32 { + * (+RW) + } + ER_ZI +0 { + * (+ZI) + } +} diff --git a/BaseTools/Scripts/Rvct-Align4K.sct b/BaseTools/Scripts/Rvct-Align4K.sct new file mode 100644 index 000000000000..83f5a0d5e4cd --- /dev/null +++ b/BaseTools/Scripts/Rvct-Align4K.sct @@ -0,0 +1,25 @@ +/** @file + + Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR> + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +REGION 0x1000 RELOC { + ER_RO +0 ALIGN 4096 { + * (+RO) + } + ER_RW +0 ALIGN 4096 { + * (+RW) + } + ER_ZI +0 { + * (+ZI) + } +} -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
