<brijesh.si...@amd.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 9
MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
in PEI to let VTd PEI
get the RMRR information.
This series patch resolves this problem.
We also updated sample driver to show how to get the RMRR information.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@
Let system report RMRR table for the platform support
PEI graphic.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInf
to skip the
RMRR region, and program the reset PCI VTd engine to skip
the another DMA buffer allocated in PEI phase for other
device driver.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
Int
bution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Include/Ppi/VtdInfo.h | 26 +++-
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/IntelSiliconPkg/Include/Ppi/VtdInfo.h
b/IntelSiliconPkg/Include/Ppi/VtdInfo.h
index e8be
In S3 resume, before system transfer to waking vector,
the VTdPrm need turn off VTd protection based upon VTdPolicy.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg
Clarify the VTdPolicy is for both PEI and DXE.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/IntelSiliconPkg.dec | 4 ++--
1 file changed, 2 insertions(+), 2 deleti
Make sure the context table are flush to memory.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c | 9 +++--
IntelSilico
r.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
Jiewen Yao (3):
IntelSiliconPkg/VTdDxe: Clean up DXE flush memory.
IntelSiliconPkg/dec: Clarify VTdPolicy.
IntelSiliconPkg/VTdPmrPei: Add EndOfPei callback for S3
Int
Move IntelVTdPmrPei to Feature/VTd/IntelVTdPmrPei.
Suggested-by: Star Zeng <star.z...@intel.com>
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Feature/
Move PlatformIntelVTdInfoSamplePei to Feature/VTd/.
Suggested-by: Star Zeng <star.z...@intel.com>
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Feature/VTd/Platfo
Move PlatformVTdSampleDxe to Feature/VTd/PlatformVTdSampleDxe.
Suggested-by: Star Zeng <star.z...@intel.com>
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSili
r: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen....@intel.com>
Jiewen Yao (4):
IntelSiliconPkg/IntelVTdDxe: Move to feature dir.
IntelSiliconPkg/PlatformVTdSampleDxe: Move to feature dir.
IntelSiliconPkg/IntelVTdPmrPei: Move to feature dir.
bution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/IntelSiliconPkg.dec | 6 ++
1 file changed, 6 insertions(+)
diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec
b/IntelSiliconPkg/IntelSiliconPkg.dec
index 663a232..2fc6379 100644
--- a/Int
Add PcdVTdPolicyPropertyMask
BIT0: This is to control if a platform wants to enable VTd
based protection during boot.
BIT1: This is to control if a platform wants to keep VTd
enabled at ExitBootService.
The default configuration is BIT0:1, BIT1:0.
Jiewen Yao (2):
IntelSiliconPkg/dec: Add VTd
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/IntelVTdDxe/DmaProtection.c | 7 +--
IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c | 4
IntelSiliconPkg
<star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmr.c | 314 ++
IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.c| 615
Int
This is a sample driver to produce VTD_INFO PPI.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
MdeModulePkg/MdeModulePkg.dec | 3 +++
1 file changed, 3 insertions(+)
diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModuleP
transfer in PEI phase,
2) We can still use XHCI in DXE phase, such as shell environment.
3) If the device driver does not consume IOMMU_PPI, the DMA fails.
Jiewen Yao (11):
MdeModulePkg/Include: Add IOMMU_PPI.
MdeModulePkg/Dec: Add IOMMU_PPI GUID.
IntelSiliconPkg/Vtd.h: Add definition for PMR
bution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c| 249
MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c | 55 +++--
MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h | 9 +-
MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c | 55 -
This IOMMU_PPI is to provide IOMMU abstraction in PEI.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
MdeModulePkg/Include/Ppi/IoMmu.h | 196
1 file changed, 19
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/IntelSiliconPkg.dsc | 9 +
1 file changed, 9 insertions(+)
diff --git a/IntelSiliconPkg/IntelSiliconPkg.dsc
b/Int
Add missing PMR definition in VTd spec.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Include/IndustryStandard/Vtd.h | 6 ++
1 file changed, 6 insertions(+)
When VTd translation is enabled, PMR can be disable.
Or the DMA will be blocked by PMR.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/IntelVTdDxe/V
ed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Include/Ppi/VtdInfo.h | 40
1 file changed, 40 insertions(+)
diff --git a/IntelSiliconPkg/Include/Ppi/VtdInfo.h
b/IntelSiliconPkg/Include/Ppi/VtdInfo.h
new file mode 100644
index 000..e8be63f
--- /de
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/IntelSiliconPkg.dec | 3 +++
1 file changed, 3 insertions(+)
diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec
b/Int
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/IntelSiliconPkg.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/IntelSiliconPkg/IntelSiliconPkg.dsc
b/Int
If IOMMU is enabled, the legacy BIOS need allow the legacy memory
access by the legacy device.
The legacy memory is below 1M memory and HighPmm memory.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@
This serial patch is to enable IOMMU support for CSM.
Jiewen Yao (2):
IntelSiliconPkg/Vtd: Support CSM usage.
IntelFramdworkModulePkg/LegacyBios: Add IoMmu Support.
IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf | 1 +
IntelFrameworkModulePkg/Csm/LegacyBiosDxe
eement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/IntelVTdDxe/BmDma.c| 8
IntelSiliconPkg/IntelVTdDxe/TranslationTable.c | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/IntelSiliconPkg/IntelVTdDxe/BmDma.c
b/Int
confusing.
3. Fix the debug message too long issue.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/IntelVTdDxe/DmaProtection.c | 143 -
IntelSiliconPkg
/DeviceId based reporting
Such as, VID:8086|DID:9D2F|Rev:21|SVID:8086|SDID:7270
Jiewen Yao (3):
IntelSiliconPkg/header: update PlatformVtdPolicy
IntelSiliconPkg/IntelVTd: update PlatformVtdPolicy
IntelSiliconPkg/PlatformVTdSample: update ExceptionDevice
IntelSiliconPkg/Include/Protocol
Add sample for device scope based exception list
and PCI vendor id based exception list.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVT
-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h | 51 +++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h
b/Int
Change ExitBootServices TPL to CALLBACK, so that a device
can disable BME before IOMMU grants access right.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Feature/VTd
Since the exception list is not a recommended way, we returns
EFI_UNSUPPORTED in the sample code.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Feature/VTd/Platform
Signed-off-by: Jiewen Yao <jiewen@intel.com>
Jiewen Yao (2):
IntelSiliconPkg/VtdPmrPei: Add premem support.
IntelSiliconPkg/VtdPeiSample: Add premem support.
IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c
| 580 ++
IntelSiliconPkg
and protect rest.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c| 580
++
IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/I
com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
| 234 +---
IntelSiliconPkg/Feature/VTd/PlatformVTdI
com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
| 234 +---
IntelSiliconPkg/Feature/VTd/PlatformVTdI
Fix a calculation problem in IGD RMRR memory.
Cc: Zeng Star <zeng.s...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
| 2 +-
1
by reinstalling VTD_INFO_PPI.
This patch is validated on one Intel Client kabylake platform.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
Jiewen Yao (2):
IntelSiliconPkg/VtdPmrPei: Add pr
and protect rest.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c| 580
++
IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/I
com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
| 234 +---
IntelSiliconPkg/Feature/VTd/PlatformVTdI
com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
| 234 +---
IntelSiliconPkg/Feature/VTd/PlatformVTdI
VTD_INFO_PPI.
This patch is validated on one Intel Client kabylake platform.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
Jiewen Yao (2):
IntelSiliconPkg/VtdPmrPei: Add premem support.
Int
and protect rest.
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c| 580
++
IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/I
AutoGen.c. Only Base.h is there. It should add Library/DebugLib.h.
Cc: Bob Feng
Cc: Liming Gao
Cc: Yonghong Zhu
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao
---
BaseTools/Source/Python/AutoGen/GenC.py | 56 ++--
1 file changed, 29 insertions
Contribution Agreement 1.1
Signed-off-by: Jiewen Yao
---
BaseTools/Source/Python/AutoGen/GenC.py | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/BaseTools/Source/Python/AutoGen/GenC.py
b/BaseTools/Source/Python/AutoGen/GenC.py
index 9700bf8527..c4bba8da17 100644
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521
Add information dump for Control Protection exception.
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen
---
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521
We scan the SMM code with ROPgadget.
http://shell-storm.org/project/ROPgadget/
https://github.com/JonathanSalwan/ROPgadget/tree/master
This tool reports the gadget in SMM driver.
This patch enabled CET ShadowStack for X86 SMM.
If CET is
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521
This patch adds SSP - shadow stack pointer to JumpBuffer.
It will be used for the platform that enabled CET/ShadowStack.
We add gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask
to control the global enable/disable.
Cc:
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521
This is to add CET related instruction in Nasm
because CET instruction is not supported yet.
See https://www.nasm.us/xdoc/2.14.02/html/nasmdocb.html
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
to each patch.
I also post all update to https://github.com/jyao1/edk2/tree/CET_V2
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen
Jiewen Yao (4):
MdePkg/Include: Add Nasm.inc
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521
This patch adds SSP - shadow stack pointer to JumpBuffer.
It will be used for the platform that enabled CET/ShadowStack.
We add gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask
to control the global enable/disable.
Cc: Eric
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521
We scan the SMM code with ROPgadget.
http://shell-storm.org/project/ROPgadget/
https://github.com/JonathanSalwan/ROPgadget/tree/master
This tool reports the gadget in SMM driver.
This patch enabled CET ShadowStack for X86 SMM.
If CET is
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521
Add information dump for Control Protection exception.
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen
---
Contribution Agreement 1.1
Signed-off-by: Yao Jiewen
Jiewen Yao (3):
MdePkg/BaseLib: Add Shadow Stack Support for X86.
UefiCpuPkg/ExceptionLib: Add CET support.
UefiCpuPkg/PiSmmCpu: Add Shadow Stack Support for X86 SMM.
MdePkg/Include/Library/BaseLib.h | 2 +
MdePkg/Library
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521
We scan the SMM code with ROPgadget.
http://shell-storm.org/project/ROPgadget/
https://github.com/JonathanSalwan/ROPgadget/tree/master
This tool reports the gadget in SMM driver.
This patch enabled CET ShadowStack for X86 SMM.
If CET is
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521
This patch adds SSP - shadow stack pointer to JumpBuffer.
It will be used for the platform that enabled CET/ShadowStack.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521
Add information dump for Control Protection exception.
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen
---
: Ray Ni
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen
Jiewen Yao (3):
MdePkg/BaseLib: Add Shadow Stack Support for X86.
UefiCpuPkg/ExceptionLib: Add CET support.
UefiCpuPkg/PiSmmCpu: Add Shadow Stack Support for X86 SMM.
MdePkg/Include
Feng
Cc: Liming Gao
Cc: Yonghong Zhu
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao
---
BaseTools/Source/Python/AutoGen/AutoGen.py | 15 ---
BaseTools/Source/Python/build/build.py | 2 ++
2 files changed, 10 insertions(+), 7 deletions
701 - 764 of 764 matches
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