[edk2] [PATCH] BaseTool/Build: Add --disable-include-path-check.

[Jiewen Yao]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1620

This option is added to disable the include path check
for outside of package.
The original purpose of thie check is to make sure EDK II
modules must not reference header files outside of the packages
they depend on or within the module's directory tree.

However, we do see the usage to build EDKII as executable running
in the operating system which requires include path to outside.
For example, EmulatorPkg. The current solution (soft link) is
weird hack - EmulatorPkg\Unix\Host\X11IncludeHack.

With this solution, this can be supported easily.

The patch is validated with and without --disable-include-path-check.
If user does not use --disable-include-path-check, the build will fail
with outside path in the include path.
If user uses --disable-include-path-check, the build will pass
with outside path in the include path.

Cc: Bob Feng 
Cc: Liming Gao 
Cc: Yonghong Zhu 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao 
---
 BaseTools/Source/Python/AutoGen/AutoGen.py | 15 ---
 BaseTools/Source/Python/build/build.py |  2 ++
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/BaseTools/Source/Python/AutoGen/AutoGen.py 
b/BaseTools/Source/Python/AutoGen/AutoGen.py
index e7dbf66e2f..568d535754 100644
--- a/BaseTools/Source/Python/AutoGen/AutoGen.py
+++ b/BaseTools/Source/Python/AutoGen/AutoGen.py
@@ -3037,13 +3037,14 @@ class ModuleAutoGen(AutoGen):
 # EDK II modules must not reference header files outside of the 
packages they depend on or
 # within the module's directory tree. Report error if violation.
 #
-for Path in IncPathList:
-if (Path not in self.IncludePathList) and (CommonPath([Path, 
self.MetaFile.Dir]) != self.MetaFile.Dir):
-ErrMsg = "The include directory for the EDK II module in 
this line is invalid %s specified in %s FLAGS '%s'" % (Path, Tool, FlagOption)
-EdkLogger.error("build",
-PARAMETER_INVALID,
-ExtraData=ErrMsg,
-File=str(self.MetaFile))
+if GlobalData.gDisableIncludePathCheck == False:
+for Path in IncPathList:
+if (Path not in self.IncludePathList) and 
(CommonPath([Path, self.MetaFile.Dir]) != self.MetaFile.Dir):
+ErrMsg = "The include directory for the EDK II module 
in this line is invalid %s specified in %s FLAGS '%s'" % (Path, Tool, 
FlagOption)
+EdkLogger.error("build",
+PARAMETER_INVALID,
+ExtraData=ErrMsg,
+File=str(self.MetaFile))
 RetVal += IncPathList
 return RetVal
 
diff --git a/BaseTools/Source/Python/build/build.py 
b/BaseTools/Source/Python/build/build.py
index 99e79d4dca..de641fb452 100644
--- a/BaseTools/Source/Python/build/build.py
+++ b/BaseTools/Source/Python/build/build.py
@@ -719,6 +719,7 @@ class Build():
 GlobalData.gBinCacheDest   = BuildOptions.BinCacheDest
 GlobalData.gBinCacheSource = BuildOptions.BinCacheSource
 GlobalData.gEnableGenfdsMultiThread = BuildOptions.GenfdsMultiThread
+GlobalData.gDisableIncludePathCheck = 
BuildOptions.DisableIncludePathCheck
 
 if GlobalData.gBinCacheDest and not GlobalData.gUseHashCache:
 EdkLogger.error("build", OPTION_NOT_SUPPORTED, 
ExtraData="--binary-destination must be used together with --hash.")
@@ -2268,6 +2269,7 @@ def MyOptionParser():
 Parser.add_option("--binary-destination", action="store", type="string", 
dest="BinCacheDest", help="Generate a cache of binary files in the specified 
directory.")
 Parser.add_option("--binary-source", action="store", type="string", 
dest="BinCacheSource", help="Consume a cache of binary files from the specified 
directory.")
 Parser.add_option("--genfds-multi-thread", action="store_true", 
dest="GenfdsMultiThread", default=False, help="Enable GenFds multi thread to 
generate ffs file.")
+Parser.add_option("--disable-include-path-check", action="store_true", 
dest="DisableIncludePathCheck", default=False, help="Disable the include path 
check for outside of package.")
 (Opt, Args) = Parser.parse_args()
 return (Opt, Args)
 
-- 
2.19.2.windows.1

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[edk2] [PATCH V3 2/4] MdePkg/BaseLib: Add Shadow Stack Support for X86.

[Jiewen Yao]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521

This patch adds SSP - shadow stack pointer to JumpBuffer.
It will be used for the platform that enabled CET/ShadowStack.

We add gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask
to control the global enable/disable.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen 
---
 MdePkg/Include/Library/BaseLib.h  |  2 ++
 MdePkg/Library/BaseLib/BaseLib.inf|  3 ++-
 MdePkg/Library/BaseLib/Ia32/LongJump.c| 28 +++-
 MdePkg/Library/BaseLib/Ia32/LongJump.nasm | 25 -
 MdePkg/Library/BaseLib/Ia32/SetJump.c | 28 +++-
 MdePkg/Library/BaseLib/Ia32/SetJump.nasm  | 23 +++-
 MdePkg/Library/BaseLib/X64/LongJump.nasm  | 27 ++-
 MdePkg/Library/BaseLib/X64/SetJump.nasm   | 23 +++-
 MdePkg/MdePkg.dec |  7 +
 9 files changed, 159 insertions(+), 7 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 9c42f82a7d..616ba2e95b 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -31,6 +31,7 @@ typedef struct {
   UINT32Ebp;
   UINT32Esp;
   UINT32Eip;
+  UINT32Ssp;
 } BASE_LIBRARY_JUMP_BUFFER;
 
 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4
@@ -54,6 +55,7 @@ typedef struct {
   UINT64Rip;
   UINT64MxCsr;
   UINT8 XmmBuffer[160]; ///< XMM6-XMM15.
+  UINT64Ssp;
 } BASE_LIBRARY_JUMP_BUFFER;
 
 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index f25a067a23..a0d6c372f9 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -1,7 +1,7 @@
 ## @file
 #  Base Library implementation.
 #
-#  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+#  Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
 #  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
 #  Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
 #
@@ -620,6 +620,7 @@
   gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength  ## 
SOMETIMES_CONSUMES
   gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength ## 
SOMETIMES_CONSUMES
   gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength   ## 
SOMETIMES_CONSUMES
+  gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask   ## 
SOMETIMES_CONSUMES
 
 [FeaturePcd]
   gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList  ## CONSUMES
diff --git a/MdePkg/Library/BaseLib/Ia32/LongJump.c 
b/MdePkg/Library/BaseLib/Ia32/LongJump.c
index 73973a9cce..2c1feb8373 100644
--- a/MdePkg/Library/BaseLib/Ia32/LongJump.c
+++ b/MdePkg/Library/BaseLib/Ia32/LongJump.c
@@ -1,7 +1,7 @@
 /** @file
   Implementation of _LongJump() on IA-32.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -36,6 +36,32 @@ InternalLongJump (
   )
 {
   _asm {
+mov eax, [PcdGet32 (PcdControlFlowEnforcementPropertyMask)]
+testeax, eax
+jz  CetDone
+_emit  0x0F
+_emit  0x20
+_emit  0xE0; mov eax, cr4
+bt  eax, 23; check if CET is enabled
+jnc CetDone
+
+mov edx, [esp + 4] ; edx = JumpBuffer
+mov edx, [edx + 24]; edx = target SSP
+_emit  0xF3
+_emit  0x0F
+_emit  0x1E
+_emit  0xC8; READSSP EAX
+sub edx, eax   ; edx = delta
+mov eax, edx   ; eax = delta
+
+shr eax, 2 ; eax = delta/sizeof(UINT32)
+_emit  0xF3
+_emit  0x0F
+_emit  0xAE
+_emit  0xE8; INCSSP EAX
+
+CetDone:
+
 pop eax ; skip return address
 pop edx ; edx <- JumpBuffer
 pop eax ; eax <- Value
diff --git a/MdePkg/Library/BaseLib/Ia32/LongJump.nasm 
b/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
index 7ef03462ee..57305d4981 100644
--- a/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
@@ -1,6 +1,6 @@
 ;--
 ;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2019, Intel Corporation. All rights 

[edk2] [PATCH V3 4/4] UefiCpuPkg/PiSmmCpu: Add Shadow Stack Support for X86 SMM.

[Jiewen Yao]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521

We scan the SMM code with ROPgadget.
http://shell-storm.org/project/ROPgadget/
https://github.com/JonathanSalwan/ROPgadget/tree/master
This tool reports the gadget in SMM driver.

This patch enabled CET ShadowStack for X86 SMM.
If CET is supported, SMM will enable CET ShadowStack.
SMM CET will save the OS CET context at SmmEntry and
restore OS CET context at SmmExit.

Test:
1) test Intel internal platform (x64 only, CET enabled/disabled)
Boot test:
CET supported or not supported CPU
on CET supported platform
  CET enabled/disabled
  PcdCpuSmmCetEnable enabled/disabled
  Single core/Multiple core
  PcdCpuSmmStackGuard enabled/disabled
  PcdCpuSmmProfileEnable enabled/disabled
  PcdCpuSmmStaticPageTable enabled/disabled
CET exception test:
  #CF generated with PcdCpuSmmStackGuard enabled/disabled.
Other exception test:
  #PF for normal stack overflow
  #PF for NX protection
  #PF for RO protection
CET env test:
  Launch SMM in CET enabled/disabled environment (DXE) - no impact to DXE

The test case can be found at
https://github.com/jyao1/SecurityEx/tree/master/ControlFlowPkg

2) test ovmf (both IA32 and X64 SMM, CET disabled only)
test OvmfIa32/Ovmf3264, with -D SMM_REQUIRE.
  qemu-system-x86_64.exe -machine q35,smm=on -smp 4
-serial file:serial.log
-drive if=pflash,format=raw,unit=0,file=OVMF_CODE.fd,readonly=on
-drive if=pflash,format=raw,unit=1,file=OVMF_VARS.fd
QEMU emulator version 3.1.0 (v3.1.0-11736-g7a30e7adb0-dirty)

3) not tested
IA32 CET enabled platform

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen 
---
 UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h |  23 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm|  39 +++
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c   |  38 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm   |  99 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm   |   6 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c  |  57 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c  |  12 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c |  97 ++--
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 103 -
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf   |   6 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c |  85 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c |  18 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h |   4 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c |   4 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm |  40 +++
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c|  39 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm| 120 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c   |  58 +-
 UefiCpuPkg/UefiCpuPkg.dec  |   6 +-
 19 files changed, 807 insertions(+), 47 deletions(-)

diff --git a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h 
b/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
index 4478003467..aec24b5dda 100644
--- a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
+++ b/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
@@ -1,7 +1,7 @@
 /** @file
 Library that provides CPU specific functions to support the PiSmmCpuDxeSmm 
module.
 
-Copyright (c) 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -160,14 +160,33 @@ SmmCpuFeaturesGetSmiHandlerSize (
   than zero and is called by the CPU that was elected as monarch during System
   Management Mode initialization.
 
+//
+// Append Shadow Stack after normal stack
+//
+// |= SmiStack
+// 
+--+---+
+// | Known Good Stack | Guard Page |SMM Stack | Known Good Shadow 
Stack | Guard Page |SMM Shadow Stack|
+// 
+--+---+
+// |   |PcdCpuSmmStackSize|
  |PcdCpuSmmShadowStackSize|
+// |< StackSize 
->|<- ShadowStackSize 
--->|
+// |   
   |
+// |< Processor N 
--->|
+// | low address (bottom)  
high address (top) |
+

[edk2] [PATCH V3 0/4] Add SMM CET support

[Jiewen Yao]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521

V3:
Add Nasm.inc to include CET related instruction as MACRO.
This is the only place to use DB.
Any other NASM just use the MACRO - 
SETSSBSY, READSSP_[E|R]AX, INCSSP_[E|R]AX
=

V2:
Fix emulation platform issue.
The NT32 platform cannot access CR4 register.
So we add a global PCD to choose disable CR4 access in SetJump/LongJump.
gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask
=

This patch series implement add CET ShadowStack support for SMM.

The CET document can be found at:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

Patch 1 adds SSP (ShadowStackPointer) to JUMP_BUFFER.
Patch 2 adds Control Protection exception (CP#) dump info.
Patch 3 adds CET ShadowStack support in SMM.

For more detail please refer to each patch. 

I also post all update to https://github.com/jyao1/edk2/tree/CET_V2

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen 

Jiewen Yao (4):
  MdePkg/Include: Add Nasm.inc
  MdePkg/BaseLib: Add Shadow Stack Support for X86.
  UefiCpuPkg/ExceptionLib: Add CET support.
  UefiCpuPkg/PiSmmCpu: Add Shadow Stack Support for X86 SMM.

 MdePkg/Include/Ia32/Nasm.inc  |  28 
 MdePkg/Include/Library/BaseLib.h  |   2 +
 MdePkg/Include/X64/Nasm.inc   |  28 
 MdePkg/Library/BaseLib/BaseLib.inf|   3 +-
 MdePkg/Library/BaseLib/Ia32/LongJump.c|  28 +++-
 MdePkg/Library/BaseLib/Ia32/LongJump.nasm |  25 +++-
 MdePkg/Library/BaseLib/Ia32/SetJump.c |  28 +++-
 MdePkg/Library/BaseLib/Ia32/SetJump.nasm  |  23 +++-
 MdePkg/Library/BaseLib/X64/LongJump.nasm  |  27 +++-
 MdePkg/Library/BaseLib/X64/SetJump.nasm   |  23 +++-
 MdePkg/MdePkg.dec |   7 +
 .../Include/Library/SmmCpuFeaturesLib.h   |  23 +++-
 .../CpuExceptionCommon.c  |   7 +-
 .../CpuExceptionCommon.h  |   3 +-
 .../Ia32/ArchExceptionHandler.c   |   5 +-
 .../X64/ArchExceptionHandler.c|   5 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm   |  39 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c  |  38 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm  |  99 ++-
 .../PiSmmCpuDxeSmm/Ia32/SmiException.nasm |   6 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c |  57 -
 UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c |  12 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c|  97 --
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h| 103 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf  |   6 +-
 .../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c   |  85 -
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c|  18 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h|   4 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c|   4 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm|  40 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c   |  39 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm   | 120 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c  |  58 -
 UefiCpuPkg/UefiCpuPkg.dec |   6 +-
 34 files changed, 1034 insertions(+), 62 deletions(-)
 create mode 100644 MdePkg/Include/Ia32/Nasm.inc
 create mode 100644 MdePkg/Include/X64/Nasm.inc
 create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm
 create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm

-- 
2.19.2.windows.1

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[edk2] [PATCH V3 1/4] MdePkg/Include: Add Nasm.inc

[Jiewen Yao]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521

This is to add CET related instruction in Nasm
because CET instruction is not supported yet.

See https://www.nasm.us/xdoc/2.14.02/html/nasmdocb.html

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen 
---
 MdePkg/Include/Ia32/Nasm.inc | 28 
 MdePkg/Include/X64/Nasm.inc  | 28 
 2 files changed, 56 insertions(+)

diff --git a/MdePkg/Include/Ia32/Nasm.inc b/MdePkg/Include/Ia32/Nasm.inc
new file mode 100644
index 00..c018bb3cae
--- /dev/null
+++ b/MdePkg/Include/Ia32/Nasm.inc
@@ -0,0 +1,28 @@
+;--
+;
+; Copyright (c) 2019, Intel Corporation. All rights reserved.
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD 
License
+; which accompanies this distribution.  The full text of the license may be 
found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Abstract:
+;
+;   This file provides macro definitions for NASM files.
+;
+;--
+
+%macro SETSSBSY0
+DB 0xF3, 0x0F, 0x01, 0xE8
+%endmacro
+
+%macro READSSP_EAX 0
+DB 0xF3, 0x0F, 0x1E, 0xC8
+%endmacro
+
+%macro INCSSP_EAX  0
+DB 0xF3, 0x0F, 0xAE, 0xE8
+%endmacro
diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc
new file mode 100644
index 00..129a330212
--- /dev/null
+++ b/MdePkg/Include/X64/Nasm.inc
@@ -0,0 +1,28 @@
+;--
+;
+; Copyright (c) 2019, Intel Corporation. All rights reserved.
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD 
License
+; which accompanies this distribution.  The full text of the license may be 
found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Abstract:
+;
+;   This file provides macro definitions for NASM files.
+;
+;--
+
+%macro SETSSBSY0
+DB 0xF3, 0x0F, 0x01, 0xE8
+%endmacro
+
+%macro READSSP_RAX 0
+DB 0xF3, 0x48, 0x0F, 0x1E, 0xC8
+%endmacro
+
+%macro INCSSP_RAX  0
+DB 0xF3, 0x48, 0x0F, 0xAE, 0xE8
+%endmacro
-- 
2.19.2.windows.1

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[edk2] [PATCH V3 3/4] UefiCpuPkg/ExceptionLib: Add CET support.

[Jiewen Yao]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521

Add information dump for Control Protection exception.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen 
---
 UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c| 7 
---
 UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h| 3 ++-
 UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c | 5 +++--
 UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c  | 5 +++--
 4 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
index 0576144a97..ca210d1de2 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
@@ -1,7 +1,7 @@
 /** @file
   CPU Exception Handler Library common functions.
 
-  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -20,7 +20,7 @@
 //
 // 1 means an error code will be pushed, otherwise 0
 //
-CONST UINT32 mErrorCodeFlag = 0x00027d00;
+CONST UINT32 mErrorCodeFlag = 0x00227d00;
 
 //
 // Define the maximum message length
@@ -49,7 +49,8 @@ CONST CHAR8 *mExceptionNameStr[] = {
   "#AC - Alignment Check",
   "#MC - Machine-Check",
   "#XM - SIMD floating-point",
-  "#VE - Virtualization"
+  "#VE - Virtualization",
+  "#CP - Control Protection"
 };
 
 #define EXCEPTION_KNOWN_NAME_NUM  (sizeof (mExceptionNameStr) / sizeof (CHAR8 
*))
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 83e55ab828..edf46cb60d 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -1,7 +1,7 @@
 /** @file
   Common header file for CPU Exception Handler Library.
 
-  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -39,6 +39,7 @@
 #define IA32_PF_EC_RSVD BIT3
 #define IA32_PF_EC_ID   BIT4
 #define IA32_PF_EC_PK   BIT5
+#define IA32_PF_EC_SS   BIT6
 #define IA32_PF_EC_SGX  BIT15
 
 #include "ArchInterruptDefs.h"
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
index 531258610a..f3d993af75 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
@@ -1,7 +1,7 @@
 /** @file
   IA32 CPU Exception Handler functons.
 
-  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -326,13 +326,14 @@ DumpCpuContext (
   );
 if (ExceptionType == EXCEPT_IA32_PAGE_FAULT) {
   InternalPrintMessage (
-"  I:%x R:%x U:%x W:%x P:%x PK:%x S:%x",
+"  I:%x R:%x U:%x W:%x P:%x PK:%x SS:%x SGX:%x",
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID)   != 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_RSVD) != 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_US)   != 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_WR)   != 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_P)!= 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_PK)   != 
0,
+(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SS)   != 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SGX)  != 0
 );
 }
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
index d7e883d19a..0183239e59 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
@@ -1,7 +1,7 @@
 /** @file
   x64 

[edk2] [PATCH V2 3/3] UefiCpuPkg/PiSmmCpu: Add Shadow Stack Support for X86 SMM.

[Jiewen Yao]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521

We scan the SMM code with ROPgadget.
http://shell-storm.org/project/ROPgadget/
https://github.com/JonathanSalwan/ROPgadget/tree/master
This tool reports the gadget in SMM driver.

This patch enabled CET ShadowStack for X86 SMM.
If CET is supported, SMM will enable CET ShadowStack.
SMM CET will save the OS CET context at SmmEntry and
restore OS CET context at SmmExit.

Test:
1) test Intel internal platform (x64 only, CET enabled/disabled)
Boot test:
CET supported or not supported CPU
on CET supported platform
  CET enabled/disabled
  PcdCpuSmmCetEnable enabled/disabled
  Single core/Multiple core
  PcdCpuSmmStackGuard enabled/disabled
  PcdCpuSmmProfileEnable enabled/disabled
  PcdCpuSmmStaticPageTable enabled/disabled
CET exception test:
  #CF generated with PcdCpuSmmStackGuard enabled/disabled.
Other exception test:
  #PF for normal stack overflow
  #PF for NX protection
  #PF for RO protection
CET env test:
  Launch SMM in CET enabled/disabled environment (DXE) - no impact to DXE

The test case can be found at
https://github.com/jyao1/SecurityEx/tree/master/ControlFlowPkg

2) test ovmf (both IA32 and X64 SMM, CET disabled only)
test OvmfIa32/Ovmf3264, with -D SMM_REQUIRE.
  qemu-system-x86_64.exe -machine q35,smm=on -smp 4
-serial file:serial.log
-drive if=pflash,format=raw,unit=0,file=OVMF_CODE.fd,readonly=on
-drive if=pflash,format=raw,unit=1,file=OVMF_VARS.fd
QEMU emulator version 3.1.0 (v3.1.0-11736-g7a30e7adb0-dirty)

3) not tested
IA32 CET enabled platform

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen 
---
 UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h |  23 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm|  37 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c   |  38 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm   |  98 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm   |   6 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c  |  57 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c  |  12 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c |  97 ++--
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 103 -
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf   |   6 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c |  85 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c |  18 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h |   4 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c |   4 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm |  38 +++
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c|  39 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm| 119 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c   |  58 +-
 UefiCpuPkg/UefiCpuPkg.dec  |   6 +-
 19 files changed, 801 insertions(+), 47 deletions(-)

diff --git a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h 
b/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
index 4478003467..aec24b5dda 100644
--- a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
+++ b/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
@@ -1,7 +1,7 @@
 /** @file
 Library that provides CPU specific functions to support the PiSmmCpuDxeSmm 
module.
 
-Copyright (c) 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -160,14 +160,33 @@ SmmCpuFeaturesGetSmiHandlerSize (
   than zero and is called by the CPU that was elected as monarch during System
   Management Mode initialization.
 
+//
+// Append Shadow Stack after normal stack
+//
+// |= SmiStack
+// 
+--+---+
+// | Known Good Stack | Guard Page |SMM Stack | Known Good Shadow 
Stack | Guard Page |SMM Shadow Stack|
+// 
+--+---+
+// |   |PcdCpuSmmStackSize|
  |PcdCpuSmmShadowStackSize|
+// |< StackSize 
->|<- ShadowStackSize 
--->|
+// |   
   |
+// |< Processor N 
--->|
+// | low address (bottom)  
high address (top) |
+//

[edk2] [PATCH V2 0/3] Add SMM CET support

[Jiewen Yao]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521

V2:
Fix emulation platform issue.
The NT32 platform cannot access CR4 register.
So we add a global PCD to choose disable CR4 access in SetJump/LongJump.
gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask
=

This patch series implement add CET ShadowStack support for SMM.

The CET document can be found at:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

Patch 1 adds SSP (ShadowStackPointer) to JUMP_BUFFER.
Patch 2 adds Control Protection exception (CP#) dump info.
Patch 3 adds CET ShadowStack support in SMM.

For more detail please refer to each patch. 

I also post all update to https://github.com/jyao1/edk2/tree/CET_V2

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen 

Jiewen Yao (3):
  MdePkg/BaseLib: Add Shadow Stack Support for X86.
  UefiCpuPkg/ExceptionLib: Add CET support.
  UefiCpuPkg/PiSmmCpu: Add Shadow Stack Support for X86 SMM.

 MdePkg/Include/Library/BaseLib.h  |   2 +
 MdePkg/Library/BaseLib/BaseLib.inf|   3 +-
 MdePkg/Library/BaseLib/Ia32/LongJump.c|  28 -
 MdePkg/Library/BaseLib/Ia32/LongJump.nasm |  23 +++-
 MdePkg/Library/BaseLib/Ia32/SetJump.c |  28 -
 MdePkg/Library/BaseLib/Ia32/SetJump.nasm  |  21 +++-
 MdePkg/Library/BaseLib/X64/LongJump.nasm  |  25 +++-
 MdePkg/Library/BaseLib/X64/SetJump.nasm   |  21 +++-
 MdePkg/MdePkg.dec |   7 ++
 .../Include/Library/SmmCpuFeaturesLib.h   |  23 +++-
 .../CpuExceptionCommon.c  |   7 +-
 .../CpuExceptionCommon.h  |   3 +-
 .../Ia32/ArchExceptionHandler.c   |   5 +-
 .../X64/ArchExceptionHandler.c|   5 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm   |  37 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c  |  38 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm  |  98 ++-
 .../PiSmmCpuDxeSmm/Ia32/SmiException.nasm |   6 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c |  57 -
 UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c |  12 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c|  97 --
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h| 103 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf  |   6 +-
 .../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c   |  85 -
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c|  18 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h|   4 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c|   4 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm|  38 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c   |  39 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm   | 119 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c  |  58 -
 UefiCpuPkg/UefiCpuPkg.dec |   6 +-
 32 files changed, 964 insertions(+), 62 deletions(-)
 create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm
 create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm

-- 
2.19.2.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH V2 2/3] UefiCpuPkg/ExceptionLib: Add CET support.

[Jiewen Yao]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521

Add information dump for Control Protection exception.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen 
---
 UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c| 7 
---
 UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h| 3 ++-
 UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c | 5 +++--
 UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c  | 5 +++--
 4 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
index 0576144a97..ca210d1de2 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
@@ -1,7 +1,7 @@
 /** @file
   CPU Exception Handler Library common functions.
 
-  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -20,7 +20,7 @@
 //
 // 1 means an error code will be pushed, otherwise 0
 //
-CONST UINT32 mErrorCodeFlag = 0x00027d00;
+CONST UINT32 mErrorCodeFlag = 0x00227d00;
 
 //
 // Define the maximum message length
@@ -49,7 +49,8 @@ CONST CHAR8 *mExceptionNameStr[] = {
   "#AC - Alignment Check",
   "#MC - Machine-Check",
   "#XM - SIMD floating-point",
-  "#VE - Virtualization"
+  "#VE - Virtualization",
+  "#CP - Control Protection"
 };
 
 #define EXCEPTION_KNOWN_NAME_NUM  (sizeof (mExceptionNameStr) / sizeof (CHAR8 
*))
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 83e55ab828..edf46cb60d 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -1,7 +1,7 @@
 /** @file
   Common header file for CPU Exception Handler Library.
 
-  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -39,6 +39,7 @@
 #define IA32_PF_EC_RSVD BIT3
 #define IA32_PF_EC_ID   BIT4
 #define IA32_PF_EC_PK   BIT5
+#define IA32_PF_EC_SS   BIT6
 #define IA32_PF_EC_SGX  BIT15
 
 #include "ArchInterruptDefs.h"
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
index 531258610a..f3d993af75 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
@@ -1,7 +1,7 @@
 /** @file
   IA32 CPU Exception Handler functons.
 
-  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -326,13 +326,14 @@ DumpCpuContext (
   );
 if (ExceptionType == EXCEPT_IA32_PAGE_FAULT) {
   InternalPrintMessage (
-"  I:%x R:%x U:%x W:%x P:%x PK:%x S:%x",
+"  I:%x R:%x U:%x W:%x P:%x PK:%x SS:%x SGX:%x",
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID)   != 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_RSVD) != 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_US)   != 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_WR)   != 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_P)!= 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_PK)   != 
0,
+(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SS)   != 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SGX)  != 0
 );
 }
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
index d7e883d19a..0183239e59 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
@@ -1,7 +1,7 @@
 /** @file
   x64 

[edk2] [PATCH V2 1/3] MdePkg/BaseLib: Add Shadow Stack Support for X86.

[Jiewen Yao]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521

This patch adds SSP - shadow stack pointer to JumpBuffer.
It will be used for the platform that enabled CET/ShadowStack.

We add gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask
to control the global enable/disable.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen 
---
 MdePkg/Include/Library/BaseLib.h  |  2 ++
 MdePkg/Library/BaseLib/BaseLib.inf|  3 ++-
 MdePkg/Library/BaseLib/Ia32/LongJump.c| 28 +++-
 MdePkg/Library/BaseLib/Ia32/LongJump.nasm | 23 +++-
 MdePkg/Library/BaseLib/Ia32/SetJump.c | 28 +++-
 MdePkg/Library/BaseLib/Ia32/SetJump.nasm  | 21 ++-
 MdePkg/Library/BaseLib/X64/LongJump.nasm  | 25 -
 MdePkg/Library/BaseLib/X64/SetJump.nasm   | 21 ++-
 MdePkg/MdePkg.dec |  7 +
 9 files changed, 151 insertions(+), 7 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 9c42f82a7d..616ba2e95b 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -31,6 +31,7 @@ typedef struct {
   UINT32Ebp;
   UINT32Esp;
   UINT32Eip;
+  UINT32Ssp;
 } BASE_LIBRARY_JUMP_BUFFER;
 
 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4
@@ -54,6 +55,7 @@ typedef struct {
   UINT64Rip;
   UINT64MxCsr;
   UINT8 XmmBuffer[160]; ///< XMM6-XMM15.
+  UINT64Ssp;
 } BASE_LIBRARY_JUMP_BUFFER;
 
 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index f25a067a23..a0d6c372f9 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -1,7 +1,7 @@
 ## @file
 #  Base Library implementation.
 #
-#  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+#  Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
 #  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
 #  Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
 #
@@ -620,6 +620,7 @@
   gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength  ## 
SOMETIMES_CONSUMES
   gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength ## 
SOMETIMES_CONSUMES
   gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength   ## 
SOMETIMES_CONSUMES
+  gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask   ## 
SOMETIMES_CONSUMES
 
 [FeaturePcd]
   gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList  ## CONSUMES
diff --git a/MdePkg/Library/BaseLib/Ia32/LongJump.c 
b/MdePkg/Library/BaseLib/Ia32/LongJump.c
index 73973a9cce..2c1feb8373 100644
--- a/MdePkg/Library/BaseLib/Ia32/LongJump.c
+++ b/MdePkg/Library/BaseLib/Ia32/LongJump.c
@@ -1,7 +1,7 @@
 /** @file
   Implementation of _LongJump() on IA-32.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -36,6 +36,32 @@ InternalLongJump (
   )
 {
   _asm {
+mov eax, [PcdGet32 (PcdControlFlowEnforcementPropertyMask)]
+testeax, eax
+jz  CetDone
+_emit  0x0F
+_emit  0x20
+_emit  0xE0; mov eax, cr4
+bt  eax, 23; check if CET is enabled
+jnc CetDone
+
+mov edx, [esp + 4] ; edx = JumpBuffer
+mov edx, [edx + 24]; edx = target SSP
+_emit  0xF3
+_emit  0x0F
+_emit  0x1E
+_emit  0xC8; READSSP EAX
+sub edx, eax   ; edx = delta
+mov eax, edx   ; eax = delta
+
+shr eax, 2 ; eax = delta/sizeof(UINT32)
+_emit  0xF3
+_emit  0x0F
+_emit  0xAE
+_emit  0xE8; INCSSP EAX
+
+CetDone:
+
 pop eax ; skip return address
 pop edx ; edx <- JumpBuffer
 pop eax ; eax <- Value
diff --git a/MdePkg/Library/BaseLib/Ia32/LongJump.nasm 
b/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
index 7ef03462ee..1e806fb635 100644
--- a/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
@@ -1,6 +1,6 @@
 ;--
 ;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 ; This program and the 

[edk2] [PATCH 1/3] MdePkg/BaseLib: Add Shadow Stack Support for X86.

[Jiewen Yao]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521

This patch adds SSP - shadow stack pointer to JumpBuffer.
It will be used for the platform that enabled CET/ShadowStack.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen 
---
 MdePkg/Include/Library/BaseLib.h  |  2 ++
 MdePkg/Library/BaseLib/Ia32/LongJump.nasm | 18 +-
 MdePkg/Library/BaseLib/Ia32/SetJump.nasm  | 17 -
 MdePkg/Library/BaseLib/X64/LongJump.nasm  | 20 +++-
 MdePkg/Library/BaseLib/X64/SetJump.nasm   | 17 -
 5 files changed, 70 insertions(+), 4 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 9c42f82a7d..616ba2e95b 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -31,6 +31,7 @@ typedef struct {
   UINT32Ebp;
   UINT32Esp;
   UINT32Eip;
+  UINT32Ssp;
 } BASE_LIBRARY_JUMP_BUFFER;
 
 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4
@@ -54,6 +55,7 @@ typedef struct {
   UINT64Rip;
   UINT64MxCsr;
   UINT8 XmmBuffer[160]; ///< XMM6-XMM15.
+  UINT64Ssp;
 } BASE_LIBRARY_JUMP_BUFFER;
 
 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
diff --git a/MdePkg/Library/BaseLib/Ia32/LongJump.nasm 
b/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
index 7ef03462ee..e0f98c195e 100644
--- a/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
@@ -1,6 +1,6 @@
 ;--
 ;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 ; This program and the accompanying materials
 ; are licensed and made available under the terms and conditions of the BSD 
License
 ; which accompanies this distribution.  The full text of the license may be 
found at
@@ -31,6 +31,22 @@
 ;--
 global ASM_PFX(InternalLongJump)
 ASM_PFX(InternalLongJump):
+
+mov eax, cr4
+bt  eax, 23; check if CET is enabled
+jnc CetDone
+
+mov edx, [esp + 4] ; edx = JumpBuffer
+mov edx, [edx + 24]; edx = target SSP
+DB  0xF3, 0x0F, 0x1E, 0xC8 ; READSSP EAX
+sub edx, eax   ; eax = delta
+mov eax, edx   ; eax = delta
+
+shr eax, 2 ; eax = delta/sizeof(UINT32)
+DB  0xF3, 0x0F, 0xAE, 0xE8 ; INCSSP EAX
+
+CetDone:
+
 pop eax ; skip return address
 pop edx ; edx <- JumpBuffer
 pop eax ; eax <- Value
diff --git a/MdePkg/Library/BaseLib/Ia32/SetJump.nasm 
b/MdePkg/Library/BaseLib/Ia32/SetJump.nasm
index 6d3a5a25bb..51e0d5351c 100644
--- a/MdePkg/Library/BaseLib/Ia32/SetJump.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/SetJump.nasm
@@ -1,6 +1,6 @@
 ;--
 ;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 ; This program and the accompanying materials
 ; are licensed and made available under the terms and conditions of the BSD 
License
 ; which accompanies this distribution.  The full text of the license may be 
found at
@@ -37,6 +37,21 @@ ASM_PFX(SetJump):
 pop ecx
 pop ecx ; ecx <- return address
 mov edx, [esp]
+
+xor eax, eax
+mov [edx + 24], eax; save 0 to SSP
+
+mov eax, cr4
+bt  eax, 23; check if CET is enabled
+jnc CetDone
+
+mov eax, 1
+DB  0xF3, 0x0F, 0xAE, 0xE8 ; INCSSP EAX to read original SSP
+DB  0xF3, 0x0F, 0x1E, 0xC8 ; READSSP EAX
+mov [edx + 0x24], eax  ; save SSP
+
+CetDone:
+
 mov [edx], ebx
 mov [edx + 4], esi
 mov [edx + 8], edi
diff --git a/MdePkg/Library/BaseLib/X64/LongJump.nasm 
b/MdePkg/Library/BaseLib/X64/LongJump.nasm
index 3bac27469e..5f3f07da07 100644
--- a/MdePkg/Library/BaseLib/X64/LongJump.nasm
+++ b/MdePkg/Library/BaseLib/X64/LongJump.nasm
@@ -1,6 +1,6 @@
 ;--
 ;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 ; This program and the accompanying materials
 ; are licensed and made available under the terms and conditions of the BSD 
License
 ; which accompanies this distribution.  The full text of the license may be 

[edk2] [PATCH 2/3] UefiCpuPkg/ExceptionLib: Add CET support.

[Jiewen Yao]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521

Add information dump for Control Protection exception.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen 
---
 UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c| 7 
---
 UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h| 3 ++-
 UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c | 5 +++--
 UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c  | 5 +++--
 4 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
index 0576144a97..ca210d1de2 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
@@ -1,7 +1,7 @@
 /** @file
   CPU Exception Handler Library common functions.
 
-  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -20,7 +20,7 @@
 //
 // 1 means an error code will be pushed, otherwise 0
 //
-CONST UINT32 mErrorCodeFlag = 0x00027d00;
+CONST UINT32 mErrorCodeFlag = 0x00227d00;
 
 //
 // Define the maximum message length
@@ -49,7 +49,8 @@ CONST CHAR8 *mExceptionNameStr[] = {
   "#AC - Alignment Check",
   "#MC - Machine-Check",
   "#XM - SIMD floating-point",
-  "#VE - Virtualization"
+  "#VE - Virtualization",
+  "#CP - Control Protection"
 };
 
 #define EXCEPTION_KNOWN_NAME_NUM  (sizeof (mExceptionNameStr) / sizeof (CHAR8 
*))
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 83e55ab828..edf46cb60d 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -1,7 +1,7 @@
 /** @file
   Common header file for CPU Exception Handler Library.
 
-  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -39,6 +39,7 @@
 #define IA32_PF_EC_RSVD BIT3
 #define IA32_PF_EC_ID   BIT4
 #define IA32_PF_EC_PK   BIT5
+#define IA32_PF_EC_SS   BIT6
 #define IA32_PF_EC_SGX  BIT15
 
 #include "ArchInterruptDefs.h"
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
index 531258610a..f3d993af75 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
@@ -1,7 +1,7 @@
 /** @file
   IA32 CPU Exception Handler functons.
 
-  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -326,13 +326,14 @@ DumpCpuContext (
   );
 if (ExceptionType == EXCEPT_IA32_PAGE_FAULT) {
   InternalPrintMessage (
-"  I:%x R:%x U:%x W:%x P:%x PK:%x S:%x",
+"  I:%x R:%x U:%x W:%x P:%x PK:%x SS:%x SGX:%x",
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID)   != 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_RSVD) != 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_US)   != 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_WR)   != 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_P)!= 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_PK)   != 
0,
+(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SS)   != 
0,
 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SGX)  != 0
 );
 }
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
index d7e883d19a..0183239e59 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
@@ -1,7 +1,7 @@
 /** @file
   x64 

[edk2] [PATCH 3/3] UefiCpuPkg/PiSmmCpu: Add Shadow Stack Support for X86 SMM.

[Jiewen Yao]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521

We scan the SMM code with ROPgadget.
http://shell-storm.org/project/ROPgadget/
https://github.com/JonathanSalwan/ROPgadget/tree/master
This tool reports the gadget in SMM driver.

This patch enabled CET ShadowStack for X86 SMM.
If CET is supported, SMM will enable CET ShadowStack.
SMM CET will save the OS CET context at SmmEntry and
restore OS CET context at SmmExit.

Test:
1) test Intel internal platform (x64 only, CET enabled/disabled)
Boot test:
CET supported or not supported CPU
on CET supported platform
  CET enabled/disabled
  PcdCpuSmmCetEnable enabled/disabled
  Single core/Multiple core
  PcdCpuSmmStackGuard enabled/disabled
  PcdCpuSmmProfileEnable enabled/disabled
  PcdCpuSmmStaticPageTable enabled/disabled
CET exception test:
  #CF generated with PcdCpuSmmStackGuard enabled/disabled.
Other exception test:
  #PF for normal stack overflow
  #PF for NX protection
  #PF for RO protection
CET env test:
  Launch SMM in CET enabled/disabled environment (DXE) - no impact to DXE

The test case can be found at
https://github.com/jyao1/SecurityEx/tree/master/ControlFlowPkg

2) test ovmf (both IA32 and X64 SMM, CET disabled only)
test OvmfIa32/Ovmf3264, with -D SMM_REQUIRE.
  qemu-system-x86_64.exe -machine q35,smm=on -smp 4
-serial file:serial.log
-drive if=pflash,format=raw,unit=0,file=OVMF_CODE.fd,readonly=on
-drive if=pflash,format=raw,unit=1,file=OVMF_VARS.fd
QEMU emulator version 3.1.0 (v3.1.0-11736-g7a30e7adb0-dirty)

3) not tested
IA32 CET enabled platform

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen 
---
 UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h |  23 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm|  37 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c   |  38 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm   |  98 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm   |   6 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c  |  57 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c  |  12 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c |  97 ++--
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 103 -
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf   |   6 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c |  85 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c |  18 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h |   4 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c |   4 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm |  38 +++
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c|  39 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm| 119 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c   |  58 +-
 UefiCpuPkg/UefiCpuPkg.dec  |  13 ++-
 19 files changed, 808 insertions(+), 47 deletions(-)

diff --git a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h 
b/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
index 4478003467..aec24b5dda 100644
--- a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
+++ b/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
@@ -1,7 +1,7 @@
 /** @file
 Library that provides CPU specific functions to support the PiSmmCpuDxeSmm 
module.
 
-Copyright (c) 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -160,14 +160,33 @@ SmmCpuFeaturesGetSmiHandlerSize (
   than zero and is called by the CPU that was elected as monarch during System
   Management Mode initialization.
 
+//
+// Append Shadow Stack after normal stack
+//
+// |= SmiStack
+// 
+--+---+
+// | Known Good Stack | Guard Page |SMM Stack | Known Good Shadow 
Stack | Guard Page |SMM Shadow Stack|
+// 
+--+---+
+// |   |PcdCpuSmmStackSize|
  |PcdCpuSmmShadowStackSize|
+// |< StackSize 
->|<- ShadowStackSize 
--->|
+// |   
   |
+// |< Processor N 
--->|
+// | low address (bottom)  
high address (top) |
+

[edk2] [PATCH 0/3] Add SMM CET support

[Jiewen Yao]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521

This patch series implement add CET ShadowStack support for SMM.

The CET document can be found at:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

Patch 1 adds SSP (ShadowStackPointer) to JUMP_BUFFER.
Patch 2 adds Control Protection exception (CP#) dump info.
Patch 3 adds CET ShadowStack support in SMM.

For more detail please refer to each patch. 

I also post all update to https://github.com/jyao1/edk2/tree/CET

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yao Jiewen 

Jiewen Yao (3):
  MdePkg/BaseLib: Add Shadow Stack Support for X86.
  UefiCpuPkg/ExceptionLib: Add CET support.
  UefiCpuPkg/PiSmmCpu: Add Shadow Stack Support for X86 SMM.

 MdePkg/Include/Library/BaseLib.h  |   2 +
 MdePkg/Library/BaseLib/Ia32/LongJump.nasm |  18 ++-
 MdePkg/Library/BaseLib/Ia32/SetJump.nasm  |  17 ++-
 MdePkg/Library/BaseLib/X64/LongJump.nasm  |  20 ++-
 MdePkg/Library/BaseLib/X64/SetJump.nasm   |  17 ++-
 .../Include/Library/SmmCpuFeaturesLib.h   |  23 +++-
 .../CpuExceptionCommon.c  |   7 +-
 .../CpuExceptionCommon.h  |   3 +-
 .../Ia32/ArchExceptionHandler.c   |   5 +-
 .../X64/ArchExceptionHandler.c|   5 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm   |  37 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c  |  38 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm  |  98 ++-
 .../PiSmmCpuDxeSmm/Ia32/SmiException.nasm |   6 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c |  57 -
 UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c |  12 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c|  97 --
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h| 103 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf  |   6 +-
 .../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c   |  85 -
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c|  18 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h|   4 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c|   4 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm|  38 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c   |  39 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm   | 119 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c  |  58 -
 UefiCpuPkg/UefiCpuPkg.dec |  13 +-
 28 files changed, 890 insertions(+), 59 deletions(-)
 create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm
 create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm

-- 
2.19.2.windows.1

___
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edk2-devel@lists.01.org
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[edk2] [PATCH V2] BaseTool/GenC: Fix build error when type is BASE or USER_DEFINED.

[Jiewen Yao]

https://bugzilla.tianocore.org/show_bug.cgi?id=1544

=
V2: (Feedback from Liming) Add filter for 1) below:
Only constructor/destructor with BASE type is included here.
The constructor/destructor with PEI/DXE/SMM type is still excluded
to keep original behavior.

Test: NT32 build and boot successfully.

=

1) The GenC tool does not include the constructor/destructor for
USER_DEFINED module. It should be included.
Only constructor/destructor with BASE type is included here.
The constructor/destructor with PEI/DXE/SMM type is still excluded
to keep original behavior.

2) The GenC tool includes the UnloadImage code for BASE module.
It should NOT be included.

3) The GenC tool uses EFI_STATUS and ASSERT_EFI_ERROR for BASE type.
It should use RETURN_STATUS and ASSERT_RETURN_ERROR.

4) The GenC tool miss DebugLib.h for BASE or USER_DEFINED module
AutoGen.c. Only Base.h is there. It should add Library/DebugLib.h.

Cc: Bob Feng 
Cc: Liming Gao 
Cc: Yonghong Zhu 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao 
---
 BaseTools/Source/Python/AutoGen/GenC.py | 56 ++--
 1 file changed, 29 insertions(+), 27 deletions(-)

diff --git a/BaseTools/Source/Python/AutoGen/GenC.py 
b/BaseTools/Source/Python/AutoGen/GenC.py
index 9700bf8527..a922464f56 100644
--- a/BaseTools/Source/Python/AutoGen/GenC.py
+++ b/BaseTools/Source/Python/AutoGen/GenC.py
@@ -684,7 +684,7 @@ ${Function} (
 gLibraryStructorCall = {
 SUP_MODULE_BASE  : TemplateString("""${BEGIN}
   Status = ${Function} ();
-  ASSERT_EFI_ERROR (Status);${END}
+  ASSERT_RETURN_ERROR (Status);${END}
 """),
 
 'PEI'   : TemplateString("""${BEGIN}
@@ -714,7 +714,7 @@ ProcessLibrary${Type}List (
   VOID
   )
 {
-${BEGIN}  EFI_STATUS  Status;
+${BEGIN}  RETURN_STATUS  Status;
 ${FunctionCall}${END}
 }
 """),
@@ -768,7 +768,7 @@ ${FunctionCall}${END}
 gBasicHeaderFile = "Base.h"
 
 gModuleTypeHeaderFile = {
-SUP_MODULE_BASE  :   [gBasicHeaderFile],
+SUP_MODULE_BASE  :   [gBasicHeaderFile, "Library/DebugLib.h"],
 SUP_MODULE_SEC   :   ["PiPei.h", "Library/DebugLib.h"],
 SUP_MODULE_PEI_CORE  :   ["PiPei.h", "Library/DebugLib.h", 
"Library/PeiCoreEntryPoint.h"],
 SUP_MODULE_PEIM  :   ["PiPei.h", "Library/DebugLib.h", 
"Library/PeimEntryPoint.h"],
@@ -782,7 +782,7 @@ gModuleTypeHeaderFile = {
 SUP_MODULE_SMM_CORE  :   ["PiDxe.h", "Library/BaseLib.h", 
"Library/DebugLib.h", "Library/UefiDriverEntryPoint.h"],
 SUP_MODULE_MM_STANDALONE :   ["PiMm.h", "Library/BaseLib.h", 
"Library/DebugLib.h", "Library/StandaloneMmDriverEntryPoint.h"],
 SUP_MODULE_MM_CORE_STANDALONE :  ["PiMm.h", "Library/BaseLib.h", 
"Library/DebugLib.h", "Library/StandaloneMmCoreEntryPoint.h"],
-SUP_MODULE_USER_DEFINED  :   [gBasicHeaderFile]
+SUP_MODULE_USER_DEFINED  :   [gBasicHeaderFile, "Library/DebugLib.h"]
 }
 
 ## Autogen internal worker macro to define DynamicEx PCD name includes both 
the TokenSpaceGuidName
@@ -1345,16 +1345,17 @@ def CreateLibraryConstructorCode(Info, AutoGenC, 
AutoGenH):
 if Lib.ModuleType in [SUP_MODULE_BASE, SUP_MODULE_SEC]:
 
ConstructorPrototypeString.Append(gLibraryStructorPrototype[SUP_MODULE_BASE].Replace(Dict))
 
ConstructorCallingString.Append(gLibraryStructorCall[SUP_MODULE_BASE].Replace(Dict))
-elif Lib.ModuleType in SUP_MODULE_SET_PEI:
-
ConstructorPrototypeString.Append(gLibraryStructorPrototype['PEI'].Replace(Dict))
-
ConstructorCallingString.Append(gLibraryStructorCall['PEI'].Replace(Dict))
-elif Lib.ModuleType in [SUP_MODULE_DXE_CORE, SUP_MODULE_DXE_DRIVER, 
SUP_MODULE_DXE_SMM_DRIVER, SUP_MODULE_DXE_RUNTIME_DRIVER,
-SUP_MODULE_DXE_SAL_DRIVER, 
SUP_MODULE_UEFI_DRIVER, SUP_MODULE_UEFI_APPLICATION, SUP_MODULE_SMM_CORE]:
-
ConstructorPrototypeString.Append(gLibraryStructorPrototype['DXE'].Replace(Dict))
-
ConstructorCallingString.Append(gLibraryStructorCall['DXE'].Replace(Dict))
-elif Lib.ModuleType in [SUP_MODULE_MM_STANDALONE, 
SUP_MODULE_MM_CORE_STANDALONE]:
-
ConstructorPrototypeString.Append(gLibraryStructorPrototype['MM'].Replace(Dict))
-
ConstructorCallingString.Append(gLibraryStructorCall['MM'].Replace(Dict))
+if Info.ModuleType not in [SUP_MODULE_BASE, SUP_MODULE_USER_DEFINED]:
+if Lib.ModuleType in SUP_MODULE_SET_PEI:
+
ConstructorPrototypeString.Append(gLibraryStructorPrototype['PEI'].Replace(Dict))
+
ConstructorCallingString.Append(gLibraryStructorCall['PEI'].Re

[edk2] [PATCH] BaseTool/GenC: Fix build error when type is BASE or USER_DEFINED.

[Jiewen Yao]

https://bugzilla.tianocore.org/show_bug.cgi?id=1544

1) The GenC tool does not include the constructor/destructor for
USER_DEFINED module. It should be included.

2) The GenC tool includes the UnloadImage code for BASE module.
It should NOT be included.

3) The GenC tool uses EFI_STATUS and ASSERT_EFI_ERROR for BASE type.
It should use RETURN_STATUS and ASSERT_RETURN_ERROR.

4) The GenC tool miss DebugLib.h for BASE or USER_DEFINED module
AutoGen.c. Only Base.h is there. It should add Library/DebugLib.h.

Cc: Bob Feng 
Cc: Liming Gao 
Cc: Yonghong Zhu 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao 
---
 BaseTools/Source/Python/AutoGen/GenC.py | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/BaseTools/Source/Python/AutoGen/GenC.py 
b/BaseTools/Source/Python/AutoGen/GenC.py
index 9700bf8527..c4bba8da17 100644
--- a/BaseTools/Source/Python/AutoGen/GenC.py
+++ b/BaseTools/Source/Python/AutoGen/GenC.py
@@ -684,7 +684,7 @@ ${Function} (
 gLibraryStructorCall = {
 SUP_MODULE_BASE  : TemplateString("""${BEGIN}
   Status = ${Function} ();
-  ASSERT_EFI_ERROR (Status);${END}
+  ASSERT_RETURN_ERROR (Status);${END}
 """),
 
 'PEI'   : TemplateString("""${BEGIN}
@@ -714,7 +714,7 @@ ProcessLibrary${Type}List (
   VOID
   )
 {
-${BEGIN}  EFI_STATUS  Status;
+${BEGIN}  RETURN_STATUS  Status;
 ${FunctionCall}${END}
 }
 """),
@@ -768,7 +768,7 @@ ${FunctionCall}${END}
 gBasicHeaderFile = "Base.h"
 
 gModuleTypeHeaderFile = {
-SUP_MODULE_BASE  :   [gBasicHeaderFile],
+SUP_MODULE_BASE  :   [gBasicHeaderFile, "Library/DebugLib.h"],
 SUP_MODULE_SEC   :   ["PiPei.h", "Library/DebugLib.h"],
 SUP_MODULE_PEI_CORE  :   ["PiPei.h", "Library/DebugLib.h", 
"Library/PeiCoreEntryPoint.h"],
 SUP_MODULE_PEIM  :   ["PiPei.h", "Library/DebugLib.h", 
"Library/PeimEntryPoint.h"],
@@ -782,7 +782,7 @@ gModuleTypeHeaderFile = {
 SUP_MODULE_SMM_CORE  :   ["PiDxe.h", "Library/BaseLib.h", 
"Library/DebugLib.h", "Library/UefiDriverEntryPoint.h"],
 SUP_MODULE_MM_STANDALONE :   ["PiMm.h", "Library/BaseLib.h", 
"Library/DebugLib.h", "Library/StandaloneMmDriverEntryPoint.h"],
 SUP_MODULE_MM_CORE_STANDALONE :  ["PiMm.h", "Library/BaseLib.h", 
"Library/DebugLib.h", "Library/StandaloneMmCoreEntryPoint.h"],
-SUP_MODULE_USER_DEFINED  :   [gBasicHeaderFile]
+SUP_MODULE_USER_DEFINED  :   [gBasicHeaderFile, "Library/DebugLib.h"]
 }
 
 ## Autogen internal worker macro to define DynamicEx PCD name includes both 
the TokenSpaceGuidName
@@ -1373,7 +1373,7 @@ def CreateLibraryConstructorCode(Info, AutoGenC, 
AutoGenH):
 if Info.IsLibrary:
 AutoGenH.Append("${BEGIN}${FunctionPrototype}${END}", Dict)
 else:
-if Info.ModuleType in [SUP_MODULE_BASE, SUP_MODULE_SEC]:
+if Info.ModuleType in [SUP_MODULE_BASE, SUP_MODULE_SEC, 
SUP_MODULE_USER_DEFINED]:
 AutoGenC.Append(gLibraryString[SUP_MODULE_BASE].Replace(Dict))
 elif Info.ModuleType in SUP_MODULE_SET_PEI:
 AutoGenC.Append(gLibraryString['PEI'].Replace(Dict))
@@ -1435,7 +1435,7 @@ def CreateLibraryDestructorCode(Info, AutoGenC, AutoGenH):
 if Info.IsLibrary:
 AutoGenH.Append("${BEGIN}${FunctionPrototype}${END}", Dict)
 else:
-if Info.ModuleType in [SUP_MODULE_BASE, SUP_MODULE_SEC]:
+if Info.ModuleType in [SUP_MODULE_BASE, SUP_MODULE_SEC, 
SUP_MODULE_USER_DEFINED]:
 AutoGenC.Append(gLibraryString[SUP_MODULE_BASE].Replace(Dict))
 elif Info.ModuleType in SUP_MODULE_SET_PEI:
 AutoGenC.Append(gLibraryString['PEI'].Replace(Dict))
@@ -1533,7 +1533,7 @@ def CreateModuleEntryPointCode(Info, AutoGenC, AutoGenH):
 #   @param  AutoGenHThe TemplateString object for header file
 #
 def CreateModuleUnloadImageCode(Info, AutoGenC, AutoGenH):
-if Info.IsLibrary or Info.ModuleType in [SUP_MODULE_USER_DEFINED, 
SUP_MODULE_SEC]:
+if Info.IsLibrary or Info.ModuleType in [SUP_MODULE_USER_DEFINED, 
SUP_MODULE_BASE, SUP_MODULE_SEC]:
 return
 #
 # Unload Image Handlers
-- 
2.19.2.windows.1

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[edk2] [PATCH V3 1/2] IntelSiliconPkg/VtdPmrPei: Add premem support.

[Jiewen Yao]

Remove memory discovered dependency to support both premem
VTD_INFO_PPI and postmem VTD_INFO_PPI.

If VTD_INFO_PPI is installed before memory is ready, this
driver protects all memory region.
If VTD_INFO_PPI is installed or reinstalled after memory
is ready, this driver allocates DMA buffer and protect rest.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c| 580 
++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c  | 130 ++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c   | 846 
+++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.h   |  93 +++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf |  11 +-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c   | 293 +++
 6 files changed, 1356 insertions(+), 597 deletions(-)

diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c 
b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c
new file mode 100644
index 000..891efa6
--- /dev/null
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c
@@ -0,0 +1,580 @@
+/** @file
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "IntelVTdPmrPei.h"
+
+/**
+  Dump DMAR DeviceScopeEntry.
+
+  @param[in]  DmarDeviceScopeEntry  DMAR DeviceScopeEntry
+**/
+VOID
+DumpDmarDeviceScopeEntry (
+  IN EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DmarDeviceScopeEntry
+  )
+{
+  UINTN   PciPathNumber;
+  UINTN   PciPathIndex;
+  EFI_ACPI_DMAR_PCI_PATH  *PciPath;
+
+  if (DmarDeviceScopeEntry == NULL) {
+return;
+  }
+
+  DEBUG ((DEBUG_INFO,
+"
*\n"
+));
+  DEBUG ((DEBUG_INFO,
+"*   DMA-Remapping Device Scope Entry Structure
  *\n"
+));
+  DEBUG ((DEBUG_INFO,
+"
*\n"
+));
+  DEBUG ((DEBUG_INFO,
+(sizeof(UINTN) == sizeof(UINT64)) ?
+"DMAR Device Scope Entry address .. 0x%016lx\n" :
+"DMAR Device Scope Entry address .. 0x%08x\n",
+DmarDeviceScopeEntry
+));
+  DEBUG ((DEBUG_INFO,
+"  Device Scope Entry Type  0x%02x\n",
+DmarDeviceScopeEntry->Type
+));
+  switch (DmarDeviceScopeEntry->Type) {
+  case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT:
+DEBUG ((DEBUG_INFO,
+  "PCI Endpoint Device\n"
+  ));
+break;
+  case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE:
+DEBUG ((DEBUG_INFO,
+  "PCI Sub-hierachy\n"
+  ));
+break;
+  default:
+break;
+  }
+  DEBUG ((DEBUG_INFO,
+"  Length . 0x%02x\n",
+DmarDeviceScopeEntry->Length
+));
+  DEBUG ((DEBUG_INFO,
+"  Enumeration ID . 0x%02x\n",
+DmarDeviceScopeEntry->EnumerationId
+));
+  DEBUG ((DEBUG_INFO,
+"  Starting Bus Number  0x%02x\n",
+DmarDeviceScopeEntry->StartBusNumber
+));
+
+  PciPathNumber = (DmarDeviceScopeEntry->Length - 
sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER)) / 
sizeof(EFI_ACPI_DMAR_PCI_PATH);
+  PciPath = (EFI_ACPI_DMAR_PCI_PATH *)(DmarDeviceScopeEntry + 1);
+  for (PciPathIndex = 0; PciPathIndex < PciPathNumber; PciPathIndex++) {
+DEBUG ((DEBUG_INFO,
+  "  Device . 0x%02x\n",
+  PciPath[PciPathIndex].Device
+  ));
+DEBUG ((DEBUG_INFO,
+  "  Function ... 0x%02x\n",
+  PciPath[PciPathIndex].Function
+  ));
+  }
+
+  DEBUG ((DEBUG_INFO,
+"
*\n\n"
+));
+
+  return;
+}
+
+/**
+  Dump DMAR RMRR table.
+
+  @param[in]  Rmrr  DMAR RMRR table
+**/
+VOID
+DumpDmarRmrr (
+  IN EFI_ACPI_DMAR_RMRR_HEADER *Rmrr
+  )
+{
+  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER   *DmarDeviceScopeEntry;
+  INTNRm

[edk2] [PATCH V3 2/2] IntelSiliconPkg/VtdPeiSample: Add premem support.

[Jiewen Yao]

Before memory is ready, this sample produces one VTd engine.
After memory and silicon is initialized, this sample produces
both IGD VTd engine and all-rest VTd engine by reinstall the
FV_INFO_PPI.

This update is to demonstrate how to support pre-mem VTd usage.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c 
  | 234 +---
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
 |   2 +-
 2 files changed, 201 insertions(+), 35 deletions(-)

diff --git 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
index 6267da7..852dc0e 100644
--- 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
+++ 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define R_SA_MCHBAR   (0x48)
 #define R_SA_GGC  (0x50)
@@ -33,6 +34,8 @@
 #define R_SA_MCHBAR_VTD1_OFFSET  0x5400  ///< HW UNIT for IGD
 #define R_SA_MCHBAR_VTD2_OFFSET  0x5410  ///< HW UNIT for all other - PEG, 
USB, SATA etc
 
+EFI_GUID gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 
0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}};
+
 typedef struct {
   EFI_ACPI_DMAR_HEADER DmarHeader;
   //
@@ -131,50 +134,188 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {
   
 };
 
+typedef struct {
+  EFI_ACPI_DMAR_HEADER DmarHeader;
+  //
+  // VTd engine 2 - all rest
+  //
+  EFI_ACPI_DMAR_DRHD_HEADERDrhd2;
+} MY_VTD_INFO_NO_IGD_PPI;
+
+MY_VTD_INFO_NO_IGD_PPI  mPlatformVTdNoIgdSample = {
+  { // DmarHeader
+{ // Header
+  EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,
+  sizeof(MY_VTD_INFO_NO_IGD_PPI),
+  EFI_ACPI_DMAR_REVISION,
+},
+0x26, // HostAddressWidth
+  },
+
+  { // Drhd2
+{ // Header
+  EFI_ACPI_DMAR_TYPE_DRHD,
+  sizeof(EFI_ACPI_DMAR_DRHD_HEADER)
+},
+EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags
+0, // Reserved
+0, // SegmentNumber
+0xFED91000 // RegisterBaseAddress -- TO BE PATCHED
+  },
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDesc = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  ,
+  
+};
+
 /**
-  Patch Graphic UMA address in RMRR and base address.
+  Initialize VTd register.
 **/
 VOID
-PatchDmar (
+InitDmar (
   VOID
   )
 {
   UINT32  MchBar;
-  UINT16  IgdMode;
-  UINT16  GttMode;
-  UINT32  IgdMemSize;
-  UINT32  GttMemSize;
-
-  ///
-  /// Calculate IGD memsize
-  ///
-  IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & 
B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;
-  if (IgdMode < 0xF0) {
-IgdMemSize = IgdMode * 32 * (1024) * (1024);
+
+  DEBUG ((DEBUG_INFO, "InitDmar\n"));
+
+  MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;
+  PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED1 | BIT0);
+  DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar));
+
+  MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, 
(UINT32)mPlatformVTdSample.Drhd2.RegisterBaseAddress | 1);
+  DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + 
R_SA_MCHBAR_VTD2_OFFSET;
+}
+
+/**
+  Patch Graphic UMA address in RMRR and base address.
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+PatchDmar (
+  VOID
+  )
+{
+  UINT32  MchBar;
+  UINT16  IgdMode;
+  UINT16  GttMode;
+  UINT32  IgdMemSize;
+  UINT32  GttMemSize;
+  MY_VTD_INFO_PPI *PlatformVTdSample;
+  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdInfoSampleDesc;
+  MY_VTD_INFO_NO_IGD_PPI  *PlatformVTdNoIgdSample;
+  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdNoIgdInfoSampleDesc;
+
+  DEBUG ((DEBUG_INFO, "PatchDmar\n"));
+
+  if (PciRead16 (PCI_LIB_ADDRESS(0, 2, 0, 0)) != 0x) {
+PlatformVTdSample = AllocateCopyPool (sizeof(MY_VTD_INFO_PPI), 
);
+ASSERT(PlatformVTdSample != NULL);
+PlatformVTdInfoSampleDesc = AllocateCopyPool 
(sizeof(EFI_PEI_PPI_DESCRIPTOR), );
+ASSERT(PlatformVTdInfoSampleDesc != NULL);
+PlatformVTdInfoSampleDesc->Ppi = PlatformVTdSample;
+
+///
+/// Calculate IGD memsize
+///
+IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & 
B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;
+if (IgdMode < 0xF0) {
+  IgdMemSize = IgdMode * 32 * (1024) * (1024);
+} else {
+  IgdMemSize = 4 * (IgdMode - 0xF0 + 1) * (1024) * (1024);
+}
+
+///
+/// Calculate GTT mem size
+///
+GttMe

[edk2] [PATCH V3 0/2] IntelSiliconPkg: Add Pre-Memory DMA protection in PEI

[Jiewen Yao]

 V3 =
Address feedback from Star Zeng.
1) update the function comments of InitDmar()
2) update the function comments of SiliconInitializedPpiNotifyCallback()
3) remove duplicated BAR debug message.
4) fix the size field in the mPlatformVTdNoIgdSample structure.

 V2 =
Minor enhancement:
Replace IsDmaProtectionEnabled() by GetDmaProtectionEnabledEngineMask(),
for better code management.

 V1 =
This series patch adds Pre-Memory DMA protection in PEI.
The purpose is to make sure when the system memory is initialized, the DMA
protection takes effect immediately.

The IntelVTdPmrPei driver is updated to remove the global variable and
add VTD_INFO_PPI notification.

The VTdInfoSample driver is updated to install the initial
VTD_INFO_PPI before memory init, and add more content after memory init
by reinstalling VTD_INFO_PPI.

This patch is validated on one Intel Client kabylake platform.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>

Jiewen Yao (2):
  IntelSiliconPkg/VtdPmrPei: Add premem support.
  IntelSiliconPkg/VtdPeiSample: Add premem support.

 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c 
   | 580 ++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c   
   | 130 ++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
   | 846 +++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.h
   |  93 +++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf  
   |  11 +-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c
   | 293 +++
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c 
  | 234 +-
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
 |   2 +-
 8 files changed, 1557 insertions(+), 632 deletions(-)
 create mode 100644 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c
 create mode 100644 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c

-- 
2.7.4.windows.1

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[edk2] [PATCH V2 2/2] IntelSiliconPkg/VtdPeiSample: Add premem support.

[Jiewen Yao]

Before memory is ready, this sample produces one VTd engine.
After memory and silicon is initialized, this sample produces
both IGD VTd engine and all-rest VTd engine by reinstall the
FV_INFO_PPI.

This update is to demonstrate how to support pre-mem VTd usage.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c 
  | 234 +---
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
 |   2 +-
 2 files changed, 202 insertions(+), 34 deletions(-)

diff --git 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
index 6267da7..921daef 100644
--- 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
+++ 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define R_SA_MCHBAR   (0x48)
 #define R_SA_GGC  (0x50)
@@ -33,6 +34,8 @@
 #define R_SA_MCHBAR_VTD1_OFFSET  0x5400  ///< HW UNIT for IGD
 #define R_SA_MCHBAR_VTD2_OFFSET  0x5410  ///< HW UNIT for all other - PEG, 
USB, SATA etc
 
+EFI_GUID gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 
0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}};
+
 typedef struct {
   EFI_ACPI_DMAR_HEADER DmarHeader;
   //
@@ -131,50 +134,190 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {
   
 };
 
+typedef struct {
+  EFI_ACPI_DMAR_HEADER DmarHeader;
+  //
+  // VTd engine 2 - all rest
+  //
+  EFI_ACPI_DMAR_DRHD_HEADERDrhd2;
+} MY_VTD_INFO_NO_IGD_PPI;
+
+MY_VTD_INFO_NO_IGD_PPI  mPlatformVTdNoIgdSample = {
+  { // DmarHeader
+{ // Header
+  EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,
+  sizeof(MY_VTD_INFO_PPI),
+  EFI_ACPI_DMAR_REVISION,
+},
+0x26, // HostAddressWidth
+  },
+
+  { // Drhd2
+{ // Header
+  EFI_ACPI_DMAR_TYPE_DRHD,
+  sizeof(EFI_ACPI_DMAR_DRHD_HEADER)
+},
+EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags
+0, // Reserved
+0, // SegmentNumber
+0xFED91000 // RegisterBaseAddress -- TO BE PATCHED
+  },
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDesc = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  ,
+  
+};
+
 /**
   Patch Graphic UMA address in RMRR and base address.
 **/
 VOID
-PatchDmar (
+InitDmar (
   VOID
   )
 {
   UINT32  MchBar;
-  UINT16  IgdMode;
-  UINT16  GttMode;
-  UINT32  IgdMemSize;
-  UINT32  GttMemSize;
-
-  ///
-  /// Calculate IGD memsize
-  ///
-  IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & 
B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;
-  if (IgdMode < 0xF0) {
-IgdMemSize = IgdMode * 32 * (1024) * (1024);
+
+  DEBUG ((DEBUG_INFO, "InitDmar\n"));
+
+  MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;
+  DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar));
+
+  PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED1 | BIT0);
+  DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar));
+
+  DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + 
R_SA_MCHBAR_VTD2_OFFSET) &~1)));
+  MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, 
(UINT32)mPlatformVTdSample.Drhd2.RegisterBaseAddress | 1);
+  DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + 
R_SA_MCHBAR_VTD2_OFFSET) &~1)));
+}
+
+/**
+  Patch Graphic UMA address in RMRR and base address.
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+PatchDmar (
+  VOID
+  )
+{
+  UINT32  MchBar;
+  UINT16  IgdMode;
+  UINT16  GttMode;
+  UINT32  IgdMemSize;
+  UINT32  GttMemSize;
+  MY_VTD_INFO_PPI *PlatformVTdSample;
+  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdInfoSampleDesc;
+  MY_VTD_INFO_NO_IGD_PPI  *PlatformVTdNoIgdSample;
+  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdNoIgdInfoSampleDesc;
+
+  DEBUG ((DEBUG_INFO, "PatchDmar\n"));
+
+  if (PciRead16 (PCI_LIB_ADDRESS(0, 2, 0, 0)) != 0x) {
+PlatformVTdSample = AllocateCopyPool (sizeof(MY_VTD_INFO_PPI), 
);
+ASSERT(PlatformVTdSample != NULL);
+PlatformVTdInfoSampleDesc = AllocateCopyPool 
(sizeof(EFI_PEI_PPI_DESCRIPTOR), );
+ASSERT(PlatformVTdInfoSampleDesc != NULL);
+PlatformVTdInfoSampleDesc->Ppi = PlatformVTdSample;
+
+///
+/// Calculate IGD memsize
+///
+IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & 
B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;
+if (IgdMode < 0xF0) {
+  IgdMemSize = IgdMode * 32 * (1024) * (1024);

[edk2] [PATCH V2 0/2] IntelSiliconPkg: Add Pre-Memory DMA protection in PEI

[Jiewen Yao]

 V2 =
Minor enhancement:
Replace IsDmaProtectionEnabled() by GetDmaProtectionEnabledEngineMask(),
for better code management.

 V1 =
This series patch adds Pre-Memory DMA protection in PEI.
The purpose is to make sure when the system memory is initialized, the DMA
protection takes effect immediately.

The IntelVTdPmrPei driver is updated to remove the global variable and
add VTD_INFO_PPI notification.

The VTdInfoSample driver is updated to install the initial
VTD_INFO_PPI before memory init, and add more content after memory init
by reinstalling VTD_INFO_PPI.

This patch is validated on one Intel Client kabylake platform.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>

Jiewen Yao (2):
  IntelSiliconPkg/VtdPmrPei: Add premem support.
  IntelSiliconPkg/VtdPeiSample: Add premem support.

 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c 
   | 580 ++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c   
   | 130 ++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
   | 846 +++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.h
   |  93 +++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf  
   |  11 +-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c
   | 293 +++
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c 
  | 234 +-
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
 |   2 +-
 8 files changed, 1558 insertions(+), 631 deletions(-)
 create mode 100644 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c
 create mode 100644 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c

-- 
2.7.4.windows.1

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[edk2] [PATCH V2 1/2] IntelSiliconPkg/VtdPmrPei: Add premem support.

[Jiewen Yao]

Remove memory discovered dependency to support both premem
VTD_INFO_PPI and postmem VTD_INFO_PPI.

If VTD_INFO_PPI is installed before memory is ready, this
driver protects all memory region.
If VTD_INFO_PPI is installed or reinstalled after memory
is ready, this driver allocates DMA buffer and protect rest.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c| 580 
++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c  | 130 ++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c   | 846 
+++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.h   |  93 +++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf |  11 +-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c   | 293 +++
 6 files changed, 1356 insertions(+), 597 deletions(-)

diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c 
b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c
new file mode 100644
index 000..891efa6
--- /dev/null
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c
@@ -0,0 +1,580 @@
+/** @file
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "IntelVTdPmrPei.h"
+
+/**
+  Dump DMAR DeviceScopeEntry.
+
+  @param[in]  DmarDeviceScopeEntry  DMAR DeviceScopeEntry
+**/
+VOID
+DumpDmarDeviceScopeEntry (
+  IN EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DmarDeviceScopeEntry
+  )
+{
+  UINTN   PciPathNumber;
+  UINTN   PciPathIndex;
+  EFI_ACPI_DMAR_PCI_PATH  *PciPath;
+
+  if (DmarDeviceScopeEntry == NULL) {
+return;
+  }
+
+  DEBUG ((DEBUG_INFO,
+"
*\n"
+));
+  DEBUG ((DEBUG_INFO,
+"*   DMA-Remapping Device Scope Entry Structure
  *\n"
+));
+  DEBUG ((DEBUG_INFO,
+"
*\n"
+));
+  DEBUG ((DEBUG_INFO,
+(sizeof(UINTN) == sizeof(UINT64)) ?
+"DMAR Device Scope Entry address .. 0x%016lx\n" :
+"DMAR Device Scope Entry address .. 0x%08x\n",
+DmarDeviceScopeEntry
+));
+  DEBUG ((DEBUG_INFO,
+"  Device Scope Entry Type  0x%02x\n",
+DmarDeviceScopeEntry->Type
+));
+  switch (DmarDeviceScopeEntry->Type) {
+  case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT:
+DEBUG ((DEBUG_INFO,
+  "PCI Endpoint Device\n"
+  ));
+break;
+  case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE:
+DEBUG ((DEBUG_INFO,
+  "PCI Sub-hierachy\n"
+  ));
+break;
+  default:
+break;
+  }
+  DEBUG ((DEBUG_INFO,
+"  Length . 0x%02x\n",
+DmarDeviceScopeEntry->Length
+));
+  DEBUG ((DEBUG_INFO,
+"  Enumeration ID . 0x%02x\n",
+DmarDeviceScopeEntry->EnumerationId
+));
+  DEBUG ((DEBUG_INFO,
+"  Starting Bus Number  0x%02x\n",
+DmarDeviceScopeEntry->StartBusNumber
+));
+
+  PciPathNumber = (DmarDeviceScopeEntry->Length - 
sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER)) / 
sizeof(EFI_ACPI_DMAR_PCI_PATH);
+  PciPath = (EFI_ACPI_DMAR_PCI_PATH *)(DmarDeviceScopeEntry + 1);
+  for (PciPathIndex = 0; PciPathIndex < PciPathNumber; PciPathIndex++) {
+DEBUG ((DEBUG_INFO,
+  "  Device . 0x%02x\n",
+  PciPath[PciPathIndex].Device
+  ));
+DEBUG ((DEBUG_INFO,
+  "  Function ... 0x%02x\n",
+  PciPath[PciPathIndex].Function
+  ));
+  }
+
+  DEBUG ((DEBUG_INFO,
+"
*\n\n"
+));
+
+  return;
+}
+
+/**
+  Dump DMAR RMRR table.
+
+  @param[in]  Rmrr  DMAR RMRR table
+**/
+VOID
+DumpDmarRmrr (
+  IN EFI_ACPI_DMAR_RMRR_HEADER *Rmrr
+  )
+{
+  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER   *DmarDeviceScopeEntry;
+  INTNRm

[edk2] [PATCH] IntelSiliconPkg/VTdDxe: return unsupported for exceptionlist

[Jiewen Yao]

Since the exception list is not a recommended way, we returns
EFI_UNSUPPORTED in the sample code.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c | 5 
+++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c
index 3587fa3..e522db0 100644
--- a/IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c
+++ b/IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c
@@ -359,6 +359,7 @@ PlatformVTdGetExceptionDeviceList (
   // Uncomment to take affect and comment the sample codes for device scope
   // based exception list.
   //
+  /*
   *DeviceInfo = AllocateZeroPool (sizeof(mExceptionPciDeviceIdList));
   if (*DeviceInfo == NULL) {
 return EFI_OUT_OF_RESOURCES;
@@ -366,8 +367,8 @@ PlatformVTdGetExceptionDeviceList (
   CopyMem (*DeviceInfo, mExceptionPciDeviceIdList, 
sizeof(mExceptionPciDeviceIdList));
 
   *DeviceInfoCount = ARRAY_SIZE(mExceptionPciDeviceIdList);
-
-  return EFI_SUCCESS;
+  */
+  return EFI_UNSUPPORTED;
 }
 
 EDKII_PLATFORM_VTD_POLICY_PROTOCOL  mPlatformVTdSample = {
-- 
2.7.4.windows.1

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[edk2] [PATCH] IntelSiliconPkg/VTdDxe: Change EBS Event TPL to CALLBACK.

[Jiewen Yao]

Change ExitBootServices TPL to CALLBACK, so that a device
can disable BME before IOMMU grants access right.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c 
b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c
index f5de01f..4a4d82e 100644
--- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c
@@ -483,7 +483,7 @@ InitializeDmaProtection (
 
   Status = gBS->CreateEventEx (
   EVT_NOTIFY_SIGNAL,
-  TPL_NOTIFY,
+  TPL_CALLBACK,
   OnExitBootServices,
   NULL,
   ,
@@ -492,7 +492,7 @@ InitializeDmaProtection (
   ASSERT_EFI_ERROR (Status);
 
   Status = EfiCreateEventLegacyBootEx (
- TPL_NOTIFY,
+ TPL_CALLBACK,
  OnLegacyBoot,
  NULL,
  
-- 
2.7.4.windows.1

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[edk2] [PATCH 0/2] IntelSiliconPkg: Add Pre-Memory DMA protection in PEI

[Jiewen Yao]

This series patch adds Pre-Memory DMA protection in PEI.
The purpose is to make sure when the system memory is initialized, the DMA
protection takes effect immediately.

The IntelVTdPmrPei driver is updated to remove the global variable and
add VTD_INFO_PPI notification.

The VTdInfoSample driver is updated to install the initial
VTD_INFO_PPI before memory init, and add more content after memory init
by reinstalling VTD_INFO_PPI.

This patch is validated on one Intel Client kabylake platform.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>

Jiewen Yao (2):
  IntelSiliconPkg/VtdPmrPei: Add premem support.
  IntelSiliconPkg/VtdPeiSample: Add premem support.

 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c 
   | 580 ++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c   
   | 130 ++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
   | 846 +++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.h
   |  93 +++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf  
   |  11 +-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c
   | 293 +++
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c 
  | 234 +-
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
 |   2 +-
 8 files changed, 1558 insertions(+), 631 deletions(-)
 create mode 100644 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c
 create mode 100644 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c

-- 
2.7.4.windows.1

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[edk2] [PATCH 1/2] IntelSiliconPkg/VtdPmrPei: Add premem support.

[Jiewen Yao]

Remove memory discovered dependency to support both premem
VTD_INFO_PPI and postmem VTD_INFO_PPI.

If VTD_INFO_PPI is installed before memory is ready, this
driver protects all memory region.
If VTD_INFO_PPI is installed or reinstalled after memory
is ready, this driver allocates DMA buffer and protect rest.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c| 580 
++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c  | 130 ++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c   | 846 
+++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.h   |  93 +++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf |  11 +-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c   | 293 +++
 6 files changed, 1356 insertions(+), 597 deletions(-)

diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c 
b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c
new file mode 100644
index 000..891efa6
--- /dev/null
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c
@@ -0,0 +1,580 @@
+/** @file
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "IntelVTdPmrPei.h"
+
+/**
+  Dump DMAR DeviceScopeEntry.
+
+  @param[in]  DmarDeviceScopeEntry  DMAR DeviceScopeEntry
+**/
+VOID
+DumpDmarDeviceScopeEntry (
+  IN EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DmarDeviceScopeEntry
+  )
+{
+  UINTN   PciPathNumber;
+  UINTN   PciPathIndex;
+  EFI_ACPI_DMAR_PCI_PATH  *PciPath;
+
+  if (DmarDeviceScopeEntry == NULL) {
+return;
+  }
+
+  DEBUG ((DEBUG_INFO,
+"
*\n"
+));
+  DEBUG ((DEBUG_INFO,
+"*   DMA-Remapping Device Scope Entry Structure
  *\n"
+));
+  DEBUG ((DEBUG_INFO,
+"
*\n"
+));
+  DEBUG ((DEBUG_INFO,
+(sizeof(UINTN) == sizeof(UINT64)) ?
+"DMAR Device Scope Entry address .. 0x%016lx\n" :
+"DMAR Device Scope Entry address .. 0x%08x\n",
+DmarDeviceScopeEntry
+));
+  DEBUG ((DEBUG_INFO,
+"  Device Scope Entry Type  0x%02x\n",
+DmarDeviceScopeEntry->Type
+));
+  switch (DmarDeviceScopeEntry->Type) {
+  case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT:
+DEBUG ((DEBUG_INFO,
+  "PCI Endpoint Device\n"
+  ));
+break;
+  case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE:
+DEBUG ((DEBUG_INFO,
+  "PCI Sub-hierachy\n"
+  ));
+break;
+  default:
+break;
+  }
+  DEBUG ((DEBUG_INFO,
+"  Length . 0x%02x\n",
+DmarDeviceScopeEntry->Length
+));
+  DEBUG ((DEBUG_INFO,
+"  Enumeration ID . 0x%02x\n",
+DmarDeviceScopeEntry->EnumerationId
+));
+  DEBUG ((DEBUG_INFO,
+"  Starting Bus Number  0x%02x\n",
+DmarDeviceScopeEntry->StartBusNumber
+));
+
+  PciPathNumber = (DmarDeviceScopeEntry->Length - 
sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER)) / 
sizeof(EFI_ACPI_DMAR_PCI_PATH);
+  PciPath = (EFI_ACPI_DMAR_PCI_PATH *)(DmarDeviceScopeEntry + 1);
+  for (PciPathIndex = 0; PciPathIndex < PciPathNumber; PciPathIndex++) {
+DEBUG ((DEBUG_INFO,
+  "  Device . 0x%02x\n",
+  PciPath[PciPathIndex].Device
+  ));
+DEBUG ((DEBUG_INFO,
+  "  Function ... 0x%02x\n",
+  PciPath[PciPathIndex].Function
+  ));
+  }
+
+  DEBUG ((DEBUG_INFO,
+"
*\n\n"
+));
+
+  return;
+}
+
+/**
+  Dump DMAR RMRR table.
+
+  @param[in]  Rmrr  DMAR RMRR table
+**/
+VOID
+DumpDmarRmrr (
+  IN EFI_ACPI_DMAR_RMRR_HEADER *Rmrr
+  )
+{
+  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER   *DmarDeviceScopeEntry;
+  INTNRm

[edk2] [PATCH 2/2] IntelSiliconPkg/VtdPeiSample: Add premem support.

[Jiewen Yao]

Before memory is ready, this sample produces one VTd engine.
After memory and silicon is initialized, this sample produces
both IGD VTd engine and all-rest VTd engine by reinstall the
FV_INFO_PPI.

This update is to demonstrate how to support pre-mem VTd usage.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c 
  | 234 +---
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
 |   2 +-
 2 files changed, 202 insertions(+), 34 deletions(-)

diff --git 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
index 6267da7..921daef 100644
--- 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
+++ 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define R_SA_MCHBAR   (0x48)
 #define R_SA_GGC  (0x50)
@@ -33,6 +34,8 @@
 #define R_SA_MCHBAR_VTD1_OFFSET  0x5400  ///< HW UNIT for IGD
 #define R_SA_MCHBAR_VTD2_OFFSET  0x5410  ///< HW UNIT for all other - PEG, 
USB, SATA etc
 
+EFI_GUID gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 
0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}};
+
 typedef struct {
   EFI_ACPI_DMAR_HEADER DmarHeader;
   //
@@ -131,50 +134,190 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {
   
 };
 
+typedef struct {
+  EFI_ACPI_DMAR_HEADER DmarHeader;
+  //
+  // VTd engine 2 - all rest
+  //
+  EFI_ACPI_DMAR_DRHD_HEADERDrhd2;
+} MY_VTD_INFO_NO_IGD_PPI;
+
+MY_VTD_INFO_NO_IGD_PPI  mPlatformVTdNoIgdSample = {
+  { // DmarHeader
+{ // Header
+  EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,
+  sizeof(MY_VTD_INFO_PPI),
+  EFI_ACPI_DMAR_REVISION,
+},
+0x26, // HostAddressWidth
+  },
+
+  { // Drhd2
+{ // Header
+  EFI_ACPI_DMAR_TYPE_DRHD,
+  sizeof(EFI_ACPI_DMAR_DRHD_HEADER)
+},
+EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags
+0, // Reserved
+0, // SegmentNumber
+0xFED91000 // RegisterBaseAddress -- TO BE PATCHED
+  },
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDesc = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  ,
+  
+};
+
 /**
   Patch Graphic UMA address in RMRR and base address.
 **/
 VOID
-PatchDmar (
+InitDmar (
   VOID
   )
 {
   UINT32  MchBar;
-  UINT16  IgdMode;
-  UINT16  GttMode;
-  UINT32  IgdMemSize;
-  UINT32  GttMemSize;
-
-  ///
-  /// Calculate IGD memsize
-  ///
-  IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & 
B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;
-  if (IgdMode < 0xF0) {
-IgdMemSize = IgdMode * 32 * (1024) * (1024);
+
+  DEBUG ((DEBUG_INFO, "InitDmar\n"));
+
+  MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;
+  DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar));
+
+  PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED1 | BIT0);
+  DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar));
+
+  DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + 
R_SA_MCHBAR_VTD2_OFFSET) &~1)));
+  MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, 
(UINT32)mPlatformVTdSample.Drhd2.RegisterBaseAddress | 1);
+  DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + 
R_SA_MCHBAR_VTD2_OFFSET) &~1)));
+}
+
+/**
+  Patch Graphic UMA address in RMRR and base address.
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+PatchDmar (
+  VOID
+  )
+{
+  UINT32  MchBar;
+  UINT16  IgdMode;
+  UINT16  GttMode;
+  UINT32  IgdMemSize;
+  UINT32  GttMemSize;
+  MY_VTD_INFO_PPI *PlatformVTdSample;
+  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdInfoSampleDesc;
+  MY_VTD_INFO_NO_IGD_PPI  *PlatformVTdNoIgdSample;
+  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdNoIgdInfoSampleDesc;
+
+  DEBUG ((DEBUG_INFO, "PatchDmar\n"));
+
+  if (PciRead16 (PCI_LIB_ADDRESS(0, 2, 0, 0)) != 0x) {
+PlatformVTdSample = AllocateCopyPool (sizeof(MY_VTD_INFO_PPI), 
);
+ASSERT(PlatformVTdSample != NULL);
+PlatformVTdInfoSampleDesc = AllocateCopyPool 
(sizeof(EFI_PEI_PPI_DESCRIPTOR), );
+ASSERT(PlatformVTdInfoSampleDesc != NULL);
+PlatformVTdInfoSampleDesc->Ppi = PlatformVTdSample;
+
+///
+/// Calculate IGD memsize
+///
+IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & 
B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;
+if (IgdMode < 0xF0) {
+  IgdMemSize = IgdMode * 32 * (1024) * (1024);

[edk2] [PATCH 2/2] IntelSiliconPkg/VtdPeiSample: Add premem support.

[Jiewen Yao]

Before memory is ready, this sample produces one VTd engine.
After memory and silicon is initialized, this sample produces
both IGD VTd engine and all-rest VTd engine by reinstall the
FV_INFO_PPI.

This update is to demonstrate how to support pre-mem VTd usage.

Cc: Zeng Star <zeng.s...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c 
  | 234 +---
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
 |   2 +-
 2 files changed, 202 insertions(+), 34 deletions(-)

diff --git 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
index 6267da7..921daef 100644
--- 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
+++ 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define R_SA_MCHBAR   (0x48)
 #define R_SA_GGC  (0x50)
@@ -33,6 +34,8 @@
 #define R_SA_MCHBAR_VTD1_OFFSET  0x5400  ///< HW UNIT for IGD
 #define R_SA_MCHBAR_VTD2_OFFSET  0x5410  ///< HW UNIT for all other - PEG, 
USB, SATA etc
 
+EFI_GUID gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 
0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}};
+
 typedef struct {
   EFI_ACPI_DMAR_HEADER DmarHeader;
   //
@@ -131,50 +134,190 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {
   
 };
 
+typedef struct {
+  EFI_ACPI_DMAR_HEADER DmarHeader;
+  //
+  // VTd engine 2 - all rest
+  //
+  EFI_ACPI_DMAR_DRHD_HEADERDrhd2;
+} MY_VTD_INFO_NO_IGD_PPI;
+
+MY_VTD_INFO_NO_IGD_PPI  mPlatformVTdNoIgdSample = {
+  { // DmarHeader
+{ // Header
+  EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,
+  sizeof(MY_VTD_INFO_PPI),
+  EFI_ACPI_DMAR_REVISION,
+},
+0x26, // HostAddressWidth
+  },
+
+  { // Drhd2
+{ // Header
+  EFI_ACPI_DMAR_TYPE_DRHD,
+  sizeof(EFI_ACPI_DMAR_DRHD_HEADER)
+},
+EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags
+0, // Reserved
+0, // SegmentNumber
+0xFED91000 // RegisterBaseAddress -- TO BE PATCHED
+  },
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDesc = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  ,
+  
+};
+
 /**
   Patch Graphic UMA address in RMRR and base address.
 **/
 VOID
-PatchDmar (
+InitDmar (
   VOID
   )
 {
   UINT32  MchBar;
-  UINT16  IgdMode;
-  UINT16  GttMode;
-  UINT32  IgdMemSize;
-  UINT32  GttMemSize;
-
-  ///
-  /// Calculate IGD memsize
-  ///
-  IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & 
B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;
-  if (IgdMode < 0xF0) {
-IgdMemSize = IgdMode * 32 * (1024) * (1024);
+
+  DEBUG ((DEBUG_INFO, "InitDmar\n"));
+
+  MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;
+  DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar));
+
+  PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED1 | BIT0);
+  DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar));
+
+  DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + 
R_SA_MCHBAR_VTD2_OFFSET) &~1)));
+  MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, 
(UINT32)mPlatformVTdSample.Drhd2.RegisterBaseAddress | 1);
+  DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + 
R_SA_MCHBAR_VTD2_OFFSET) &~1)));
+}
+
+/**
+  Patch Graphic UMA address in RMRR and base address.
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+PatchDmar (
+  VOID
+  )
+{
+  UINT32  MchBar;
+  UINT16  IgdMode;
+  UINT16  GttMode;
+  UINT32  IgdMemSize;
+  UINT32  GttMemSize;
+  MY_VTD_INFO_PPI *PlatformVTdSample;
+  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdInfoSampleDesc;
+  MY_VTD_INFO_NO_IGD_PPI  *PlatformVTdNoIgdSample;
+  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdNoIgdInfoSampleDesc;
+
+  DEBUG ((DEBUG_INFO, "PatchDmar\n"));
+
+  if (PciRead16 (PCI_LIB_ADDRESS(0, 2, 0, 0)) != 0x) {
+PlatformVTdSample = AllocateCopyPool (sizeof(MY_VTD_INFO_PPI), 
);
+ASSERT(PlatformVTdSample != NULL);
+PlatformVTdInfoSampleDesc = AllocateCopyPool 
(sizeof(EFI_PEI_PPI_DESCRIPTOR), );
+ASSERT(PlatformVTdInfoSampleDesc != NULL);
+PlatformVTdInfoSampleDesc->Ppi = PlatformVTdSample;
+
+///
+/// Calculate IGD memsize
+///
+IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & 
B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;
+if (IgdMode < 0xF0) {
+  IgdMemSize = IgdMode * 32 * (1024) * (1024);

[edk2] [PATCH] IntelSiliconPkg/VtdInfoSample: Fix IGD RMRR memory.

[Jiewen Yao]

Fix a calculation problem in IGD RMRR memory.

Cc: Zeng Star <zeng.s...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c 
| 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
index 08a4db3..6267da7 100644
--- 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
+++ 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -159,7 +159,7 @@ PatchDmar (
   /// Calculate GTT mem size
   ///
   GttMemSize = 0;
-  GttMode = PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC) & 
B_SKL_SA_GGC_GGMS_MASK) >> N_SKL_SA_GGC_GGMS_OFFSET;
+  GttMode = (PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & 
B_SKL_SA_GGC_GGMS_MASK) >> N_SKL_SA_GGC_GGMS_OFFSET;
   if (GttMode <= V_SKL_SA_GGC_GGMS_8MB) {
 GttMemSize = (1 << GttMode) * (1024) * (1024);
   }
-- 
2.7.4.windows.1

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[edk2] [PATCH 3/3] IntelSiliconPkg/VTdPmrPei: Add EndOfPei callback for S3

[Jiewen Yao]

In S3 resume, before system transfer to waking vector,
the VTdPrm need turn off VTd protection based upon VTdPolicy.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c   | 59 
+++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf |  1 +
 2 files changed, 58 insertions(+), 2 deletions(-)

diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c 
b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
index e768274..3fe6d65 100644
--- a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
@@ -24,16 +24,18 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "IntelVTdPmrPei.h"
 
 #define  TOTAL_DMA_BUFFER_SIZESIZE_4MB
+#define  TOTAL_DMA_BUFFER_SIZE_S3 SIZE_1MB
 
 EFI_ACPI_DMAR_HEADER  *mAcpiDmarTable;
 VTD_INFO  *mVTdInfo;
 UINT64mEngineMask;
 UINTN mDmaBufferBase;
-UINTN mDmaBufferSize = TOTAL_DMA_BUFFER_SIZE;
+UINTN mDmaBufferSize;
 UINTN mDmaBufferCurrentTop;
 UINTN mDmaBufferCurrentBottom;
 
@@ -544,6 +546,7 @@ InitDmaProtection (
   }
   ASSERT (DmaBufferSize == ALIGN_VALUE(DmaBufferSize, MemoryAlignment));
   *DmaBufferBase = (UINTN)AllocateAlignedPages 
(EFI_SIZE_TO_PAGES(DmaBufferSize), MemoryAlignment);
+  ASSERT (*DmaBufferBase != 0);
   if (*DmaBufferBase == 0) {
 DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n"));
 return EFI_OUT_OF_RESOURCES;
@@ -1105,6 +1108,41 @@ ParseDmarAcpiTableRmrr (
 }
 
 /**
+  This function handles S3 resume task at the end of PEI
+
+  @param[in] PeiServicesPointer to PEI Services Table.
+  @param[in] NotifyDesc Pointer to the descriptor for the Notification 
event that
+caused this function to execute.
+  @param[in] PpiPointer to the PPI data associated with this 
function.
+
+  @retval EFI_STATUSAlways return EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+S3EndOfPeiNotify(
+  IN EFI_PEI_SERVICES  **PeiServices,
+  IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
+  IN VOID  *Ppi
+  )
+{
+  UINT64  EngineMask;
+
+  DEBUG((DEBUG_INFO, "VTdPmr S3EndOfPeiNotify\n"));
+
+  if ((PcdGet8(PcdVTdPolicyPropertyMask) & BIT1) == 0) {
+EngineMask = LShiftU64 (1, mVTdInfo->VTdEngineCount) - 1;
+DisableDmaProtection (EngineMask);
+  }
+  return EFI_SUCCESS;
+}
+
+EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc = {
+  (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | 
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  ,
+  S3EndOfPeiNotify
+};
+
+/**
   Initializes the Intel VTd PMR PEIM.
 
   @param  FileHandle  Handle of the file being invoked.
@@ -1122,11 +1160,14 @@ IntelVTdPmrInitialize (
   )
 {
   EFI_STATUS  Status;
+  EFI_BOOT_MODE   BootMode;
 
   if ((PcdGet8(PcdVTdPolicyPropertyMask) & BIT0) == 0) {
 return EFI_UNSUPPORTED;
   }
 
+  PeiServicesGetBootMode ();
+
   Status = PeiServicesLocatePpi (
  ,
  0,
@@ -1150,6 +1191,13 @@ IntelVTdPmrInitialize (
   //
   ParseDmarAcpiTableRmrr ();
 
+  if (BootMode == BOOT_ON_S3_RESUME) {
+mDmaBufferSize = TOTAL_DMA_BUFFER_SIZE_S3;
+  } else {
+mDmaBufferSize = TOTAL_DMA_BUFFER_SIZE;
+  }
+  DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", mDmaBufferSize));
+
   //
   // Find a pre-memory in resource hob as DMA buffer
   // Mark PEI memory to be DMA protected.
@@ -1160,7 +1208,6 @@ IntelVTdPmrInitialize (
   }
 
   DEBUG ((DEBUG_INFO, " DmaBufferBase : 0x%x\n", mDmaBufferBase));
-  DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", mDmaBufferSize));
 
   mDmaBufferCurrentTop = mDmaBufferBase + mDmaBufferSize;
   mDmaBufferCurrentBottom = mDmaBufferBase;
@@ -1171,6 +1218,14 @@ IntelVTdPmrInitialize (
   Status = PeiServicesInstallPpi ();
   ASSERT_EFI_ERROR(Status);
 
+  //
+  // Register EndOfPei Notify for S3 to run FSP NotifyPhase
+  //
+  if (BootMode == BOOT_ON_S3_RESUME) {
+Status = PeiServicesNotifyPpi ();
+ASSERT_EFI_ERROR (Status);
+  }
+
   return Status;
 }
 
diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf 
b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
index 86cd7d1..e1aa980 100644
--- a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
@@ -46,6 +46,7 @@
 [Ppis]
   gEdkiiIoMmuPpiGuid## PRODUCES
   gEdkiiVTdInfoPpiGuid  ## CONSUMES
+  gEfiEndOfPeiSignalPpiGuid ## CONSUMES
 
 [Pcd]
   gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask   ## CONSU

[edk2] [PATCH 2/3] IntelSiliconPkg/dec: Clarify VTdPolicy.

[Jiewen Yao]

Clarify the VTdPolicy is for both PEI and DXE.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelSiliconPkg.dec | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec 
b/IntelSiliconPkg/IntelSiliconPkg.dec
index 941380a..b88630d 100644
--- a/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -48,8 +48,8 @@
   gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid|{ 0xa9, 0x2d, 
0x75, 0x56, 0x6b, 0xde, 0x95, 0x48, 0x88, 0x19, 0x19, 0x45, 0xb6, 0xb7, 0x6c, 
0x22 }|VOID*|0x0001
 
   ## The mask is used to control VTd behavior.
-  #  BIT0: Enable IOMMU during boot.
-  #  BIT1: Enable IOMMU on exit boot service.
+  #  BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. If 
VTD_INFO_PPI is installed in PEI.)
+  #  BIT1: Enable IOMMU when transfer control to OS (ExitBootService in normal 
boot. EndOfPEI in S3)
   # @Prompt The policy for VTd driver behavior.
   gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|1|UINT8|0x0002
 
-- 
2.7.4.windows.1

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[edk2] [PATCH 0/3] IntelVTd fix

[Jiewen Yao]

1) Make sure context cache in VTdDxe is flushed in every path.
2) Clarify VTdPolicy PCD usage for PEI and DXE.
3) Add EndOfPei callback in VTdPrmPei for S3 resume.

The patch is tested in Intel Kabylake platform.
Windows 10 boot and S3 resume success with VTd enabled.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>

Jiewen Yao (3):
  IntelSiliconPkg/VTdDxe: Clean up DXE flush memory.
  IntelSiliconPkg/dec: Clarify VTdPolicy.
  IntelSiliconPkg/VTdPmrPei: Add EndOfPei callback for S3

 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c|  9 ++-
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c  |  4 +-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c   | 59 
+++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf |  1 +
 IntelSiliconPkg/IntelSiliconPkg.dec   |  4 +-
 5 files changed, 69 insertions(+), 8 deletions(-)

-- 
2.7.4.windows.1

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[edk2] [PATCH 1/3] IntelSiliconPkg/VTdDxe: Clean up DXE flush memory.

[Jiewen Yao]

Make sure the context table are flush to memory.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c   | 9 +++--
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c | 4 ++--
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c 
b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
index ccecc95..cecb5d2 100644
--- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
@@ -124,7 +124,6 @@ CreateContextEntry (
   RootEntry->Bits.ContextTablePointerHi  = (UINT32) RShiftU64 
((UINT64)(UINTN)Buffer, 32);
   RootEntry->Bits.Present = 1;
   Buffer = (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (ContextPages);
-  FlushPageTableMemory (VtdIndex, (UINTN)RootEntry, sizeof(*RootEntry));
 }
 
 ContextEntryTable = (VTD_CONTEXT_ENTRY 
*)(UINTN)VTD_64BITS_ADDRESS(RootEntry->Bits.ContextTablePointerLo, 
RootEntry->Bits.ContextTablePointerHi) ;
@@ -143,9 +142,10 @@ CreateContextEntry (
   ContextEntry->Bits.AddressWidth = 0x2;
   break;
 }
-FlushPageTableMemory (VtdIndex, (UINTN)ContextEntry, 
sizeof(*ContextEntry));
   }
 
+  FlushPageTableMemory (VtdIndex, 
(UINTN)mVtdUnitInformation[VtdIndex].RootEntryTable, 
EFI_PAGES_TO_SIZE(EntryTablePages));
+
   return EFI_SUCCESS;
 }
 
@@ -196,6 +196,7 @@ CreateSecondLevelPagingEntryTable (
   DEBUG ((DEBUG_ERROR,"Could not Alloc LVL4 PT. \n"));
   return NULL;
 }
+FlushPageTableMemory (VtdIndex, (UINTN)SecondLevelPagingEntry, 
EFI_PAGES_TO_SIZE(1));
   }
 
   //
@@ -219,6 +220,7 @@ CreateSecondLevelPagingEntryTable (
 ASSERT(FALSE);
 return NULL;
   }
+  FlushPageTableMemory (VtdIndex, (UINTN)Lvl4PtEntry[Index4].Uint64, 
SIZE_4KB);
   SetSecondLevelPagingEntryAttribute ([Index4], 
EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE);
 }
 
@@ -239,6 +241,7 @@ CreateSecondLevelPagingEntryTable (
   ASSERT(FALSE);
   return NULL;
 }
+FlushPageTableMemory (VtdIndex, (UINTN)Lvl3PtEntry[Index3].Uint64, 
SIZE_4KB);
 SetSecondLevelPagingEntryAttribute ([Index3], 
EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE);
   }
 
@@ -542,6 +545,7 @@ GetSecondLevelPageTableEntry (
   *PageAttribute = PageNone;
   return NULL;
 }
+FlushPageTableMemory (VtdIndex, (UINTN)L4PageTable[Index4], SIZE_4KB);
 SetSecondLevelPagingEntryAttribute ((VTD_SECOND_LEVEL_PAGING_ENTRY 
*)[Index4], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE);
 FlushPageTableMemory (VtdIndex, (UINTN)[Index4], 
sizeof(L4PageTable[Index4]));
   }
@@ -555,6 +559,7 @@ GetSecondLevelPageTableEntry (
   *PageAttribute = PageNone;
   return NULL;
 }
+FlushPageTableMemory (VtdIndex, (UINTN)L3PageTable[Index3], SIZE_4KB);
 SetSecondLevelPagingEntryAttribute ((VTD_SECOND_LEVEL_PAGING_ENTRY 
*)[Index3], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE);
 FlushPageTableMemory (VtdIndex, (UINTN)[Index3], 
sizeof(L3PageTable[Index3]));
   }
diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c 
b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
index 68b25a7..0b3006a 100644
--- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
@@ -73,7 +73,6 @@ CreateExtContextEntry (
   ExtRootEntry->Bits.UpperContextTablePointerLo  = (UINT32) RShiftU64 
((UINT64)(UINTN)Buffer, 12) + 1;
   ExtRootEntry->Bits.UpperContextTablePointerHi  = (UINT32) RShiftU64 
(RShiftU64 ((UINT64)(UINTN)Buffer, 12) + 1, 20);
   ExtRootEntry->Bits.UpperPresent = 1;
-  FlushPageTableMemory (VtdIndex, (UINTN)ExtRootEntry, 
sizeof(*ExtRootEntry));
   Buffer = (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (ContextPages);
 }
 
@@ -93,9 +92,10 @@ CreateExtContextEntry (
   ExtContextEntry->Bits.AddressWidth = 0x2;
   break;
 }
-FlushPageTableMemory (VtdIndex, (UINTN)ExtContextEntry, 
sizeof(*ExtContextEntry));
   }
 
+  FlushPageTableMemory (VtdIndex, 
(UINTN)mVtdUnitInformation[VtdIndex].ExtRootEntryTable, 
EFI_PAGES_TO_SIZE(EntryTablePages));
+
   return EFI_SUCCESS;
 }
 
-- 
2.7.4.windows.1

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[edk2] [PATCH 1/3] IntelSiliconPkg/VTdInfoPpi: Let it follow DMAR table.

[Jiewen Yao]

We notice that there is real usage in PEI to show
the graphic output. As such we need report RMRR table
in PEI to let VTdPmrPei driver skip the IGD UMA region.

Now the VTD_INFO PPI uses the same DMAR data structure.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Include/Ppi/VtdInfo.h | 26 +++-
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/IntelSiliconPkg/Include/Ppi/VtdInfo.h 
b/IntelSiliconPkg/Include/Ppi/VtdInfo.h
index e8be63f..a0a6f9c 100644
--- a/IntelSiliconPkg/Include/Ppi/VtdInfo.h
+++ b/IntelSiliconPkg/Include/Ppi/VtdInfo.h
@@ -17,22 +17,26 @@
 #ifndef __VTD_INFO_PPI_H__
 #define __VTD_INFO_PPI_H__
 
+#include 
+#include 
+
 #define EDKII_VTD_INFO_PPI_GUID \
 { \
   0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x68, 
0x4a } \
 }
 
-typedef struct _EDKII_VTD_INFO_PPI  EDKII_VTD_INFO_PPI;
-
-#define EDKII_VTD_INFO_PPI_REVISION 0x0001
-
-struct _EDKII_VTD_INFO_PPI {
-  UINT64  Revision;
-  UINT8   HostAddressWidth;
-  UINT8   Reserved[3];
-  UINT32  VTdEngineCount;
-  UINT64  VTdEngineAddress[1];
-};
+//
+// VTD info PPI just use same data structure as DMAR table.
+//
+// The reported information must include what is needed in PEI phase, e.g.
+//   the VTd engine (such as DRHD)
+//   the reserved DMA address in PEI for eary graphic (such as RMRR for 
graphic UMA)
+//
+// The reported information can be and might be a subset of full DMAR table, 
e.g.
+//   if some data is not avaiable (such as ANDD),
+//   if some data is not needed (such as RMRR for legacy USB).
+//
+typedef EFI_ACPI_DMAR_HEADER EDKII_VTD_INFO_PPI;
 
 extern EFI_GUID gEdkiiVTdInfoPpiGuid;
 
-- 
2.7.4.windows.1

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[edk2] [PATCH 0/3] IntelSiliconPkg/InteVTdPei: Add RMRR support in PEI

[Jiewen Yao]

We notice that there is real usage in PEI to show
the graphic output.
The Integrated Graphic Device is blocked by current
IntelVTdPei because the DMA buffer is fully controlled
by VTd PEIM. The UMA is not allowed.

In DXE phase, the UMA is reported via RMRR table.

As such, we need similar way in PEI to let VTd PEI
get the RMRR information.

This series patch resolves this problem.

We also updated sample driver to show how to get the RMRR information.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>

Jiewen Yao (3):
  IntelSiliconPkg/VTdInfoPpi: Let it follow DMAR table.
  IntelSiliconPkg/IntelVTdPmrPei: Parse RMRR table.
  IntelSiliconPkg/VTdInfoSample: Add RMRR table.

 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c   
   |  52 +-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
   | 581 +++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.h
   |  20 +-
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c 
  | 156 +-
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
 |   3 +
 IntelSiliconPkg/Include/Ppi/VtdInfo.h  
   |  26 +-
 6 files changed, 788 insertions(+), 50 deletions(-)

-- 
2.7.4.windows.1

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[edk2] [PATCH 3/3] IntelSiliconPkg/VTdInfoSample: Add RMRR table.

[Jiewen Yao]

Let system report RMRR table for the platform support
PEI graphic.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c 
  | 156 ++--
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
 |   3 +
 2 files changed, 149 insertions(+), 10 deletions(-)

diff --git 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
index c79398f..423e2f1 100644
--- 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
+++ 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -18,21 +18,111 @@
 
 #include 
 #include 
+#include 
+#include 
+
+#define R_SA_MCHBAR   (0x48)
+#define R_SA_GGC  (0x50)
+#define N_SKL_SA_GGC_GGMS_OFFSET  (0x6)
+#define B_SKL_SA_GGC_GGMS_MASK(0xc0)
+#define N_SKL_SA_GGC_GMS_OFFSET   (0x8)
+#define B_SKL_SA_GGC_GMS_MASK (0xff00)
+#define V_SKL_SA_GGC_GGMS_8MB 3
+#define R_SA_TOLUD(0xbc)
+
+#define R_SA_MCHBAR_VTD1_OFFSET  0x5400  ///< HW UNIT for IGD
+#define R_SA_MCHBAR_VTD2_OFFSET  0x5410  ///< HW UNIT for all other - PEG, 
USB, SATA etc
 
 typedef struct {
-  UINT64  Revision;
-  UINT8   HostAddressWidth;
-  UINT8   Reserved[3];
-  UINT32  VTdEngineCount;
-  UINT64  VTdEngineAddress[2];
+  EFI_ACPI_DMAR_HEADER DmarHeader;
+  //
+  // VTd engine 1 - integrated graphic
+  //
+  EFI_ACPI_DMAR_DRHD_HEADERDrhd1;
+  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER  Drhd11;
+  EFI_ACPI_DMAR_PCI_PATH   Drhd111;
+  //
+  // VTd engine 2 - all rest
+  //
+  EFI_ACPI_DMAR_DRHD_HEADERDrhd2;
+  //
+  // RMRR 1 - integrated graphic
+  //
+  EFI_ACPI_DMAR_RMRR_HEADERRmrr1;
+  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER  Rmrr11;
+  EFI_ACPI_DMAR_PCI_PATH   Rmrr111;
 } MY_VTD_INFO_PPI;
 
 MY_VTD_INFO_PPI  mPlatformVTdSample = {
-  EDKII_VTD_INFO_PPI_REVISION,
-  0x26,
-  {0},
-  2,
-  {0xFED9, 0xFED91000},
+  { // DmarHeader
+{ // Header
+  EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,
+  sizeof(MY_VTD_INFO_PPI),
+  EFI_ACPI_DMAR_REVISION,
+},
+0x26, // HostAddressWidth
+  },
+
+  { // Drhd1
+{ // Header
+  EFI_ACPI_DMAR_TYPE_DRHD,
+  sizeof(EFI_ACPI_DMAR_DRHD_HEADER) +
+sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +
+sizeof(EFI_ACPI_DMAR_PCI_PATH)
+},
+0, // Flags
+0, // Reserved
+0, // SegmentNumber
+0xFED9 // RegisterBaseAddress -- TO BE PATCHED
+  },
+  { // Drhd11
+EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,
+sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +
+  sizeof(EFI_ACPI_DMAR_PCI_PATH),
+0, // Reserved2
+0, // EnumerationId
+0  // StartBusNumber
+  },
+  { // Drhd111
+2,  // Device
+0   // Function
+  },
+
+  { // Drhd2
+{ // Header
+  EFI_ACPI_DMAR_TYPE_DRHD,
+  sizeof(EFI_ACPI_DMAR_DRHD_HEADER)
+},
+EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags
+0, // Reserved
+0, // SegmentNumber
+0xFED91000 // RegisterBaseAddress -- TO BE PATCHED
+  },
+
+  { // Rmrr1
+{ // Header
+  EFI_ACPI_DMAR_TYPE_RMRR,
+  sizeof(EFI_ACPI_DMAR_RMRR_HEADER) +
+sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +
+sizeof(EFI_ACPI_DMAR_PCI_PATH)
+},
+{0}, // Reserved
+0, // SegmentNumber
+0x0, // ReservedMemoryRegionBaseAddress -- TO BE PATCHED
+0x0 // ReservedMemoryRegionLimitAddress -- TO BE PATCHED
+  },
+  { // Rmrr11
+EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,
+sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +
+  sizeof(EFI_ACPI_DMAR_PCI_PATH),
+0, // Reserved2
+0, // EnumerationId
+0  // StartBusNumber
+  },
+  { // Rmrr111
+2,  // Device
+0   // Function
+  },
 };
 
 EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {
@@ -42,6 +132,50 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {
 };
 
 /**
+  Patch Graphic UMA address in RMRR and base address.
+**/
+VOID
+PatchDmar (
+  VOID
+  )
+{
+  UINT32  MchBar;
+  UINT16  IgdMode;
+  UINT16  GttMode;
+  UINT32  IgdMemSize;
+  UINT32  GttMemSize;
+
+  ///
+  /// Calculate IGD memsize
+  ///
+  IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & 
B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;
+  if (IgdMode < 0xF0) {
+IgdMemSize = IgdMode * 32 * (1024) * (1024);
+  } else {
+IgdMemSize

[edk2] [PATCH 2/3] IntelSiliconPkg/IntelVTdPmrPei: Parse RMRR table.

[Jiewen Yao]

In order to support PEI graphic, we let VTdPmrPei driver
parse DMAR table RMRR entry and allow the UMA access.

If a system has no PEI IGD, no RMRR is needed. The behavior
is unchanged.

If a system has PEI IGD, it must report RMRR in PEI phase.
The PeiVTdPrm will program the IGD VTd engine to skip the
RMRR region, and program the reset PCI VTd engine to skip
the another DMA buffer allocated in PEI phase for other
device driver.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c|  52 +-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c | 581 
+++-
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.h |  20 +-
 3 files changed, 624 insertions(+), 29 deletions(-)

diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c 
b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c
index ef08e29..be841aa 100644
--- a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c
@@ -22,7 +22,7 @@
 
 #include "IntelVTdPmrPei.h"
 
-extern EDKII_VTD_INFO_PPI*mVTdInfoPpi;
+extern VTD_INFO*mVTdInfo;
 
 /**
   Get protected low memory alignment.
@@ -60,7 +60,7 @@ GetPhmrAlignment (
   UINT64Data64;
   UINT8 HostAddressWidth;
 
-  HostAddressWidth = mVTdInfoPpi->HostAddressWidth;
+  HostAddressWidth = mVTdInfo->HostAddressWidth;
 
   MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG, 0x);
   Data64 = MmioRead64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG);
@@ -73,11 +73,13 @@ GetPhmrAlignment (
 /**
   Get protected low memory alignment.
 
+  @param EngineMask The mask of the VTd engine to be accessed.
+
   @return protected low memory alignment.
 **/
 UINT32
 GetLowMemoryAlignment (
-  VOID
+  IN UINT64EngineMask
   )
 {
   UINTN Index;
@@ -85,8 +87,11 @@ GetLowMemoryAlignment (
   UINT32FinalAlignment;
 
   FinalAlignment = 0;
-  for (Index = 0; Index < mVTdInfoPpi->VTdEngineCount; Index++) {
-Alignment = GetPlmrAlignment ((UINTN)mVTdInfoPpi->VTdEngineAddress[Index]);
+  for (Index = 0; Index < mVTdInfo->VTdEngineCount; Index++) {
+if ((EngineMask & LShiftU64(1, Index)) == 0) {
+  continue;
+}
+Alignment = GetPlmrAlignment ((UINTN)mVTdInfo->VTdEngineAddress[Index]);
 if (FinalAlignment < Alignment) {
   FinalAlignment = Alignment;
 }
@@ -97,11 +102,13 @@ GetLowMemoryAlignment (
 /**
   Get protected high memory alignment.
 
+  @param EngineMask The mask of the VTd engine to be accessed.
+
   @return protected high memory alignment.
 **/
 UINT64
 GetHighMemoryAlignment (
-  VOID
+  IN UINT64EngineMask
   )
 {
   UINTN Index;
@@ -109,8 +116,11 @@ GetHighMemoryAlignment (
   UINT64FinalAlignment;
 
   FinalAlignment = 0;
-  for (Index = 0; Index < mVTdInfoPpi->VTdEngineCount; Index++) {
-Alignment = GetPhmrAlignment ((UINTN)mVTdInfoPpi->VTdEngineAddress[Index]);
+  for (Index = 0; Index < mVTdInfo->VTdEngineCount; Index++) {
+if ((EngineMask & LShiftU64(1, Index)) == 0) {
+  continue;
+}
+Alignment = GetPhmrAlignment ((UINTN)mVTdInfo->VTdEngineAddress[Index]);
 if (FinalAlignment < Alignment) {
   FinalAlignment = Alignment;
 }
@@ -246,6 +256,7 @@ SetPmrRegion (
 /**
   Set DMA protected region.
 
+  @param EngineMask The mask of the VTd engine to be accessed.
   @param LowMemoryBase  The protected low memory region base.
   @param LowMemoryLengthThe protected low memory region length.
   @param HighMemoryBase The protected high memory region base.
@@ -256,6 +267,7 @@ SetPmrRegion (
 **/
 EFI_STATUS
 SetDmaProtectedRange (
+  IN UINT64EngineMask,
   IN UINT32LowMemoryBase,
   IN UINT32LowMemoryLength,
   IN UINT64HighMemoryBase,
@@ -265,12 +277,15 @@ SetDmaProtectedRange (
   UINTN   Index;
   EFI_STATUS  Status;
 
-  DEBUG ((DEBUG_INFO, "SetDmaProtectedRange - [0x%x, 0x%x] [0x%lx, 0x%lx]\n", 
LowMemoryBase, LowMemoryLength, HighMemoryBase, HighMemoryLength));
+  DEBUG ((DEBUG_INFO, "SetDmaProtectedRange(0x%lx) - [0x%x, 0x%x] [0x%lx, 
0x%lx]\n", EngineMask, LowMemoryBase, LowMemoryLength, HighMemoryBase, 
HighMemoryLength));
 
-  for (Index = 0; Index < mVTdInfoPpi->VTdEngineCount; Index++) {
-DisablePmr ((UINTN)mVTdInfoPpi->VTdEngineAddress[Index]);
+  for (Index = 0; Index < mVTdInfo->VTdEngineCount; Index++) {
+if ((EngineMask & LShiftU64(1, Index)) == 0) {
+  continue;
+}
+DisablePmr ((UINTN)mVTdInfo->VTdEngineAddress[Index]);
 Status = SetPmrRegion (
-   (UINTN)mVTdInfoPpi->VTdEngineAddress[Index],
+   (UINTN)mVTdInfo->VTdEngineAd

[edk2] [PATCH 2/4] IntelSiliconPkg/PlatformVTdSampleDxe: Move to feature dir.

[Jiewen Yao]

Move PlatformVTdSampleDxe to Feature/VTd/PlatformVTdSampleDxe.

Suggested-by: Star Zeng <star.z...@intel.com>
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c
| 409 
 IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxe.inf  
|  59 +++
 IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxe.uni  
|  20 +
 IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxeExtra.uni 
|  20 +
 IntelSiliconPkg/IntelSiliconPkg.dsc
|   2 +-
 IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c
| 409 
 IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.inf  
|  59 ---
 IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.uni  
|  20 -
 IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxeExtra.uni 
|  20 -
 9 files changed, 509 insertions(+), 509 deletions(-)

diff --git 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c
new file mode 100644
index 000..3587fa3
--- /dev/null
+++ b/IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c
@@ -0,0 +1,409 @@
+/** @file
+  Platform VTd Sample driver.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+typedef struct {
+  ACPI_EXTENDED_HID_DEVICE_PATH  I2cController;
+  UINT8  HidStr[8];
+  UINT8  UidStr[1];
+  UINT8  CidStr[8];
+} PLATFORM_I2C_CONTROLLER_DEVICE_PATH;
+
+typedef struct {
+  ACPI_EXTENDED_HID_DEVICE_PATH  I2cDevice;
+  UINT8  HidStr[13];
+  UINT8  UidStr[1];
+  UINT8  CidStr[13];
+} PLATFORM_I2C_DEVICE_DEVICE_PATH;
+
+typedef struct {
+  PLATFORM_I2C_CONTROLLER_DEVICE_PATH  I2cController;
+  PLATFORM_I2C_DEVICE_DEVICE_PATH  I2cDevice;
+  EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_I2C_DEVICE_PATH;
+
+typedef struct {
+  ACPI_HID_DEVICE_PATH  PciRootBridge;
+  PCI_DEVICE_PATH   PciDevice;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} PLATFORM_PCI_DEVICE_PATH;
+
+typedef struct {
+  ACPI_HID_DEVICE_PATH  PciRootBridge;
+  PCI_DEVICE_PATH   PciBridge;
+  PCI_DEVICE_PATH   PciDevice;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} PLATFORM_PCI_BRIDGE_DEVICE_PATH;
+
+typedef struct {
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;
+  UINT16Segment;
+  VTD_SOURCE_ID SourceId;
+} PLATFORM_ACPI_DEVICE_MAPPING;
+
+#define PLATFORM_PCI_ROOT_BRIDGE \
+  { \
+{ \
+  ACPI_DEVICE_PATH, \
+  ACPI_DP, \
+  { \
+(UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \
+(UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \
+  }, \
+}, \
+EISA_PNP_ID (0x0A03), \
+0 \
+  }
+
+#define PLATFORM_END_ENTIRE \
+  { \
+END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { 
END_DEVICE_PATH_LENGTH, 0 } \
+  }
+
+#define PLATFORM_PCI(Device, Function) \
+  { \
+{ \
+  HARDWARE_DEVICE_PATH, \
+  HW_PCI_DP, \
+  { \
+(UINT8) (sizeof (PCI_DEVICE_PATH)), \
+(UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \
+  } \
+}, \
+(Function), \
+(Device) \
+  }
+
+#define PLATFORM_I2C(Hid, Uid, Cid, HidStr, UidStr, CidStr) \
+  { \
+{ \
+  { \
+ACPI_DEVICE_PATH, \
+ACPI_EXTENDED_DP, \
+{sizeof(ACPI_EXTENDED_HID_DEVICE_PATH) + sizeof(HidStr) + 
sizeof(UidStr) + sizeof(CidStr), 0} \
+  }, \
+  Hid, \
+  Uid, \
+  Cid \
+}, \
+HidStr, \
+UidStr, \
+CidStr \
+  }
+
+PLATFORM_I2C_DEVICE_PATH mPlatformI2CDevicePath = {
+  PLATFORM_I2C(0, 2, 0, "INT33C3", "", "INT33C3"),
+  PLATFORM_I2C(0, 1, 0, "I2C01\\TPANEL", "", "I2C01\\TPANEL"),
+  PLATFORM_END_ENTIRE
+};
+
+PLATFORM_ACPI_DEVICE_MAPPING  mAcpiDeviceMapping[] = {
+  {
+(EFI_DEVICE_PATH_PROTOCOL *),
+0x0, // Segment
+{{0x01, 0x15, 0x00

[edk2] [PATCH 0/4] IntelSiliconPkg: move VTd related modules to feature dir.

[Jiewen Yao]

This patch is to address the feedback from Star.Zeng during code review.

We group 4 VTd related modules to Feature/VTd dir to better maintance.

No code update, only location move.

Suggested-by: Star Zeng <star.z...@intel.com>
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen....@intel.com>

Jiewen Yao (4):
  IntelSiliconPkg/IntelVTdDxe: Move to feature dir.
  IntelSiliconPkg/PlatformVTdSampleDxe: Move to feature dir.
  IntelSiliconPkg/IntelVTdPmrPei: Move to feature dir.
  IntelSiliconPkg/PlatformIntelVTdInfoSamplePei: Move to feature dir.

 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/BmDma.c
|  441 +
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c
|  503 ++
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.h
|  562 +++
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c
| 1016 +++
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c  
|  370 +++
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
|   85 ++
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.uni
|   20 +
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxeExtra.uni   
|   20 +
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/PciInfo.c  
|  369 +++
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c 
| 1018 
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c   
|  157 +++
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c   
|  565 +++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c   
|  314 ++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
|  615 
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.h
|   68 ++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf  
|   59 ++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.uni  
|   20 +
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPeiExtra.uni 
|   20 +
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c 
   |   65 ++
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
  |   51 +
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.uni
  |   20 +
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePeiExtra.uni
 |   20 +
 IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c
|  409 
 IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxe.inf  
|   59 ++
 IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxe.uni  
|   20 +
 IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxeExtra.uni 
|   20 +
 IntelSiliconPkg/IntelSiliconPkg.dsc
|8 +-
 IntelSiliconPkg/IntelVTdDxe/BmDma.c
|  441 -
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.c
|  503 --
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.h
|  562 ---
 IntelSiliconPkg/IntelVTdDxe/DmarAcpiTable.c
| 1016 ---
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c  
|  370 ---
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf
|   85 --
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.uni
|   20 -
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxeExtra.uni   
|   20 -
 IntelSiliconPkg/IntelVTdDxe/PciInfo.c  
|  369 ---
 IntelSiliconPkg/IntelVTdDxe/TranslationTable.c 
| 1018 
 IntelSiliconPkg/IntelVTdDxe/TranslationTableEx.c   
|  157 ---
 IntelSiliconPkg/IntelVTdDxe/VtdReg.c   
|  565 ---
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmr.c   
|  314 --
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.c
|  615 
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.h
|   68 -

[edk2] [PATCH 4/4] IntelSiliconPkg/PlatformIntelVTdInfoSamplePei: Move to feature dir.

[Jiewen Yao]

Move PlatformIntelVTdInfoSamplePei to Feature/VTd/.

Suggested-by: Star Zeng <star.z...@intel.com>
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c 
   | 65 
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
  | 51 +++
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.uni
  | 20 ++
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePeiExtra.uni
 | 20 ++
 IntelSiliconPkg/IntelSiliconPkg.dsc
|  2 +-
 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
| 65 
 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf  
| 51 ---
 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.uni  
| 20 --
 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePeiExtra.uni 
| 20 --
 9 files changed, 157 insertions(+), 157 deletions(-)

diff --git 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
new file mode 100644
index 000..c79398f
--- /dev/null
+++ 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -0,0 +1,65 @@
+/** @file
+  Platform VTd Info Sample PEI driver.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+
+#include 
+
+#include 
+#include 
+
+typedef struct {
+  UINT64  Revision;
+  UINT8   HostAddressWidth;
+  UINT8   Reserved[3];
+  UINT32  VTdEngineCount;
+  UINT64  VTdEngineAddress[2];
+} MY_VTD_INFO_PPI;
+
+MY_VTD_INFO_PPI  mPlatformVTdSample = {
+  EDKII_VTD_INFO_PPI_REVISION,
+  0x26,
+  {0},
+  2,
+  {0xFED9, 0xFED91000},
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  ,
+  
+};
+
+/**
+  Platform VTd Info sample driver.
+
+  @param[in] FileHandle  Handle of the file being invoked.
+  @param[in] PeiServices Describes the list of possible PEI Services.
+
+  @retval EFI_SUCCESS if it completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+PlatformVTdInfoSampleInitialize (
+  IN   EFI_PEI_FILE_HANDLE  FileHandle,
+  IN CONST EFI_PEI_SERVICES **PeiServices
+  )
+{
+  EFI_STATUS  Status;
+
+  Status = PeiServicesInstallPpi ();
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
diff --git 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
new file mode 100644
index 000..fe12821
--- /dev/null
+++ 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
@@ -0,0 +1,51 @@
+## @file
+# Platform VTd Info Sample PEI driver.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD 
License
+# which accompanies this distribution.  The full text of the license may be 
found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = PlatformVTdInfoSamplePei
+  MODULE_UNI_FILE= PlatformVTdInfoSamplePei.uni
+  FILE_GUID  = 839EB770-5C64-4EED-A6D5-EC515B2B2B23
+  MODULE_TYPE= PEIM
+  VERSION_STRING = 1.0
+  ENTRY_POINT= PlatformVTdInfoSampleInitialize
+
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+#  VALID_ARCHITECTURES   = IA32 X64 IPF EBC
+#
+#
+
+[Sources]
+  PlatformVTdInfoSamplePei.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
+
+[LibraryClasses]
+  Pei

[edk2] [PATCH 3/4] IntelSiliconPkg/IntelVTdPmrPei: Move to feature dir.

[Jiewen Yao]

Move IntelVTdPmrPei to Feature/VTd/IntelVTdPmrPei.

Suggested-by: Star Zeng <star.z...@intel.com>
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c   | 314 
++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c| 615 

 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.h|  68 +++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf  |  59 ++
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.uni  |  20 +
 IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPeiExtra.uni |  20 +
 IntelSiliconPkg/IntelSiliconPkg.dsc|   2 +-
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmr.c   | 314 
--
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.c| 615 

 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.h|  68 ---
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.inf  |  59 --
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.uni  |  20 -
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPeiExtra.uni |  20 -
 13 files changed, 1097 insertions(+), 1097 deletions(-)

diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c 
b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c
new file mode 100644
index 000..ef08e29
--- /dev/null
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c
@@ -0,0 +1,314 @@
+/** @file
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License which accompanies this 
distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "IntelVTdPmrPei.h"
+
+extern EDKII_VTD_INFO_PPI*mVTdInfoPpi;
+
+/**
+  Get protected low memory alignment.
+
+  @param VtdUnitBaseAddress The base address of the VTd engine.
+
+  @return protected low memory alignment.
+**/
+UINT32
+GetPlmrAlignment (
+  IN UINTN VtdUnitBaseAddress
+  )
+{
+  UINT32Data32;
+
+  MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG, 0x);
+  Data32 = MmioRead32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG);
+  Data32 = ~Data32 + 1;
+
+  return Data32;
+}
+
+/**
+  Get protected high memory alignment.
+
+  @param VtdUnitBaseAddress The base address of the VTd engine.
+
+  @return protected high memory alignment.
+**/
+UINT64
+GetPhmrAlignment (
+  IN UINTN VtdUnitBaseAddress
+  )
+{
+  UINT64Data64;
+  UINT8 HostAddressWidth;
+
+  HostAddressWidth = mVTdInfoPpi->HostAddressWidth;
+
+  MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG, 0x);
+  Data64 = MmioRead64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG);
+  Data64 = ~Data64 + 1;
+  Data64 = Data64 & (LShiftU64 (1, HostAddressWidth) - 1);
+
+  return Data64;
+}
+
+/**
+  Get protected low memory alignment.
+
+  @return protected low memory alignment.
+**/
+UINT32
+GetLowMemoryAlignment (
+  VOID
+  )
+{
+  UINTN Index;
+  UINT32Alignment;
+  UINT32FinalAlignment;
+
+  FinalAlignment = 0;
+  for (Index = 0; Index < mVTdInfoPpi->VTdEngineCount; Index++) {
+Alignment = GetPlmrAlignment ((UINTN)mVTdInfoPpi->VTdEngineAddress[Index]);
+if (FinalAlignment < Alignment) {
+  FinalAlignment = Alignment;
+}
+  }
+  return FinalAlignment;
+}
+
+/**
+  Get protected high memory alignment.
+
+  @return protected high memory alignment.
+**/
+UINT64
+GetHighMemoryAlignment (
+  VOID
+  )
+{
+  UINTN Index;
+  UINT64Alignment;
+  UINT64FinalAlignment;
+
+  FinalAlignment = 0;
+  for (Index = 0; Index < mVTdInfoPpi->VTdEngineCount; Index++) {
+Alignment = GetPhmrAlignment ((UINTN)mVTdInfoPpi->VTdEngineAddress[Index]);
+if (FinalAlignment < Alignment) {
+  FinalAlignment = Alignment;
+}
+  }
+  return FinalAlignment;
+}
+
+/**
+  Enable PMR in the VTd engine.
+
+  @param VtdUnitBaseAddress The base address of the VTd engine.
+
+  @retval EFI_SUCCESS  The PMR is enabled.
+  @retval EFI_UNSUPPORTED  The PMR is not supported.
+**/
+EFI_STATUS
+EnablePmr (
+  IN UINTN VtdUnitBaseAddress
+  )
+{
+  UINT32Reg32;
+  VTD_CAP_REG   CapReg;
+
+  CapReg.Uint64 = MmioRead64 (VtdUnitBaseAddress + R_CAP_REG);
+  if (CapReg.Bits.PLMR == 0 || CapReg.Bits.PHMR == 0) {
+return EFI_UNSUPPORTED;
+  }
+
+  Reg32 = MmioRead32

[edk2] [PATCH 02/11] MdeModulePkg/Dec: Add IOMMU_PPI GUID.

[Jiewen Yao]

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdeModulePkg/MdeModulePkg.dec | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
index 593bff3..403a66a 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -431,6 +431,9 @@
   ## Include/Ppi/SdMmcHostController.h
   gEdkiiPeiSdMmcHostControllerPpiGuid = { 0xb30dfeed, 0x947f, 0x4396, { 0xb1, 
0x5a, 0xdf, 0xbd, 0xb9, 0x16, 0xdc, 0x24 }}
 
+  ## Include/Ppi/IoMmu.h
+  gEdkiiIoMmuPpiGuid = { 0x70b0af26, 0xf847, 0x4bb6, { 0xaa, 0xb9, 0xcd, 0xe8, 
0x4f, 0xc6, 0x14, 0x31 } }
+
 [Protocols]
   ## Load File protocol provides capability to load and unload EFI image into 
memory and execute it.
   #  Include/Protocol/LoadPe32Image.h
-- 
2.7.4.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH 09/11] IntelSiliconPkg: Add PlatformVTdInfoSamplePei.

[Jiewen Yao]

This is a sample driver to produce VTD_INFO PPI.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c| 
65 
 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf  | 
51 +++
 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.uni  | 
20 ++
 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePeiExtra.uni | 
20 ++
 4 files changed, 156 insertions(+)

diff --git 
a/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c 
b/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
new file mode 100644
index 000..c79398f
--- /dev/null
+++ b/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -0,0 +1,65 @@
+/** @file
+  Platform VTd Info Sample PEI driver.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+
+#include 
+
+#include 
+#include 
+
+typedef struct {
+  UINT64  Revision;
+  UINT8   HostAddressWidth;
+  UINT8   Reserved[3];
+  UINT32  VTdEngineCount;
+  UINT64  VTdEngineAddress[2];
+} MY_VTD_INFO_PPI;
+
+MY_VTD_INFO_PPI  mPlatformVTdSample = {
+  EDKII_VTD_INFO_PPI_REVISION,
+  0x26,
+  {0},
+  2,
+  {0xFED9, 0xFED91000},
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  ,
+  
+};
+
+/**
+  Platform VTd Info sample driver.
+
+  @param[in] FileHandle  Handle of the file being invoked.
+  @param[in] PeiServices Describes the list of possible PEI Services.
+
+  @retval EFI_SUCCESS if it completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+PlatformVTdInfoSampleInitialize (
+  IN   EFI_PEI_FILE_HANDLE  FileHandle,
+  IN CONST EFI_PEI_SERVICES **PeiServices
+  )
+{
+  EFI_STATUS  Status;
+
+  Status = PeiServicesInstallPpi ();
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
diff --git 
a/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf 
b/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
new file mode 100644
index 000..fe12821
--- /dev/null
+++ b/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
@@ -0,0 +1,51 @@
+## @file
+# Platform VTd Info Sample PEI driver.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD 
License
+# which accompanies this distribution.  The full text of the license may be 
found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = PlatformVTdInfoSamplePei
+  MODULE_UNI_FILE= PlatformVTdInfoSamplePei.uni
+  FILE_GUID  = 839EB770-5C64-4EED-A6D5-EC515B2B2B23
+  MODULE_TYPE= PEIM
+  VERSION_STRING = 1.0
+  ENTRY_POINT= PlatformVTdInfoSampleInitialize
+
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+#  VALID_ARCHITECTURES   = IA32 X64 IPF EBC
+#
+#
+
+[Sources]
+  PlatformVTdInfoSamplePei.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
+
+[LibraryClasses]
+  PeimEntryPoint
+  PeiServicesLib
+
+[Ppis]
+  gEdkiiVTdInfoPpiGuid ## PRODUCES
+
+[Depex]
+  gEfiPeiMemoryDiscoveredPpiGuid
+
+[UserExtensions.TianoCore."ExtraFiles"]
+  PlatformVTdInfoSamplePeiExtra.uni
+
diff --git 
a/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.uni 
b/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.uni
new file mode 100644
index 000..36f9183
--- /dev/null
+++ b/IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.uni
@@ -0,0 +1,20 @@
+// /** @file
+// PlatformVTdInfoSamplePei Module Localized Abstract and Description Content
+//
+// Copyright (c) 2017, Intel Corporation. All rights reserved.
+//
+// This program and the accompanying materials

[edk2] [PATCH 07/11] IntelSiliconPkg: Add IntelVTdPmrPei.

[Jiewen Yao]

This PEIM is to produce IOMMU_PPI, so that PEI device
driver can have better DAM management.

This PEIM will setup VTD PMR register to protect
most DRAM. It allocates a big chunk DMA buffer in
the entrypoint, and only use this buffer for DMA.
Any other region is DMA protected.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmr.c   | 314 ++
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.c| 615 

 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.h|  68 +++
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.inf  |  59 ++
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.uni  |  20 +
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPeiExtra.uni |  20 +
 6 files changed, 1096 insertions(+)

diff --git a/IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmr.c 
b/IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmr.c
new file mode 100644
index 000..ef08e29
--- /dev/null
+++ b/IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmr.c
@@ -0,0 +1,314 @@
+/** @file
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License which accompanies this 
distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "IntelVTdPmrPei.h"
+
+extern EDKII_VTD_INFO_PPI*mVTdInfoPpi;
+
+/**
+  Get protected low memory alignment.
+
+  @param VtdUnitBaseAddress The base address of the VTd engine.
+
+  @return protected low memory alignment.
+**/
+UINT32
+GetPlmrAlignment (
+  IN UINTN VtdUnitBaseAddress
+  )
+{
+  UINT32Data32;
+
+  MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG, 0x);
+  Data32 = MmioRead32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG);
+  Data32 = ~Data32 + 1;
+
+  return Data32;
+}
+
+/**
+  Get protected high memory alignment.
+
+  @param VtdUnitBaseAddress The base address of the VTd engine.
+
+  @return protected high memory alignment.
+**/
+UINT64
+GetPhmrAlignment (
+  IN UINTN VtdUnitBaseAddress
+  )
+{
+  UINT64Data64;
+  UINT8 HostAddressWidth;
+
+  HostAddressWidth = mVTdInfoPpi->HostAddressWidth;
+
+  MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG, 0x);
+  Data64 = MmioRead64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG);
+  Data64 = ~Data64 + 1;
+  Data64 = Data64 & (LShiftU64 (1, HostAddressWidth) - 1);
+
+  return Data64;
+}
+
+/**
+  Get protected low memory alignment.
+
+  @return protected low memory alignment.
+**/
+UINT32
+GetLowMemoryAlignment (
+  VOID
+  )
+{
+  UINTN Index;
+  UINT32Alignment;
+  UINT32FinalAlignment;
+
+  FinalAlignment = 0;
+  for (Index = 0; Index < mVTdInfoPpi->VTdEngineCount; Index++) {
+Alignment = GetPlmrAlignment ((UINTN)mVTdInfoPpi->VTdEngineAddress[Index]);
+if (FinalAlignment < Alignment) {
+  FinalAlignment = Alignment;
+}
+  }
+  return FinalAlignment;
+}
+
+/**
+  Get protected high memory alignment.
+
+  @return protected high memory alignment.
+**/
+UINT64
+GetHighMemoryAlignment (
+  VOID
+  )
+{
+  UINTN Index;
+  UINT64Alignment;
+  UINT64FinalAlignment;
+
+  FinalAlignment = 0;
+  for (Index = 0; Index < mVTdInfoPpi->VTdEngineCount; Index++) {
+Alignment = GetPhmrAlignment ((UINTN)mVTdInfoPpi->VTdEngineAddress[Index]);
+if (FinalAlignment < Alignment) {
+  FinalAlignment = Alignment;
+}
+  }
+  return FinalAlignment;
+}
+
+/**
+  Enable PMR in the VTd engine.
+
+  @param VtdUnitBaseAddress The base address of the VTd engine.
+
+  @retval EFI_SUCCESS  The PMR is enabled.
+  @retval EFI_UNSUPPORTED  The PMR is not supported.
+**/
+EFI_STATUS
+EnablePmr (
+  IN UINTN VtdUnitBaseAddress
+  )
+{
+  UINT32Reg32;
+  VTD_CAP_REG   CapReg;
+
+  CapReg.Uint64 = MmioRead64 (VtdUnitBaseAddress + R_CAP_REG);
+  if (CapReg.Bits.PLMR == 0 || CapReg.Bits.PHMR == 0) {
+return EFI_UNSUPPORTED;
+  }
+
+  Reg32 = MmioRead32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG);
+  if ((Reg32 & BIT0) == 0) {
+MmioWrite32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG, BIT31);
+do {
+  Reg32 = MmioRead32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG);
+} while((Reg32 & BIT0) == 0);
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Disable PMR in the VTd engine.
+
+  @param VtdUnitBaseAddress The base address of the VTd engine.
+
+  @retval EFI_SUCCESS  The PMR is disabled.
+  @retval EFI_UNSUPPORTED  The PMR is not supported.
+**/
+EFI_STATUS

[edk2] [PATCH 00/11] Add IOMMU PEI support.

[Jiewen Yao]

This series patch added IOMMU PEI support.
It is also posted to https://github.com/jyao1/edk2/tree/IoMmuPpi.

1) Patch 1 and 2 add EDKII_IOMMU_PPI.
It is similar to EDKII_IOMMU_PROTOCOL.

2) Patch 3 and 4 add Intel VTD PMR register support
for DXE phase IntelVTdDxe.
This is to prepare handle PMR usage in PEI phase.

3) Patch 5 and 6 add EDKII_VTD_INFO_PPI.
This PPI is to provide Intel VTD information in PEI.
In DXE, the VTd driver can get VTD info from ACPI DMAR table.
But in PEI, there is no way to get VTD info before.
VTD_INFO_PPI is added to resolve the problem.

4) Patch 7 and 8 add IntelVTdPmrPei driver.
This driver consumes EDKII_VTD_INFO_PPI and produces IOMMU_PPI.
It enables VTD PMR register to provide DMA protection.
The PMR based DMA protection is a simple solution to
mark 2 regions can be DMA protected.
The IntelVTdPmrPei allocates a small chunk buffer for DMA
and protect the rest memory.

5) Patch 9 and 10 add a sample VTdInfo PEI driver.
It provides a sample to show how to report VTd info in PEI phase.

6) Patch 11 updates XhciPei driver to consume IOMMU_PPI.
If the IOMMU_PPI is present, XhciPei will use IOMMU_PPI to
allocate DMA buffer. Or the XhciPei will still use old way -
PeiServiceAllocatePage to allocate DRAM as DMA buffer.
This is the first PEI device driver consuming IOMMU_PPI to
show the concept. The rest PEI device drivers will be
updated in separated patches.


This series patch is validated on Intel Kabylake Platform.
1) We can use XHCI to do file transfer in PEI phase,
2) We can still use XHCI in DXE phase, such as shell environment.
3) If the device driver does not consume IOMMU_PPI, the DMA fails.

Jiewen Yao (11):
  MdeModulePkg/Include: Add IOMMU_PPI.
  MdeModulePkg/Dec: Add IOMMU_PPI GUID.
  IntelSiliconPkg/Vtd.h: Add definition for PMR.
  IntelSiliconPkg/VTdDxe: Disable PMR
  IntelSiliconPkg/include: Add VTD_INFO PPI.
  IntelSiliconPkg/dec: Add VTD_INFO PPI GUID
  IntelSiliconPkg: Add IntelVTdPmrPei.
  IntelSiliconPkg/dsc: Add IntelVTdPmrPeim.
  IntelSiliconPkg: Add PlatformVTdInfoSamplePei.
  IntelSiliconPkg/dsc: Add PlatformVTdInfoSamplePei.
  MdeModulePkg/XhciPei: Support IoMmu.

 IntelSiliconPkg/Include/IndustryStandard/Vtd.h |   
6 +
 IntelSiliconPkg/Include/Ppi/VtdInfo.h  |  
40 ++
 IntelSiliconPkg/IntelSiliconPkg.dec|   
3 +
 IntelSiliconPkg/IntelSiliconPkg.dsc|  
10 +
 IntelSiliconPkg/IntelVTdDxe/VtdReg.c   |  
51 +-
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmr.c   | 
314 ++
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.c| 
615 
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.h|  
68 +++
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.inf  |  
59 ++
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.uni  |  
20 +
 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPeiExtra.uni |  
20 +
 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c|  
65 +++
 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf  |  
51 ++
 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.uni  |  
20 +
 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePeiExtra.uni |  
20 +
 MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c  | 
249 
 MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c|  
55 +-
 MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h|   
9 +-
 MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c |  
55 +-
 MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h | 
107 
 MdeModulePkg/Bus/Pci/XhciPei/XhciPei.inf   |   
3 +
 MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c   |  
47 +-
 MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h   |   
1 +
 MdeModulePkg/Include/Ppi/IoMmu.h   | 
196 +++
 MdeModulePkg/MdeModulePkg.dec  |   
3 +
 25 files changed, 2052 insertions(+), 35 deletions(-)
 create mode 100644 IntelSiliconPkg/Include/Ppi/VtdInfo.h
 create mode 100644 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmr.c
 create mode 100644 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.c
 create mode 100644 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.h
 create mode 100644 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.inf
 create mode 100644 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.uni
 create mode 100644 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPeiExtra.uni
 create mode 100644 
IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
 create mode 100644 
IntelSiliconPkg

[edk2] [PATCH 11/11] MdeModulePkg/XhciPei: Support IoMmu.

[Jiewen Yao]

Update XHCI driver to consume IOMMU_PPI to allocate DMA buffer.

If no IOMMU_PPI exists, this driver still calls PEI service
to allocate DMA buffer, with assumption that DRAM==DMA.

This is a compatible change.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c| 249 
 MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c  |  55 +++--
 MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h  |   9 +-
 MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c   |  55 -
 MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h   | 107 +
 MdeModulePkg/Bus/Pci/XhciPei/XhciPei.inf |   3 +
 MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c |  47 +++-
 MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h |   1 +
 8 files changed, 492 insertions(+), 34 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c 
b/MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c
new file mode 100644
index 000..6e2c1b5
--- /dev/null
+++ b/MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c
@@ -0,0 +1,249 @@
+/** @file
+The DMA memory help function.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions
+of the BSD License which accompanies this distribution.  The
+full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "XhcPeim.h"
+
+EDKII_IOMMU_PPI  *mIoMmu;
+
+/**
+  Provides the controller-specific addresses required to access system memory 
from a
+  DMA bus master.
+
+  @param  Operation Indicates if the bus master is going to read 
or write to system memory.
+  @param  HostAddress   The system memory address to map to the PCI 
controller.
+  @param  NumberOfBytes On input the number of bytes to map. On output 
the number of bytes
+that were mapped.
+  @param  DeviceAddress The resulting map address for the bus master 
PCI controller to use to
+access the hosts HostAddress.
+  @param  Mapping   A resulting value to pass to Unmap().
+
+  @retval EFI_SUCCESS   The range was mapped for the returned 
NumberOfBytes.
+  @retval EFI_UNSUPPORTED   The HostAddress cannot be mapped as a common 
buffer.
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a 
lack of resources.
+  @retval EFI_DEVICE_ERROR  The system hardware could not map the 
requested address.
+
+**/
+EFI_STATUS
+IoMmuMap (
+  IN  EDKII_IOMMU_OPERATION Operation,
+  IN VOID   *HostAddress,
+  IN  OUT UINTN *NumberOfBytes,
+  OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,
+  OUT VOID  **Mapping
+  )
+{
+  EFI_STATUS  Status;
+  UINT64  Attribute;
+
+  if (mIoMmu != NULL) {
+Status = mIoMmu->Map (
+   mIoMmu,
+   Operation,
+   HostAddress,
+   NumberOfBytes,
+   DeviceAddress,
+   Mapping
+   );
+if (EFI_ERROR (Status)) {
+  return EFI_OUT_OF_RESOURCES;
+}
+switch (Operation) {
+case EdkiiIoMmuOperationBusMasterRead:
+case EdkiiIoMmuOperationBusMasterRead64:
+  Attribute = EDKII_IOMMU_ACCESS_READ;
+  break;
+case EdkiiIoMmuOperationBusMasterWrite:
+case EdkiiIoMmuOperationBusMasterWrite64:
+  Attribute = EDKII_IOMMU_ACCESS_WRITE;
+  break;
+case EdkiiIoMmuOperationBusMasterCommonBuffer:
+case EdkiiIoMmuOperationBusMasterCommonBuffer64:
+  Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
+  break;
+default:
+  ASSERT(FALSE);
+  return EFI_INVALID_PARAMETER;
+}
+Status = mIoMmu->SetAttribute (
+   mIoMmu,
+   *Mapping,
+   Attribute
+   );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+  } else {
+*DeviceAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
+*Mapping = NULL;
+Status = EFI_SUCCESS;
+  }
+  return Status;
+}
+
+/**
+  Completes the Map() operation and releases any corresponding resources.
+
+  @param  Mapping   The mapping value returned from Map().
+
+  @retval EFI_SUCCESS   The range was unmapped.
+  @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by 
Map().
+  @retval EFI_DEVICE_ERROR  The data was not committed to the target 
system memory.
+**/
+EFI_STATUS
+IoMmuUnmap (
+  IN VOID  *Mapping
+  )
+{
+  EFI_STATUS  Status;
+
+  if (mIoMmu != NULL) {
+Status = mI

[edk2] [PATCH 04/11] IntelSiliconPkg/VTdDxe: Disable PMR

[Jiewen Yao]

When VTd translation is enabled, PMR can be disable.
Or the DMA will be blocked by PMR.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelVTdDxe/VtdReg.c | 51 +++-
 1 file changed, 50 insertions(+), 1 deletion(-)

diff --git a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c 
b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
index 7402d81..1404af7 100644
--- a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
+++ b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
@@ -196,6 +196,39 @@ PrepareVtdConfig (
 }
 
 /**
+  Disable PMR in all VTd engine.
+**/
+VOID
+DisablePmr (
+  VOID
+  )
+{
+  UINT32Reg32;
+  VTD_CAP_REG   CapReg;
+  UINTN Index;
+
+  DEBUG ((DEBUG_INFO,"DisablePmr\n"));
+  for (Index = 0; Index < mVtdUnitNumber; Index++) {
+CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress 
+ R_CAP_REG);
+if (CapReg.Bits.PLMR == 0 || CapReg.Bits.PHMR == 0) {
+  continue ;
+}
+
+Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + 
R_PMEN_ENABLE_REG);
+if ((Reg32 & BIT0) != 0) {
+  MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + 
R_PMEN_ENABLE_REG, 0x0);
+  do {
+Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + 
R_PMEN_ENABLE_REG);
+  } while((Reg32 & BIT0) != 0);
+  DEBUG ((DEBUG_INFO,"Pmr(%d) disabled\n", Index));
+} else {
+  DEBUG ((DEBUG_INFO,"Pmr(%d) not enabled\n", Index));
+}
+  }
+  return ;
+}
+
+/**
   Enable DMAR translation.
 
   @retval EFI_SUCCESS   DMAR translation is enabled.
@@ -259,6 +292,11 @@ EnableDmar (
 DEBUG ((DEBUG_INFO,"VTD (%d) enabled!<<<<<<\n",Index));
   }
 
+  //
+  // Need disable PMR, since we already setup translation table.
+  //
+  DisablePmr ();
+
   mVtdEnabled = TRUE;
 
   return EFI_SUCCESS;
@@ -502,7 +540,7 @@ DumpVtdIfError (
 for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {
   FrcdReg.Uint64[0] = MmioRead64 
(mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index 
* 16) + R_FRCD_REG));
   FrcdReg.Uint64[1] = MmioRead64 
(mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index 
* 16) + R_FRCD_REG + sizeof(UINT64)));
-  if ((FrcdReg.Uint64[0] != 0) || (FrcdReg.Uint64[1] != 0)) {
+  if (FrcdReg.Bits.F != 0) {
 HasError = TRUE;
   }
 }
@@ -511,6 +549,17 @@ DumpVtdIfError (
   DEBUG((DEBUG_INFO, "\n ERROR \n"));
   DumpVtdRegs (Num);
   DEBUG((DEBUG_INFO, " ERROR \n\n"));
+  //
+  // Clear
+  //
+  for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {
+FrcdReg.Uint64[1] = MmioRead64 
(mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index 
* 16) + R_FRCD_REG + sizeof(UINT64)));
+if (FrcdReg.Bits.F != 0) {
+  FrcdReg.Bits.F = 0;
+  MmioWrite64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + 
((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)), 
FrcdReg.Uint64[1]);
+}
+MmioWrite32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG, 
MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG));
+  }
 }
   }
 }
-- 
2.7.4.windows.1

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[edk2] [PATCH 05/11] IntelSiliconPkg/include: Add VTD_INFO PPI.

[Jiewen Yao]

This VTD_INFO_PPI is to provide VTD information in PEI.
As such, we can have a generic VTd driver.

It is a lightweight version DMAR table, but it does
not contain PCI device information.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Include/Ppi/VtdInfo.h | 40 
 1 file changed, 40 insertions(+)

diff --git a/IntelSiliconPkg/Include/Ppi/VtdInfo.h 
b/IntelSiliconPkg/Include/Ppi/VtdInfo.h
new file mode 100644
index 000..e8be63f
--- /dev/null
+++ b/IntelSiliconPkg/Include/Ppi/VtdInfo.h
@@ -0,0 +1,40 @@
+/** @file
+  The definition for VTD information PPI.
+
+  This is a lightweight VTd information report in PEI phase.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __VTD_INFO_PPI_H__
+#define __VTD_INFO_PPI_H__
+
+#define EDKII_VTD_INFO_PPI_GUID \
+{ \
+  0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x68, 
0x4a } \
+}
+
+typedef struct _EDKII_VTD_INFO_PPI  EDKII_VTD_INFO_PPI;
+
+#define EDKII_VTD_INFO_PPI_REVISION 0x0001
+
+struct _EDKII_VTD_INFO_PPI {
+  UINT64  Revision;
+  UINT8   HostAddressWidth;
+  UINT8   Reserved[3];
+  UINT32  VTdEngineCount;
+  UINT64  VTdEngineAddress[1];
+};
+
+extern EFI_GUID gEdkiiVTdInfoPpiGuid;
+
+#endif
+
-- 
2.7.4.windows.1

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[edk2] [PATCH 06/11] IntelSiliconPkg/dec: Add VTD_INFO PPI GUID

[Jiewen Yao]

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelSiliconPkg.dec | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec 
b/IntelSiliconPkg/IntelSiliconPkg.dec
index 2fc6379..941380a 100644
--- a/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -33,6 +33,9 @@
   # Generic DXE Library / Driver can locate HOB(s) and add SMBIOS records into 
SMBIOS table
   gIntelSmbiosDataHobGuid = { 0x798e722e, 0x15b2, 0x4e13, { 0x8a, 
0xe9, 0x6b, 0xa3, 0x0f, 0xf7, 0xf1, 0x67 }}
 
+[Ppis]
+  gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 
0xaf, 0x2b, 0x25, 0x68, 0x4a } }
+
 [Protocols]
   gEdkiiPlatformVTdPolicyProtocolGuid = { 0x3d17e448, 0x466, 0x4e20, { 0x99, 
0x9f, 0xb2, 0xe1, 0x34, 0x88, 0xee, 0x22 }}
 
-- 
2.7.4.windows.1

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[edk2] [PATCH 10/11] IntelSiliconPkg/dsc: Add PlatformVTdInfoSamplePei.

[Jiewen Yao]

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelSiliconPkg.dsc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/IntelSiliconPkg/IntelSiliconPkg.dsc 
b/IntelSiliconPkg/IntelSiliconPkg.dsc
index 33e822f..422e202 100644
--- a/IntelSiliconPkg/IntelSiliconPkg.dsc
+++ b/IntelSiliconPkg/IntelSiliconPkg.dsc
@@ -82,6 +82,7 @@
   IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf
   IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.inf
   IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.inf
+  IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
 
 [BuildOptions]
   *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
-- 
2.7.4.windows.1

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[edk2] [PATCH 03/11] IntelSiliconPkg/Vtd.h: Add definition for PMR.

[Jiewen Yao]

Add missing PMR definition in VTd spec.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Include/IndustryStandard/Vtd.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/IntelSiliconPkg/Include/IndustryStandard/Vtd.h 
b/IntelSiliconPkg/Include/IndustryStandard/Vtd.h
index 3b7012c..cfead61 100644
--- a/IntelSiliconPkg/Include/IndustryStandard/Vtd.h
+++ b/IntelSiliconPkg/Include/IndustryStandard/Vtd.h
@@ -247,6 +247,12 @@ typedef union {
 
 #define R_FRCD_REG   0x00 // + FRO
 
+#define R_PMEN_ENABLE_REG 0x64
+#define R_PMEN_LOW_BASE_REG   0x68
+#define R_PMEN_LOW_LIMITE_REG 0x6C
+#define R_PMEN_HIGH_BASE_REG  0x70
+#define R_PMEN_HIGH_LIMITE_REG0x78
+
 typedef union {
   struct {
 UINT8 ND:3; // Number of domains supported
-- 
2.7.4.windows.1

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[edk2] [PATCH 01/11] MdeModulePkg/Include: Add IOMMU_PPI.

[Jiewen Yao]

This IOMMU_PPI is to provide IOMMU abstraction in PEI.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdeModulePkg/Include/Ppi/IoMmu.h | 196 
 1 file changed, 196 insertions(+)

diff --git a/MdeModulePkg/Include/Ppi/IoMmu.h b/MdeModulePkg/Include/Ppi/IoMmu.h
new file mode 100644
index 000..5303d68
--- /dev/null
+++ b/MdeModulePkg/Include/Ppi/IoMmu.h
@@ -0,0 +1,196 @@
+/** @file
+  PEI IOMMU PPI.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available 
under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef __PEI_IOMMU_H__
+#define __PEI_IOMMU_H__
+
+//
+// for EFI_ALLOCATE_TYPE
+//
+#include 
+
+//
+// Include protocol for common definition
+//   EDKII_IOMMU_ACCESS_xxx
+//   EDKII_IOMMU_OPERATION
+//
+#include 
+
+//
+// IOMMU Ppi GUID value
+//
+#define EDKII_IOMMU_PPI_GUID \
+{ \
+  0x70b0af26, 0xf847, 0x4bb6, { 0xaa, 0xb9, 0xcd, 0xe8, 0x4f, 0xc6, 0x14, 
0x31 } \
+}
+
+//
+// Forward reference for pure ANSI compatability
+//
+typedef struct _EDKII_IOMMU_PPI  EDKII_IOMMU_PPI;
+
+//
+// Revision The revision to which the IOMMU interface adheres.
+//  All future revisions must be backwards compatible.
+//  If a future version is not back wards compatible it is not the 
same GUID.
+//
+#define EDKII_IOMMU_PPI_REVISION 0x0001
+
+/**
+  Set IOMMU attribute for a system memory.
+
+  If the IOMMU PPI exists, the system memory cannot be used
+  for DMA by default.
+
+  When a device requests a DMA access for a system memory,
+  the device driver need use SetAttribute() to update the IOMMU
+  attribute to request DMA access (read and/or write).
+
+  @param[in]  This  The PPI instance pointer.
+  @param[in]  Mapping   The mapping value returned from Map().
+  @param[in]  IoMmuAccess   The IOMMU access.
+
+  @retval EFI_SUCCESSThe IoMmuAccess is set for the memory range 
specified by DeviceAddress and Length.
+  @retval EFI_INVALID_PARAMETER  Mapping is not a value that was returned by 
Map().
+  @retval EFI_INVALID_PARAMETER  IoMmuAccess specified an illegal combination 
of access.
+  @retval EFI_UNSUPPORTEDThe bit mask of IoMmuAccess is not supported 
by the IOMMU.
+  @retval EFI_UNSUPPORTEDThe IOMMU does not support the memory range 
specified by Mapping.
+  @retval EFI_OUT_OF_RESOURCES   There are not enough resources available to 
modify the IOMMU access.
+  @retval EFI_DEVICE_ERROR   The IOMMU device reported an error while 
attempting the operation.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_PEI_IOMMU_SET_ATTRIBUTE)(
+  IN EDKII_IOMMU_PPI   *This,
+  IN VOID  *Mapping,
+  IN UINT64IoMmuAccess
+  );
+
+/**
+  Provides the controller-specific addresses required to access system memory 
from a
+  DMA bus master.
+
+  @param  This  The PPI instance pointer.
+  @param  Operation Indicates if the bus master is going to read 
or write to system memory.
+  @param  HostAddress   The system memory address to map to the PCI 
controller.
+  @param  NumberOfBytes On input the number of bytes to map. On output 
the number of bytes
+that were mapped.
+  @param  DeviceAddress The resulting map address for the bus master 
PCI controller to use to
+access the hosts HostAddress.
+  @param  Mapping   A resulting value to pass to Unmap().
+
+  @retval EFI_SUCCESS   The range was mapped for the returned 
NumberOfBytes.
+  @retval EFI_UNSUPPORTED   The HostAddress cannot be mapped as a common 
buffer.
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a 
lack of resources.
+  @retval EFI_DEVICE_ERROR  The system hardware could not map the 
requested address.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_PEI_IOMMU_MAP)(
+  IN EDKII_IOMMU_PPI*This,
+  IN EDKII_IOMMU_OPERATION  Operation,
+  IN VOID   *HostAddress,
+  IN OUT UINTN  *NumberOfBytes,
+  OUTEFI_PHYSICAL_ADDRESS   *DeviceAddress,
+  OUTVOID   **Mapping
+  );
+
+/**
+  Completes the Map() operation and releases any corresponding resources.
+
+  @param  This  The PPI instance point

[edk2] [PATCH 08/11] IntelSiliconPkg/dsc: Add IntelVTdPmrPeim.

[Jiewen Yao]

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelSiliconPkg.dsc | 9 +
 1 file changed, 9 insertions(+)

diff --git a/IntelSiliconPkg/IntelSiliconPkg.dsc 
b/IntelSiliconPkg/IntelSiliconPkg.dsc
index 9a9920f..33e822f 100644
--- a/IntelSiliconPkg/IntelSiliconPkg.dsc
+++ b/IntelSiliconPkg/IntelSiliconPkg.dsc
@@ -40,6 +40,14 @@
   SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
   
CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
 
+[LibraryClasses.common.PEIM]
+  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+  
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+
+  
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+
 [LibraryClasses.common.DXE_DRIVER]
   
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
   
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
@@ -72,6 +80,7 @@
 [Components]
   IntelSiliconPkg/Library/DxeSmbiosDataHobLib/DxeSmbiosDataHobLib.inf
   IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf
+  IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.inf
   IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.inf
 
 [BuildOptions]
-- 
2.7.4.windows.1

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[edk2] [PATCH 0/2] Add VTd policy PCD

[Jiewen Yao]

Add PcdVTdPolicyPropertyMask
BIT0: This is to control if a platform wants to enable VTd
based protection during boot.
BIT1: This is to control if a platform wants to keep VTd
enabled at ExitBootService.

The default configuration is BIT0:1, BIT1:0.

Jiewen Yao (2):
  IntelSiliconPkg/dec: Add VTd policy PCD
  IntelSiliconPkg/IntelVtd: Consume VTd policy PCD

 IntelSiliconPkg/IntelSiliconPkg.dec | 6 ++
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.c | 7 +--
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c   | 4 
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf | 3 +++
 4 files changed, 18 insertions(+), 2 deletions(-)

-- 
2.7.4.windows.1

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[edk2] [PATCH 2/2] IntelSiliconPkg/IntelVtd: Consume VTd policy PCD

[Jiewen Yao]

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.c | 7 +--
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c   | 4 
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf | 3 +++
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/IntelSiliconPkg/IntelVTdDxe/DmaProtection.c 
b/IntelSiliconPkg/IntelVTdDxe/DmaProtection.c
index 82ed4d2..f5de01f 100644
--- a/IntelSiliconPkg/IntelVTdDxe/DmaProtection.c
+++ b/IntelSiliconPkg/IntelVTdDxe/DmaProtection.c
@@ -437,8 +437,11 @@ OnExitBootServices (
 {
   DEBUG ((DEBUG_INFO, "Vtd OnExitBootServices\n"));
   DumpVtdRegsAll ();
-  DisableDmar ();
-  DumpVtdRegsAll ();
+
+  if ((PcdGet8(PcdVTdPolicyPropertyMask) & BIT1) == 0) {
+DisableDmar ();
+DumpVtdRegsAll ();
+  }
 }
 
 /**
diff --git a/IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c 
b/IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c
index 24b88c3..64693a8 100644
--- a/IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c
+++ b/IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c
@@ -352,6 +352,10 @@ IntelVTdInitialize (
   EFI_STATUS  Status;
   EFI_HANDLE  Handle;
 
+  if ((PcdGet8(PcdVTdPolicyPropertyMask) & BIT0) == 0) {
+return EFI_UNSUPPORTED;
+  }
+
   InitializeDmaProtection ();
 
   Handle = NULL;
diff --git a/IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf 
b/IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf
index 697932e..d45fd67 100644
--- a/IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf
+++ b/IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf
@@ -73,6 +73,9 @@
   gEfiPciEnumerationCompleteProtocolGuid  ## CONSUMES
   gEdkiiPlatformVTdPolicyProtocolGuid ## SOMETIMES_CONSUMES
 
+[Pcd]
+  gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask   ## CONSUMES
+
 [Depex]
   gEfiPciRootBridgeIoProtocolGuid AND
   gEfiAcpiSdtProtocolGuid
-- 
2.7.4.windows.1

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[edk2] [PATCH 1/2] IntelSiliconPkg/dec: Add VTd policy PCD

[Jiewen Yao]

BIT0: This is to control if a platform wants to enable VTd
based protection during boot.
BIT1: This is to control if a platform wants to keep VTd
enabled at ExitBootService.

The default configuration is BIT0:1, BIT1:0.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelSiliconPkg.dec | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec 
b/IntelSiliconPkg/IntelSiliconPkg.dec
index 663a232..2fc6379 100644
--- a/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -44,3 +44,9 @@
   # { 0x56752da9, 0xde6b, 0x4895, 0x88, 0x19, 0x19, 0x45, 0xb6, 0xb7, 0x6c, 
0x22 }
   gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid|{ 0xa9, 0x2d, 
0x75, 0x56, 0x6b, 0xde, 0x95, 0x48, 0x88, 0x19, 0x19, 0x45, 0xb6, 0xb7, 0x6c, 
0x22 }|VOID*|0x0001
 
+  ## The mask is used to control VTd behavior.
+  #  BIT0: Enable IOMMU during boot.
+  #  BIT1: Enable IOMMU on exit boot service.
+  # @Prompt The policy for VTd driver behavior.
+  gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|1|UINT8|0x0002
+
-- 
2.7.4.windows.1

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[edk2] [PATCH 1/2] IntelSiliconPkg/Vtd: Support CSM usage.

[Jiewen Yao]

Remove zero address check in IoMmuMap.
The reason is that a CSM legacy driver may use legacy memory for DMA.
As such, the legacyBios need allow below 1M to the legacy device.

This patch also fixed some typo.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelVTdDxe/BmDma.c| 8 
 IntelSiliconPkg/IntelVTdDxe/TranslationTable.c | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/IntelSiliconPkg/IntelVTdDxe/BmDma.c 
b/IntelSiliconPkg/IntelVTdDxe/BmDma.c
index 5dcee00..7a5f361 100644
--- a/IntelSiliconPkg/IntelVTdDxe/BmDma.c
+++ b/IntelSiliconPkg/IntelVTdDxe/BmDma.c
@@ -77,14 +77,14 @@ IoMmuMap (
   EFI_PHYSICAL_ADDRESS  DmaMemoryTop;
   BOOLEAN   NeedRemap;
 
-  DEBUG ((DEBUG_VERBOSE, "IoMmuMap: ==> 0x%08x - 0x%08x (%x)\n", HostAddress, 
NumberOfBytes, Operation));
-
-  if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL ||
+  if (NumberOfBytes == NULL || DeviceAddress == NULL ||
   Mapping == NULL) {
 DEBUG ((DEBUG_ERROR, "IoMmuMap: %r\n", EFI_INVALID_PARAMETER));
 return EFI_INVALID_PARAMETER;
   }
 
+  DEBUG ((DEBUG_VERBOSE, "IoMmuMap: ==> 0x%08x - 0x%08x (%x)\n", HostAddress, 
*NumberOfBytes, Operation));
+
   //
   // Make sure that Operation is valid
   //
@@ -135,7 +135,7 @@ IoMmuMap (
 if (NeedRemap) {
   //
   // Common Buffer operations can not be remapped.  If the common buffer
-  // if above 4GB, then it is not possible to generate a mapping, so return
+  // is above 4GB, then it is not possible to generate a mapping, so return
   // an error.
   //
   DEBUG ((DEBUG_ERROR, "IoMmuMap: %r\n", EFI_UNSUPPORTED));
diff --git a/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c 
b/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c
index cd3111c..ccecc95 100644
--- a/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c
+++ b/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c
@@ -891,7 +891,7 @@ SetAccessAttribute (
 
   SecondLevelPagingEntry = NULL;
 
-  DEBUG ((DEBUG_INFO,"SetAccessAttribute (S%04x B%02x D%02x F%02x) (0x%016lx - 
0x%08x, %x)\n", Segment, SourceId.Bits.Bus, SourceId.Bits.Device, 
SourceId.Bits.Function, BaseAddress, (UINTN)Length, IoMmuAccess));
+  DEBUG ((DEBUG_VERBOSE,"SetAccessAttribute (S%04x B%02x D%02x F%02x) 
(0x%016lx - 0x%08x, %x)\n", Segment, SourceId.Bits.Bus, SourceId.Bits.Device, 
SourceId.Bits.Function, BaseAddress, (UINTN)Length, IoMmuAccess));
 
   VtdIndex = FindVtdIndexByPciDevice (Segment, SourceId, , 
);
   if (VtdIndex == (UINTN)-1) {
-- 
2.7.4.windows.1

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[edk2] [PATCH 2/2] IntelFramdworkModulePkg/LegacyBios: Add IoMmu Support.

[Jiewen Yao]

If IOMMU is enabled, the legacy BIOS need allow the legacy memory
access by the legacy device.
The legacy memory is below 1M memory and HighPmm memory.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf |  1 +
 IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h |  1 +
 IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c   | 72 
+++-
 3 files changed, 73 insertions(+), 1 deletion(-)

diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf 
b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf
index 4ca412a..48473a0 100644
--- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf
+++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf
@@ -137,6 +137,7 @@
   gEfiLegacyBiosProtocolGuid## PRODUCES
   gEfiSerialIoProtocolGuid  ## CONSUMES
   gEfiSioProtocolGuid   ## CONSUMES
+  gEdkiiIoMmuProtocolGuid   ## CONSUMES
 
 [Pcd]
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion  ## 
CONSUMES
diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h 
b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h
index 069646b..fe9dd74 100644
--- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h
+++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h
@@ -47,6 +47,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c 
b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c
index c4c77ec..8ffdf0c 100644
--- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c
+++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c
@@ -41,7 +41,7 @@ BOOLEAN mIgnoreBbsUpdateFlag;
 BOOLEAN mVgaInstallationInProgress  = FALSE;
 UINT32  mRomCount   = 0x00;
 ROM_INSTANCE_ENTRY  mRomEntry[ROM_MAX_ENTRIES];
-
+EDKII_IOMMU_PROTOCOL*mIoMmu;
 
 /**
   Query shadowed legacy ROM parameters registered by RomShadow() previously.
@@ -2697,6 +2697,61 @@ Done:
 }
 
 /**
+  Let IOMMU grant DMA access for the PCI device.
+
+  @param  PciHandle The EFI handle for the PCI device.
+  @param  HostAddress   The system memory address to map to the PCI 
controller.
+  @param  NumberOfBytes The number of bytes to map.
+
+  @retval EFI_SUCCESS  The DMA access is granted.
+**/
+EFI_STATUS
+IoMmuGrantAccess (
+  IN  EFI_HANDLEPciHandle,
+  IN  EFI_PHYSICAL_ADDRESS  HostAddress,
+  IN  UINTN NumberOfBytes
+  )
+{
+  EFI_PHYSICAL_ADDRESSDeviceAddress;
+  VOID*Mapping;
+  EFI_STATUS  Status;
+
+  if (PciHandle == NULL) {
+return EFI_UNSUPPORTED;
+  }
+
+  Status = EFI_SUCCESS;
+  if (mIoMmu == NULL) {
+gBS->LocateProtocol (, NULL, (VOID **));
+  }
+  if (mIoMmu != NULL) {
+Status = mIoMmu->Map (
+   mIoMmu,
+   EdkiiIoMmuOperationBusMasterCommonBuffer,
+   (VOID *)(UINTN)HostAddress,
+   ,
+   ,
+   
+   );
+if (EFI_ERROR(Status)) {
+  DEBUG ((DEBUG_ERROR, "LegacyPci - IoMmuMap - %r\n", Status));
+} else {
+  ASSERT (DeviceAddress == HostAddress);
+  Status = mIoMmu->SetAttribute (
+ mIoMmu,
+ PciHandle,
+ Mapping,
+ EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE
+ );
+  if (EFI_ERROR(Status)) {
+DEBUG ((DEBUG_ERROR, "LegacyPci - IoMmuSetAttribute - %r\n", Status));
+  }
+}
+  }
+  return Status;
+}
+
+/**
   Load a legacy PC-AT OPROM on the PciHandle device. Return information
   about how many disks were added by the OPROM and the shadow address and
   size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C:
@@ -2978,6 +3033,21 @@ LegacyBiosInstallPciRom (
   RuntimeImageLength = Pcir->MaxRuntimeImageLength * 512;
 }
   }
+
+  //
+  // Grant access for below 1M
+  // BDA/EBDA/LowPMM and scratch memory for OPROM.
+  //
+  IoMmuGrantAccess (PciHandle, 0, SIZE_1MB);
+  //
+  // Grant access for HiPmm
+  //
+  IoMmuGrantAccess (
+PciHandle,
+Private->IntThunk->EfiToLegacy16InitTable.HiPmmMemory,
+Private->IntThunk->EfiToLegacy16InitTable.HiPmmMemorySizeInBytes
+);
+
   //
   /

[edk2] [PATCH 0/2] Enable IOMMU for CSMM

[Jiewen Yao]

This serial patch is to enable IOMMU support for CSM.

Jiewen Yao (2):
  IntelSiliconPkg/Vtd: Support CSM usage.
  IntelFramdworkModulePkg/LegacyBios: Add IoMmu Support.

 IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf |  1 +
 IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h |  1 +
 IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c   | 72 
+++-
 IntelSiliconPkg/IntelVTdDxe/BmDma.c |  8 +--
 IntelSiliconPkg/IntelVTdDxe/TranslationTable.c  |  2 +-
 5 files changed, 78 insertions(+), 6 deletions(-)

-- 
2.7.4.windows.1

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[edk2] [PATCH 3/3] IntelSiliconPkg/PlatformVTdSample: update ExceptionDevice

[Jiewen Yao]

Add sample for device scope based exception list
and PCI vendor id based exception list.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c | 80 
+---
 1 file changed, 70 insertions(+), 10 deletions(-)

diff --git a/IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c 
b/IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c
index f181b94..95e0f3a 100644
--- a/IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c
+++ b/IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c
@@ -27,6 +27,8 @@
 #include 
 #include 
 
+#include 
+
 typedef struct {
   ACPI_EXTENDED_HID_DEVICE_PATH  I2cController;
   UINT8  HidStr[8];
@@ -137,10 +139,57 @@ PLATFORM_PCI_BRIDGE_DEVICE_PATH 
mPlatformPciBridgeDevicePath = {
   PLATFORM_END_ENTIRE
 };
 
-EDKII_PLATFORM_VTD_DEVICE_INFO  mExceptionDeviceList[] = {
+#pragma pack(1)
+
+typedef struct {
+  EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO ExceptionDeviceInfo;
+  EDKII_PLATFORM_VTD_DEVICE_SCOPE  DeviceScope;
+  EFI_ACPI_DMAR_PCI_PATH   PciBridge;
+  EFI_ACPI_DMAR_PCI_PATH   PciDevice;
+} PLATFORM_EXCEPTION_DEVICE_SCOPE_STRUCT;
+
+typedef struct {
+  EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO ExceptionDeviceInfo;
+  EDKII_PLATFORM_VTD_PCI_DEVICE_ID PciDeviceId;
+} PLATFORM_EXCEPTION_PCI_DEVICE_ID_STRUCT;
+
+#pragma pack()
+
+PLATFORM_EXCEPTION_DEVICE_SCOPE_STRUCT  mExceptionDeviceScopeList[] = {
   {
-0x0, // Segment
-{{0x00, 0x00, 0x02}} // Function, Device, Bus
+{
+  EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO_TYPE_DEVICE_SCOPE,
+  sizeof(PLATFORM_EXCEPTION_DEVICE_SCOPE_STRUCT)
+},  // ExceptionDeviceInfo
+{
+  0,// SegmentNumber
+  {
+EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,  // Type
+sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +
+  2 * sizeof(EFI_ACPI_DMAR_PCI_PATH),   // Length
+0,  // Reserved2
+0,  // EnumerationId
+0,  // StartBusNumber
+  },
+},  // DeviceScope
+{ 0x1C, 1 },// PciBridge
+{ 0x0,  0 },// PciDevice
+  },
+};
+
+PLATFORM_EXCEPTION_PCI_DEVICE_ID_STRUCT  mExceptionPciDeviceIdList[] = {
+  {
+{
+  EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO_TYPE_PCI_DEVICE_ID,
+  sizeof(PLATFORM_EXCEPTION_DEVICE_SCOPE_STRUCT)
+},  // ExceptionDeviceInfo
+{
+  0x8086,   // VendorId
+  0x9D2F,   // DeviceId
+  0x21, // RevisionId
+  0x8086,   // 
SubsystemVendorId
+  0x7270,   // 
SubsystemDeviceId
+},
   },
 };
 
@@ -269,6 +318,7 @@ PlatformVTdGetDeviceId (
   @param[in]  This  The protocol instance pointer.
   @param[out] DeviceInfoCount   The count of the list of DeviceInfo.
   @param[out] DeviceInfoA callee allocated buffer to hold a list 
of DeviceInfo.
+Each DeviceInfo pointer points to 
EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO.
 
   @retval EFI_SUCCESS   The DeviceInfoCount and DeviceInfo are 
returned.
   @retval EFI_INVALID_PARAMETER DeviceInfoCount is NULL, or DeviceInfo is NULL.
@@ -280,7 +330,7 @@ EFIAPI
 PlatformVTdGetExceptionDeviceList (
   IN  EDKII_PLATFORM_VTD_POLICY_PROTOCOL   *This,
   OUT UINTN*DeviceInfoCount,
-  OUT EDKII_PLATFORM_VTD_DEVICE_INFO   **DeviceInfo
+  OUT VOID **DeviceInfo
   )
 {
   DEBUG ((DEBUG_VERBOSE, "PlatformVTdGetExceptionDeviceList\n"));
@@ -289,13 +339,23 @@ PlatformVTdGetExceptionDeviceList (
 return EFI_INVALID_PARAMETER;
   }
 
-  *DeviceInfo = AllocateZeroPool (sizeof(mExceptionDeviceList));
-  if (*DeviceInfo == NULL) {
-return EFI_OUT_OF_RESOURCES;
-  }
-  CopyMem (*DeviceInfo, mExceptionDeviceList, sizeof(mExceptionDeviceList));
+  if (0) {
+*DeviceInfo = AllocateZeroPool (sizeof(mExceptionDeviceScopeList));
+if (*DeviceInfo == NULL) {
+  return EFI_OUT_OF_RESOURCES;
+}
+CopyMem (*DeviceInfo, mExceptionDeviceScopeList, 
sizeof(mExceptionDeviceScopeList));
+
+*DeviceInfoCount = ARRAY_SIZE(mExceptionDeviceScopeList);
+  } else {
+*DeviceInfo = AllocateZeroPool (sizeof(mExceptionPciDeviceIdList))

[edk2] [PATCH 0/3] Add flexible exception device reporting

[Jiewen Yao]

During VTd enabling, we notice a platform may want to
add exception device based upon VendorId/DeviceId.

We update GetExceptionDeviceList() function to support both style.

1) Support Device scope based reporting:
Such as, Seg:0/StartBus:0/(Dev:1C|Func:0)/(Dev:0|Func:0)

2) Support PCI VendorId/DeviceId based reporting
Such as, VID:8086|DID:9D2F|Rev:21|SVID:8086|SDID:7270

Jiewen Yao (3):
  IntelSiliconPkg/header: update PlatformVtdPolicy
  IntelSiliconPkg/IntelVTd: update PlatformVtdPolicy
  IntelSiliconPkg/PlatformVTdSample: update ExceptionDevice

 IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h|  51 -
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.c | 143 -
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.h | 119 ---
 IntelSiliconPkg/IntelVTdDxe/DmarAcpiTable.c |  48 +++--
 IntelSiliconPkg/IntelVTdDxe/PciInfo.c   | 212 

 IntelSiliconPkg/IntelVTdDxe/TranslationTable.c  |  28 +--
 IntelSiliconPkg/IntelVTdDxe/TranslationTableEx.c|  20 +-
 IntelSiliconPkg/IntelVTdDxe/VtdReg.c|  14 +-
 IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c |  80 +++-
 9 files changed, 543 insertions(+), 172 deletions(-)

-- 
2.7.4.windows.1

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[edk2] [PATCH 2/3] IntelSiliconPkg/IntelVTd: update PlatformVtdPolicy

[Jiewen Yao]

1. Handle flexible exception list format.
1.1 Handle DeviceScope based device info.
1.2 Handle PciDeviceId based device info.
2. Reorg the PCI_DEVICE_INFORMATION
2.1 Merge data pointer reduce allocation times
2.2 Add PCI device id to PCI_DEVICE_INFORMATION
2.3 Rename PciDescriptor to avoid confusing.
3. Fix the debug message too long issue.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.c  | 143 -
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.h  | 119 ---
 IntelSiliconPkg/IntelVTdDxe/DmarAcpiTable.c  |  48 +++--
 IntelSiliconPkg/IntelVTdDxe/PciInfo.c| 212 
 IntelSiliconPkg/IntelVTdDxe/TranslationTable.c   |  28 +--
 IntelSiliconPkg/IntelVTdDxe/TranslationTableEx.c |  20 +-
 IntelSiliconPkg/IntelVTdDxe/VtdReg.c |  14 +-
 7 files changed, 423 insertions(+), 161 deletions(-)

diff --git a/IntelSiliconPkg/IntelVTdDxe/DmaProtection.c 
b/IntelSiliconPkg/IntelVTdDxe/DmaProtection.c
index f0628b5..82ed4d2 100644
--- a/IntelSiliconPkg/IntelVTdDxe/DmaProtection.c
+++ b/IntelSiliconPkg/IntelVTdDxe/DmaProtection.c
@@ -152,6 +152,132 @@ ReturnUefiMemoryMap (
 }
 
 /**
+  The scan bus callback function to always enable page attribute.
+
+  @param[in]  Context   The context of the callback.
+  @param[in]  Segment   The segment of the source.
+  @param[in]  Bus   The bus of the source.
+  @param[in]  DeviceThe device of the source.
+  @param[in]  Function  The function of the source.
+
+  @retval EFI_SUCCESS   The VTd entry is updated to always enable all 
DMA access for the specific device.
+**/
+EFI_STATUS
+EFIAPI
+ScanBusCallbackAlwaysEnablePageAttribute (
+  IN VOID   *Context,
+  IN UINT16 Segment,
+  IN UINT8  Bus,
+  IN UINT8  Device,
+  IN UINT8  Function
+  )
+{
+  VTD_SOURCE_ID   SourceId;
+  EFI_STATUS  Status;
+
+  SourceId.Bits.Bus = Bus;
+  SourceId.Bits.Device = Device;
+  SourceId.Bits.Function = Function;
+  Status = AlwaysEnablePageAttribute (Segment, SourceId);
+  return Status;
+}
+
+/**
+  Always enable the VTd page attribute for the device in the DeviceScope.
+
+  @param[in]  DeviceScope  the input device scope data structure
+
+  @retval EFI_SUCCESS   The VTd entry is updated to always enable all 
DMA access for the specific device in the device scope.
+**/
+EFI_STATUS
+AlwaysEnablePageAttributeDeviceScope (
+  IN  EDKII_PLATFORM_VTD_DEVICE_SCOPE   *DeviceScope
+  )
+{
+  UINT8 Bus;
+  UINT8 Device;
+  UINT8 Function;
+  VTD_SOURCE_ID SourceId;
+  UINT8 SecondaryBusNumber;
+  EFI_STATUSStatus;
+
+  Status = GetPciBusDeviceFunction (DeviceScope->SegmentNumber, 
>DeviceScope, , , );
+
+  if (DeviceScope->DeviceScope.Type == 
EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE) {
+//
+// Need scan the bridge and add all devices.
+//
+SecondaryBusNumber = PciSegmentRead8 
(PCI_SEGMENT_LIB_ADDRESS(DeviceScope->SegmentNumber, Bus, Device, Function, 
PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
+Status = ScanPciBus (NULL, DeviceScope->SegmentNumber, SecondaryBusNumber, 
ScanBusCallbackAlwaysEnablePageAttribute);
+return Status;
+  } else {
+SourceId.Bits.Bus  = Bus;
+SourceId.Bits.Device   = Device;
+SourceId.Bits.Function = Function;
+Status = AlwaysEnablePageAttribute (DeviceScope->SegmentNumber, SourceId);
+return Status;
+  }
+}
+
+/**
+  Always enable the VTd page attribute for the device matching DeviceId.
+
+  @param[in]  PciDeviceId  the input PCI device ID
+
+  @retval EFI_SUCCESS   The VTd entry is updated to always enable all 
DMA access for the specific device matching DeviceId.
+**/
+EFI_STATUS
+AlwaysEnablePageAttributePciDeviceId (
+  IN  EDKII_PLATFORM_VTD_PCI_DEVICE_ID   *PciDeviceId
+  )
+{
+  UINTNVtdIndex;
+  UINTNPciIndex;
+  PCI_DEVICE_DATA  *PciDeviceData;
+  EFI_STATUS   Status;
+
+  for (VtdIndex = 0; VtdIndex < mVtdUnitNumber; VtdIndex++) {
+for (PciIndex = 0; PciIndex < 
mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDeviceDataNumber; PciIndex++) {
+  PciDeviceData = 
[VtdIndex].PciDeviceInfo.PciDeviceData[PciIndex];
+
+  if (((PciDeviceId->VendorId == 0x) || (PciDeviceId->VendorId == 
PciDeviceData->PciDeviceId.VendorId)) &&
+  ((PciDeviceId->DeviceId == 0x) || (PciDeviceId->DeviceId == 
PciDeviceData->PciDeviceId.DeviceId)) &&
+  ((PciDeviceId->RevisionId == 0xFF) || (PciDeviceId->RevisionId == 
PciDeviceData->PciDeviceId.RevisionId)) &&
+  ((PciDevic

[edk2] [PATCH 1/3] IntelSiliconPkg/header: update PlatformVtdPolicy

[Jiewen Yao]

Add flexible exception list format:
1) Support Device scope based reporting:
Such as, Seg:0/StartBus:0/(Dev:1C|Func:0)/(Dev:0|Func:0)

2) Support PCI VendorId/DeviceId based reporting
Such as, VID:8086|DID:9D2F|Rev:21|SVID:8086|SDID:7270

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h | 51 +++-
 1 file changed, 50 insertions(+), 1 deletion(-)

diff --git a/IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h 
b/IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h
index 29774c1..441da5c 100644
--- a/IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h
+++ b/IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h
@@ -16,6 +16,7 @@
 #define __PLATFORM_VTD_POLICY_PROTOCOL_H__
 
 #include 
+#include 
 
 #define EDKII_PLATFORM_VTD_POLICY_PROTOCOL_GUID \
 { \
@@ -66,6 +67,53 @@ EFI_STATUS
   OUT EDKII_PLATFORM_VTD_DEVICE_INFO   *DeviceInfo
   );
 
+#pragma pack(1)
+
+typedef struct {
+  //
+  // The segment number of the device
+  //
+  UINT16  SegmentNumber;
+  //
+  // Device scope definition in DMAR table
+  //
+  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER DeviceScope;
+  //
+  // Pci path definition in DMAR table
+  //
+//EFI_ACPI_DMAR_PCI_PATH  PciPath[];
+} EDKII_PLATFORM_VTD_DEVICE_SCOPE;
+
+typedef struct {
+  UINT16   VendorId;
+  UINT16   DeviceId;
+  UINT8RevisionId;
+  UINT16   SubsystemVendorId;
+  UINT16   SubsystemDeviceId;
+} EDKII_PLATFORM_VTD_PCI_DEVICE_ID;
+
+#define EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO_TYPE_END   0
+#define EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO_TYPE_DEVICE_SCOPE  1
+#define EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO_TYPE_PCI_DEVICE_ID 2
+
+typedef struct {
+  //
+  // EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO_TYPE_xxx defined above.
+  //
+  UINT8 Type;
+  //
+  // The length of the full data structure including 
EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO and Data.
+  //
+  UINT8 Length;
+  //
+  // Data can be EDKII_PLATFORM_VTD_DEVICE_SCOPE or 
EDKII_PLATFORM_VTD_PCI_DEVICE_ID
+  //
+//UINT8 Data[Length - 
sizeof(EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO)];
+} EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO;
+
+#pragma pack()
+
+
 /**
   Get a list of the exception devices.
 
@@ -74,6 +122,7 @@ EFI_STATUS
   @param[in]  This  The protocol instance pointer.
   @param[out] DeviceInfoCount   The count of the list of DeviceInfo.
   @param[out] DeviceInfoA callee allocated buffer to hold a list 
of DeviceInfo.
+Each DeviceInfo pointer points to 
EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO.
 
   @retval EFI_SUCCESS   The DeviceInfoCount and DeviceInfo are 
returned.
   @retval EFI_INVALID_PARAMETER DeviceInfoCount is NULL, or DeviceInfo is NULL.
@@ -85,7 +134,7 @@ EFI_STATUS
 (EFIAPI *EDKII_PLATFORM_VTD_POLICY_GET_EXCEPTION_DEVICE_LIST) (
   IN  EDKII_PLATFORM_VTD_POLICY_PROTOCOL   *This,
   OUT UINTN*DeviceInfoCount,
-  OUT EDKII_PLATFORM_VTD_DEVICE_INFO   **DeviceInfo
+  OUT VOID **DeviceInfo
   );
 
 struct _EDKII_PLATFORM_VTD_POLICY_PROTOCOL {
-- 
2.7.4.windows.1

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[edk2] [PATCH V2 2/2] IntelSiliconPkg/IntelVTdDxe: Improve performance.

[Jiewen Yao]

This patch is to improve IOMMU performance.
All WBINVD is removed due to performance issue.
CLFLUSH is used to to only flush the context table or
second level page table if they are changed.

This patch also removed some unused functions.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.h  |  57 ++---
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c|  10 +
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf  |   3 +
 IntelSiliconPkg/IntelVTdDxe/PciInfo.c|  12 +
 IntelSiliconPkg/IntelVTdDxe/TranslationTable.c   |  58 -
 IntelSiliconPkg/IntelVTdDxe/TranslationTableEx.c |   2 +
 IntelSiliconPkg/IntelVTdDxe/VtdReg.c | 260 +++-
 7 files changed, 186 insertions(+), 216 deletions(-)

diff --git a/IntelSiliconPkg/IntelVTdDxe/DmaProtection.h 
b/IntelSiliconPkg/IntelVTdDxe/DmaProtection.h
index 8cfa69c..c3b57a0 100644
--- a/IntelSiliconPkg/IntelVTdDxe/DmaProtection.h
+++ b/IntelSiliconPkg/IntelVTdDxe/DmaProtection.h
@@ -25,6 +25,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 
 #include 
 #include 
@@ -58,6 +61,8 @@ typedef struct {
   UINTN  PciDescriptorMaxNumber;
   BOOLEAN*IsRealPciDevice;
   VTD_SOURCE_ID  *PciDescriptors;
+  // for statistic analysis
+  UINTN  *AccessCount;
 } PCI_DEVICE_INFORMATION;
 
 typedef struct {
@@ -68,6 +73,7 @@ typedef struct {
   VTD_ROOT_ENTRY   *RootEntryTable;
   VTD_EXT_ROOT_ENTRY   *ExtRootEntryTable;
   VTD_SECOND_LEVEL_PAGING_ENTRY*FixedSecondLevelPagingEntry;
+  BOOLEAN  HasDirtyContext;
   BOOLEAN  HasDirtyPages;
   PCI_DEVICE_INFORMATION   PciDeviceInfo;
 } VTD_UNIT_INFORMATION;
@@ -125,40 +131,6 @@ DisableDmar (
   );
 
 /**
-  Invalid VTd IOTLB page.
-
-  @param[in]  VtdIndex  The index of VTd engine.
-  @param[in]  Address   The address of IOTLB page.
-  @param[in]  AddressMode   The address mode of IOTLB page.
-  @param[in]  DomainIdentifier  The domain ID of the source.
-
-  @retval EFI_SUCCESS   VTd IOTLB page is invalidated.
-  @retval EFI_DEVICE_ERROR  VTd IOTLB page is not invalidated.
-**/
-EFI_STATUS
-InvalidateVtdIOTLBPage (
-  IN UINTN  VtdIndex,
-  IN UINT64 Address,
-  IN UINT8  AddressMode,
-  IN UINT16 DomainIdentifier
-  );
-
-/**
-  Invalid VTd IOTLB domain.
-
-  @param[in]  VtdIndex  The index of VTd engine.
-  @param[in]  DomainIdentifier  The domain ID of the source.
-
-  @retval EFI_SUCCESS   VTd IOTLB domain is invalidated.
-  @retval EFI_DEVICE_ERROR  VTd IOTLB domain is not invalidated.
-**/
-EFI_STATUS
-InvalidateVtdIOTLBDomain (
-  IN UINTN  VtdIndex,
-  IN UINT16 DomainIdentifier
-  );
-
-/**
   Invalid VTd global IOTLB.
 
   @param[in]  VtdIndex  The index of VTd engine.
@@ -362,6 +334,7 @@ DumpSecondLevelPagingEntry (
 EFI_STATUS
 SetPageAttribute (
   IN UINTN VtdIndex,
+  IN UINT16DomainIdentifier,
   IN VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry,
   IN UINT64BaseAddress,
   IN UINT64Length,
@@ -500,4 +473,20 @@ AllocateZeroPages (
   IN UINTN  Pages
   );
 
+/**
+  Flush VTD page table and context table memory.
+
+  This action is to make sure the IOMMU engine can get final data in memory.
+
+  @param[in]  VtdIndex  The index used to identify a VTd engine.
+  @param[in]  Base  The base address of memory to be flushed.
+  @param[in]  Size  The size of memory in bytes to be flushed.
+**/
+VOID
+FlushPageTableMemory (
+  IN UINTN  VtdIndex,
+  IN UINTN  Base,
+  IN UINTN  Size
+  );
+
 #endif
diff --git a/IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c 
b/IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c
index d2d..7feaaf5 100644
--- a/IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c
+++ b/IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c
@@ -227,6 +227,7 @@ VTdSetAttribute (
   EFI_STATUS   Status;
   UINT16   Segment;
   VTD_SOURCE_IDSourceId;
+  CHAR8PerfToken[sizeof("VTD(S.B00.D00.F00)")];
 
   DumpVtdIfError ();
 
@@ -239,8 +240,17 @@ VTdSetAttribute (
   DEBUG ((DEBUG_VERBOSE, "PCI(S%x.B%x.D%x.F%x) ", Segment, SourceId.Bits.Bus, 
SourceId.Bits.Device, SourceId.Bits.Function));
   DEBUG ((DEBUG_VERBOSE, "(0x%lx~0x%lx) - %lx\n", DeviceAddress, Length, 
IoMmuAccess));
 
+  PERF_CODE_BEGIN();
+AsciiSPrint (PerfToken, sizeof(PerfToken), "VTD(S%04x.B%02x.D%02x.F%02x)", 
Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function);
+PERF_START (gImageHandle, PerfToken, "IntelVTD", 0);
+  PERF_CODE_END();
+
   Status = SetAccessAttribute (Segment, Source

[edk2] [PATCH V2 1/2] IntelSiliconPkg/dsc: Add CacheMaintenanceLib.

[Jiewen Yao]

It will be used by IntelVTdDxe.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelSiliconPkg.dsc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/IntelSiliconPkg/IntelSiliconPkg.dsc 
b/IntelSiliconPkg/IntelSiliconPkg.dsc
index d837d84..9a9920f 100644
--- a/IntelSiliconPkg/IntelSiliconPkg.dsc
+++ b/IntelSiliconPkg/IntelSiliconPkg.dsc
@@ -38,6 +38,7 @@
   
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
   
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
   SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+  
CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
 
 [LibraryClasses.common.DXE_DRIVER]
   
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
-- 
2.7.4.windows.1

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[edk2] [PATCH V2 0/2] Improve IntelVTd performance.

[Jiewen Yao]

=== V2 =
I found CacheLineFlush() is already defined in CacheMaintenanceLib.

Drop the CpuLib update, but use in CacheMaintenanceLib directly.

=== V1 =
This series patch replace WBINVD with CLFlush
in IntelVTdDxe driver, which improves boot performance.

This patch is validated on Intel Kabylake generation.

Jiewen Yao (2):
  IntelSiliconPkg/dsc: Add CacheMaintenanceLib.
  IntelSiliconPkg/IntelVTdDxe: Improve performance.

 IntelSiliconPkg/IntelSiliconPkg.dsc  |   1 +
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.h  |  57 ++---
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c|  10 +
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf  |   3 +
 IntelSiliconPkg/IntelVTdDxe/PciInfo.c|  12 +
 IntelSiliconPkg/IntelVTdDxe/TranslationTable.c   |  58 -
 IntelSiliconPkg/IntelVTdDxe/TranslationTableEx.c |   2 +
 IntelSiliconPkg/IntelVTdDxe/VtdReg.c | 260 +++-
 8 files changed, 187 insertions(+), 216 deletions(-)

-- 
2.7.4.windows.1

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[edk2] [PATCH 4/4] IntelSiliconPkg/IntelVTdDxe: Improve performance.

[Jiewen Yao]

This patch is to improve IOMMU performance.
All WBINVD is removed due to performance issue.
CLFLUSH is used to to only flush the context table or
second level page table if they are changed.

This patch also removed some unused functions.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.c  |   6 +
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.h  |  61 ++---
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c|  10 +
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf  |   4 +
 IntelSiliconPkg/IntelVTdDxe/PciInfo.c|  12 +
 IntelSiliconPkg/IntelVTdDxe/TranslationTable.c   |  58 +++-
 IntelSiliconPkg/IntelVTdDxe/TranslationTableEx.c |   2 +
 IntelSiliconPkg/IntelVTdDxe/VtdReg.c | 283 +++-
 8 files changed, 213 insertions(+), 223 deletions(-)

diff --git a/IntelSiliconPkg/IntelVTdDxe/DmaProtection.c 
b/IntelSiliconPkg/IntelVTdDxe/DmaProtection.c
index f0628b5..91f34d7 100644
--- a/IntelSiliconPkg/IntelVTdDxe/DmaProtection.c
+++ b/IntelSiliconPkg/IntelVTdDxe/DmaProtection.c
@@ -17,6 +17,8 @@ EFI_ACPI_SDT_PROTOCOL   *mAcpiSdt;
 UINT64  mBelow4GMemoryLimit;
 UINT64  mAbove4GMemoryLimit;
 
+UINTN   mCacheLineSize;
+
 EDKII_PLATFORM_VTD_POLICY_PROTOCOL  *mPlatformVTdPolicy;
 
 /**
@@ -196,6 +198,7 @@ SetupVtd (
   UINTN   Index;
   UINT64  Below4GMemoryLimit;
   UINT64  Above4GMemoryLimit;
+  CPUID_VERSION_INFO_EBX  Ebx;
 
   //
   // PCI Enumeration must be done
@@ -207,6 +210,9 @@ SetupVtd (
   );
   ASSERT_EFI_ERROR (Status);
 
+  AsmCpuid (CPUID_VERSION_INFO, NULL, , NULL, NULL);
+  mCacheLineSize = Ebx.Bits.CacheLineSize;
+
   ReturnUefiMemoryMap (, );
   Below4GMemoryLimit = ALIGN_VALUE_UP(Below4GMemoryLimit, SIZE_256MB);
   DEBUG ((DEBUG_INFO, " Adjusted Below4GMemoryLimit: 0x%016lx\n", 
Below4GMemoryLimit));
diff --git a/IntelSiliconPkg/IntelVTdDxe/DmaProtection.h 
b/IntelSiliconPkg/IntelVTdDxe/DmaProtection.h
index 8cfa69c..f6ce365 100644
--- a/IntelSiliconPkg/IntelVTdDxe/DmaProtection.h
+++ b/IntelSiliconPkg/IntelVTdDxe/DmaProtection.h
@@ -25,6 +25,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 
 #include 
 #include 
@@ -41,6 +44,8 @@
 #include 
 #include 
 
+#include 
+
 #define VTD_64BITS_ADDRESS(Lo, Hi) (LShiftU64 (Lo, 12) | LShiftU64 (Hi, 32))
 
 #define ALIGN_VALUE_UP(Value, Alignment)  (((Value) + (Alignment) - 1) & 
(~((Alignment) - 1)))
@@ -58,6 +63,8 @@ typedef struct {
   UINTN  PciDescriptorMaxNumber;
   BOOLEAN*IsRealPciDevice;
   VTD_SOURCE_ID  *PciDescriptors;
+  // for statistic analysis
+  UINTN  *AccessCount;
 } PCI_DEVICE_INFORMATION;
 
 typedef struct {
@@ -68,6 +75,7 @@ typedef struct {
   VTD_ROOT_ENTRY   *RootEntryTable;
   VTD_EXT_ROOT_ENTRY   *ExtRootEntryTable;
   VTD_SECOND_LEVEL_PAGING_ENTRY*FixedSecondLevelPagingEntry;
+  BOOLEAN  HasDirtyContext;
   BOOLEAN  HasDirtyPages;
   PCI_DEVICE_INFORMATION   PciDeviceInfo;
 } VTD_UNIT_INFORMATION;
@@ -81,6 +89,8 @@ extern VTD_UNIT_INFORMATION *mVtdUnitInformation;
 extern UINT64   mBelow4GMemoryLimit;
 extern UINT64   mAbove4GMemoryLimit;
 
+extern UINTNmCacheLineSize;
+
 extern EDKII_PLATFORM_VTD_POLICY_PROTOCOL   *mPlatformVTdPolicy;
 
 /**
@@ -125,40 +135,6 @@ DisableDmar (
   );
 
 /**
-  Invalid VTd IOTLB page.
-
-  @param[in]  VtdIndex  The index of VTd engine.
-  @param[in]  Address   The address of IOTLB page.
-  @param[in]  AddressMode   The address mode of IOTLB page.
-  @param[in]  DomainIdentifier  The domain ID of the source.
-
-  @retval EFI_SUCCESS   VTd IOTLB page is invalidated.
-  @retval EFI_DEVICE_ERROR  VTd IOTLB page is not invalidated.
-**/
-EFI_STATUS
-InvalidateVtdIOTLBPage (
-  IN UINTN  VtdIndex,
-  IN UINT64 Address,
-  IN UINT8  AddressMode,
-  IN UINT16 DomainIdentifier
-  );
-
-/**
-  Invalid VTd IOTLB domain.
-
-  @param[in]  VtdIndex  The index of VTd engine.
-  @param[in]  DomainIdentifier  The domain ID of the source.
-
-  @retval EFI_SUCCESS   VTd IOTLB domain is invalidated.
-  @retval EFI_DEVICE_ERROR  VTd IOTLB domain is not invalidated.
-**/
-EFI_STATUS
-InvalidateVtdIOTLBDomain (
-  IN UINTN  VtdIndex,
-  IN UINT16 DomainIdentifier
-  );
-
-/**
   Invalid VTd global IOTLB.
 
   @param[in]  VtdIndex  The index of VTd engine.
@@ -362,6 +338,7 @@ DumpSecondLevelPagingEntry (
 EFI_STATUS
 SetPageAttribute (
   IN UINTN VtdIndex,
+  IN UINT16  

[edk2] [PATCH 0/4] Improve IntelVTd performance.

[Jiewen Yao]

This series patch replace WBINVD with CLFlush
in IntelVTdDxe driver, which improves boot performance.

This patch is validated on Intel Kabylake generation.

Jiewen Yao (4):
  MdePkg/CpuLib.h: Add CacheLineFlush function.
  MdePkg/BaseCpuLib: Add CacheLineFlush function.
  IntelSiliconPkg/dsc: Add CpuLib.
  IntelSiliconPkg/IntelVTdDxe: Improve performance.

 IntelSiliconPkg/IntelSiliconPkg.dsc|   1 +
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.c|   6 +
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.h|  61 ++---
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c  |  10 +
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf|   4 +
 IntelSiliconPkg/IntelVTdDxe/PciInfo.c  |  12 +
 IntelSiliconPkg/IntelVTdDxe/TranslationTable.c |  58 +++-
 IntelSiliconPkg/IntelVTdDxe/TranslationTableEx.c   |   2 +
 IntelSiliconPkg/IntelVTdDxe/VtdReg.c   | 283 +++-
 MdePkg/Include/Library/CpuLib.h|  12 +-
 MdePkg/Library/BaseCpuLib/BaseCpuLib.inf   |   5 +-
 MdePkg/Library/BaseCpuLib/Ebc/CpuSleepFlushTlb.c   |  16 +-
 MdePkg/Library/BaseCpuLib/Ia32/CacheLineFlush.nasm |  37 +++
 MdePkg/Library/BaseCpuLib/X64/CacheLineFlush.nasm  |  37 +++
 14 files changed, 318 insertions(+), 226 deletions(-)
 create mode 100644 MdePkg/Library/BaseCpuLib/Ia32/CacheLineFlush.nasm
 create mode 100644 MdePkg/Library/BaseCpuLib/X64/CacheLineFlush.nasm

-- 
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[edk2] [PATCH 2/4] MdePkg/BaseCpuLib: Add CacheLineFlush function.

[Jiewen Yao]

This function will be used by IntelVTd driver.

Cc: Liming Gao <liming@intel.com>
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdePkg/Library/BaseCpuLib/BaseCpuLib.inf   |  5 ++-
 MdePkg/Library/BaseCpuLib/Ebc/CpuSleepFlushTlb.c   | 16 -
 MdePkg/Library/BaseCpuLib/Ia32/CacheLineFlush.nasm | 37 
 MdePkg/Library/BaseCpuLib/X64/CacheLineFlush.nasm  | 37 
 4 files changed, 93 insertions(+), 2 deletions(-)

diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf 
b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
index 637a3c5..b43b393 100644
--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
@@ -4,7 +4,7 @@
 #  CPU Library implemented using ASM functions for IA-32 and X64,
 #  PAL CALLs for IPF, and empty functions for EBC.
 #
-#  Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
+#  Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
 #  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
 #  Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
 #
@@ -33,6 +33,8 @@
 #
 
 [Sources.IA32]
+  Ia32/CacheLineFlush.nasm
+
   Ia32/CpuSleep.c | MSFT 
   Ia32/CpuFlushTlb.c | MSFT 
 
@@ -45,6 +47,7 @@
   Ia32/CpuFlushTlbGcc.c | GCC 
 
 [Sources.X64]
+  X64/CacheLineFlush.nasm
   X64/CpuFlushTlb.nasm
   X64/CpuFlushTlb.asm 
   X64/CpuSleep.nasm
diff --git a/MdePkg/Library/BaseCpuLib/Ebc/CpuSleepFlushTlb.c 
b/MdePkg/Library/BaseCpuLib/Ebc/CpuSleepFlushTlb.c
index de63d63..0c554c2 100644
--- a/MdePkg/Library/BaseCpuLib/Ebc/CpuSleepFlushTlb.c
+++ b/MdePkg/Library/BaseCpuLib/Ebc/CpuSleepFlushTlb.c
@@ -1,7 +1,7 @@
 /** @file
   Base Library CPU Functions for EBC
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -15,6 +15,20 @@
 #include 
 
 /**
+  Flushes one cache line.
+
+  Flushes one cache line. The size of cache line can be got by CPU register.
+**/
+VOID
+EFIAPI
+CacheLineFlush (
+  IN UINTN  Address
+  )
+{
+  ASSERT (FALSE);
+}
+
+/**
   Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
 
   Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
diff --git a/MdePkg/Library/BaseCpuLib/Ia32/CacheLineFlush.nasm 
b/MdePkg/Library/BaseCpuLib/Ia32/CacheLineFlush.nasm
new file mode 100644
index 000..a2557ab
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ia32/CacheLineFlush.nasm
@@ -0,0 +1,37 @@
+;--
 ;
+; Copyright (c) 2017, Intel Corporation. All rights reserved.
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD 
License
+; which accompanies this distribution.  The full text of the license may be 
found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   CacheLineFlush.Asm
+;
+; Abstract:
+;
+;   CacheLineFlush function
+;
+; Notes:
+;
+;--
+
+SECTION .text
+
+;--
+; VOID
+; EFIAPI
+; CacheLineFlush (
+;   IN UINTN Address
+;   );
+;--
+global ASM_PFX(CacheLineFlush)
+ASM_PFX(CacheLineFlush):
+mov eax, [esp + 4]
+clflush [eax]
+ret
+
diff --git a/MdePkg/Library/BaseCpuLib/X64/CacheLineFlush.nasm 
b/MdePkg/Library/BaseCpuLib/X64/CacheLineFlush.nasm
new file mode 100644
index 000..7cf736e
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/X64/CacheLineFlush.nasm
@@ -0,0 +1,37 @@
+;--
 ;
+; Copyright (c) 2017, Intel Corporation. All rights reserved.
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD 
License
+; which accompanies this distribution.  The full text of the license may be 
found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   CacheLineFlush.Asm
+;
+; Abstract:
+;
+;   CacheLineFlush function
+;
+; Notes:
+;
+;---

[edk2] [PATCH 1/4] MdePkg/CpuLib.h: Add CacheLineFlush function.

[Jiewen Yao]

This function will be used by IntelVTd driver.

Cc: Liming Gao <liming@intel.com>
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdePkg/Include/Library/CpuLib.h | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/MdePkg/Include/Library/CpuLib.h b/MdePkg/Include/Library/CpuLib.h
index 100020a..1b2f7e8 100644
--- a/MdePkg/Include/Library/CpuLib.h
+++ b/MdePkg/Include/Library/CpuLib.h
@@ -7,7 +7,7 @@
   PAL Calls require PEI and DXE specific mechanisms to look up PAL Entry Point.
   As a result, these services could not be defined in the Base Library.
 
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -47,5 +47,15 @@ CpuFlushTlb (
   VOID
   );
 
+/**
+  Flushes one cache line.
+
+  Flushes one cache line. The size of cache line can be got by CPU register.
+**/
+VOID
+EFIAPI
+CacheLineFlush (
+  IN UINTN  Address
+  );
 
 #endif
-- 
2.7.4.windows.1

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[edk2] [PATCH 3/4] IntelSiliconPkg/dsc: Add CpuLib.

[Jiewen Yao]

It will be used by IntelVTdDxe.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelSiliconPkg.dsc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/IntelSiliconPkg/IntelSiliconPkg.dsc 
b/IntelSiliconPkg/IntelSiliconPkg.dsc
index d837d84..7d7981e 100644
--- a/IntelSiliconPkg/IntelSiliconPkg.dsc
+++ b/IntelSiliconPkg/IntelSiliconPkg.dsc
@@ -38,6 +38,7 @@
   
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
   
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
   SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
 
 [LibraryClasses.common.DXE_DRIVER]
   
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
-- 
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[edk2] [PATCH V2] Maintainers.txt: Change maintainer for Intel*Pkg.

[Jiewen Yao]

Since Giri left Intel, we change 3 Intel*Pkg
maintainer.

Cc: Chasel Chiu <chasel.c...@intel.com>
Cc: Amy Chan <amy.c...@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaga...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 Maintainers.txt | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Maintainers.txt b/Maintainers.txt
index 39b5b67..e6aac63 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -131,12 +131,12 @@ M: Jeff Fan <jeff@intel.com>
 IntelFsp2Pkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2Pkg
 M: Jiewen Yao <jiewen@intel.com>
-M: Giri P Mudusuru <giri.p.mudus...@intel.com>
+M: Chasel Chiu <chasel.c...@intel.com>
 
 IntelFsp2WrapperPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2WrapperPkg
 M: Jiewen Yao <jiewen@intel.com>
-M: Giri P Mudusuru <giri.p.mudus...@intel.com>
+M: Chasel Chiu <chasel.c...@intel.com>
 
 IntelFspPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFspPkg
@@ -149,7 +149,7 @@ M: Jiewen Yao <jiewen@intel.com>
 IntelSiliconPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelSiliconPkg
 M: Jiewen Yao <jiewen@intel.com>
-M: Giri P Mudusuru <giri.p.mudus...@intel.com>
+M: Rangasai V Chaganty <rangasai.v.chaga...@intel.com>
 
 MdeModulePkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/MdeModulePkg
-- 
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[edk2] [PATCH] Maintainers.txt: Change maintainer for Intel*Pkg.

[Jiewen Yao]

Since Giri left Intel, we change 3 Intel*Pkg
maintainer.

Cc: Chasel Chiu <chasel.c...@intel.com>
Cc: Amy Chan <amy.c...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 Maintainers.txt | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Maintainers.txt b/Maintainers.txt
index 39b5b67..e6aac63 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -131,12 +131,12 @@ M: Jeff Fan <jeff@intel.com>
 IntelFsp2Pkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2Pkg
 M: Jiewen Yao <jiewen@intel.com>
-M: Giri P Mudusuru <giri.p.mudus...@intel.com>
+M: Chasel Chiu <chasel.c...@intel.com>
 
 IntelFsp2WrapperPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2WrapperPkg
 M: Jiewen Yao <jiewen@intel.com>
-M: Giri P Mudusuru <giri.p.mudus...@intel.com>
+M: Chasel Chiu <chasel.c...@intel.com>
 
 IntelFspPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFspPkg
@@ -149,7 +149,7 @@ M: Jiewen Yao <jiewen@intel.com>
 IntelSiliconPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelSiliconPkg
 M: Jiewen Yao <jiewen@intel.com>
-M: Giri P Mudusuru <giri.p.mudus...@intel.com>
+M: Amy Chan <amy.c...@intel.com>
 
 MdeModulePkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/MdeModulePkg
-- 
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[edk2] [PATCH 5/7] IntelSiliconPkg/dsc: Add Vtd driver.

[Jiewen Yao]

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelSiliconPkg.dsc | 31 
 1 file changed, 31 insertions(+)

diff --git a/IntelSiliconPkg/IntelSiliconPkg.dsc 
b/IntelSiliconPkg/IntelSiliconPkg.dsc
index f77f2a9..f2625cb 100644
--- a/IntelSiliconPkg/IntelSiliconPkg.dsc
+++ b/IntelSiliconPkg/IntelSiliconPkg.dsc
@@ -23,6 +23,32 @@
   BUILD_TARGETS  = DEBUG|RELEASE|NOOPT
   SKUID_IDENTIFIER   = DEFAULT
 
+[LibraryClasses]
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+  
ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+  PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+  PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+  
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
 
###
 #
 # Components Section - list of the modules and components that will be 
processed by compilation
@@ -44,3 +70,8 @@
 
 [Components]
   IntelSiliconPkg/Library/DxeSmbiosDataHobLib/DxeSmbiosDataHobLib.inf
+  IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf
+
+[BuildOptions]
+  *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
+
-- 
2.7.4.windows.1

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[edk2] [PATCH 7/7] IntelSiliconPkg/dsc: Add PlatformVtd sample driver.

[Jiewen Yao]

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelSiliconPkg.dsc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/IntelSiliconPkg/IntelSiliconPkg.dsc 
b/IntelSiliconPkg/IntelSiliconPkg.dsc
index f2625cb..d837d84 100644
--- a/IntelSiliconPkg/IntelSiliconPkg.dsc
+++ b/IntelSiliconPkg/IntelSiliconPkg.dsc
@@ -71,6 +71,7 @@
 [Components]
   IntelSiliconPkg/Library/DxeSmbiosDataHobLib/DxeSmbiosDataHobLib.inf
   IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf
+  IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.inf
 
 [BuildOptions]
   *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
-- 
2.7.4.windows.1

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[edk2] [PATCH 6/7] IntelSiliconPkg: Add PlatformVTdSample driver.

[Jiewen Yao]

It provides sample on Platform VTd policy protocol.
This protocol is optional.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c| 339 

 IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.inf  |  59 
 IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.uni  |  20 ++
 IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxeExtra.uni |  20 ++
 4 files changed, 438 insertions(+)

diff --git a/IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c 
b/IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c
new file mode 100644
index 000..13b5feb
--- /dev/null
+++ b/IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c
@@ -0,0 +1,339 @@
+/** @file
+  Platform VTd Sample driver.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+typedef struct {
+  ACPI_EXTENDED_HID_DEVICE_PATH  I2cController;
+  UINT8  HidStr[8];
+  UINT8  UidStr[1];
+  UINT8  CidStr[8];
+} PLATFORM_I2C_CONTROLLER_DEVICE_PATH;
+
+typedef struct {
+  ACPI_EXTENDED_HID_DEVICE_PATH  I2cDevice;
+  UINT8  HidStr[13];
+  UINT8  UidStr[1];
+  UINT8  CidStr[13];
+} PLATFORM_I2C_DEVICE_DEVICE_PATH;
+
+typedef struct {
+  PLATFORM_I2C_CONTROLLER_DEVICE_PATH  I2cController;
+  PLATFORM_I2C_DEVICE_DEVICE_PATH  I2cDevice;
+  EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_I2C_DEVICE_PATH;
+
+typedef struct {
+  ACPI_HID_DEVICE_PATH  PciRootBridge;
+  PCI_DEVICE_PATH   PciDevice;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} PLATFORM_PCI_DEVICE_PATH;
+
+typedef struct {
+  ACPI_HID_DEVICE_PATH  PciRootBridge;
+  PCI_DEVICE_PATH   PciBridge;
+  PCI_DEVICE_PATH   PciDevice;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} PLATFORM_PCI_BRIDGE_DEVICE_PATH;
+
+typedef struct {
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;
+  UINT16Segment;
+  VTD_SOURCE_ID SourceId;
+} PLATFORM_ACPI_DEVICE_MAPPING;
+
+#define PLATFORM_PCI_ROOT_BRIDGE \
+  { \
+{ \
+  ACPI_DEVICE_PATH, \
+  ACPI_DP, \
+  { \
+(UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \
+(UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \
+  }, \
+}, \
+EISA_PNP_ID (0x0A03), \
+0 \
+  }
+
+#define PLATFORM_END_ENTIRE \
+  { \
+END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { 
END_DEVICE_PATH_LENGTH, 0 } \
+  }
+
+#define PLATFORM_PCI(Device, Function) \
+  { \
+{ \
+  HARDWARE_DEVICE_PATH, \
+  HW_PCI_DP, \
+  { \
+(UINT8) (sizeof (PCI_DEVICE_PATH)), \
+(UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \
+  } \
+}, \
+(Function), \
+(Device) \
+  }
+
+#define PLATFORM_I2C(Hid, Uid, Cid, HidStr, UidStr, CidStr) \
+  { \
+{ \
+  { \
+ACPI_DEVICE_PATH, \
+ACPI_EXTENDED_DP, \
+{sizeof(ACPI_EXTENDED_HID_DEVICE_PATH) + sizeof(HidStr) + 
sizeof(UidStr) + sizeof(CidStr), 0} \
+  }, \
+  Hid, \
+  Uid, \
+  Cid \
+}, \
+HidStr, \
+UidStr, \
+CidStr \
+  }
+
+PLATFORM_I2C_DEVICE_PATH mPlatformI2CDevicePath = {
+  PLATFORM_I2C(0, 2, 0, "INT33C3", "", "INT33C3"),
+  PLATFORM_I2C(0, 1, 0, "I2C01\\TPANEL", "", "I2C01\\TPANEL"),
+  PLATFORM_END_ENTIRE
+};
+
+PLATFORM_ACPI_DEVICE_MAPPING  mAcpiDeviceMapping[] = {
+  {
+(EFI_DEVICE_PATH_PROTOCOL *),
+0x0, // Segment
+{{0x01, 0x15, 0x00}} // Function, Device, Bus
+  }
+};
+
+PLATFORM_PCI_BRIDGE_DEVICE_PATH mPlatformPciBridgeDevicePath = {
+  PLATFORM_PCI_ROOT_BRIDGE,
+  PLATFORM_PCI(0x1C, 1),
+  PLATFORM_PCI(0, 0),
+  PLATFORM_END_ENTIRE
+};
+
+EDKII_PLATFORM_VTD_DEVICE_INFO  mExceptionDeviceList[] = {
+  {
+0x0, // Segment
+{{0x00, 0x00, 0x02}} // Function, Device, Bus
+  },
+};
+
+/**
+  Compares 2 device path.
+
+  @param[in] DevicePath1  A device path with EndDevicePath node.
+  @param[in] DevicePath2  A device path with EndDevicePath node.
+
+  @retval TRUE   2 device path are identical.
+  @retval FALSE  2 device p

[edk2] [PATCH 2/7] IntelSiliconPkg/Include: Add PlatformVtdPolicy Protocol

[Jiewen Yao]

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h | 100 
 1 file changed, 100 insertions(+)

diff --git a/IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h 
b/IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h
new file mode 100644
index 000..1bd9365
--- /dev/null
+++ b/IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h
@@ -0,0 +1,100 @@
+/** @file
+  The definition for platform VTD policy.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __PLATFORM_VTD_POLICY_PROTOCOL_H__
+#define __PLATFORM_VTD_POLICY_PROTOCOL_H__
+
+#include 
+
+#define EDKII_PLATFORM_VTD_POLICY_PROTOCOL_GUID \
+{ \
+  0x3d17e448, 0x466, 0x4e20, { 0x99, 0x9f, 0xb2, 0xe1, 0x34, 0x88, 0xee, 
0x22 } \
+}
+
+typedef struct _EDKII_PLATFORM_VTD_POLICY_PROTOCOL  
EDKII_PLATFORM_VTD_POLICY_PROTOCOL;
+
+#define EDKII_PLATFORM_VTD_POLICY_PROTOCOL_REVISION 0x0001
+
+typedef struct {
+  UINT16   Segment;
+  VTD_SOURCE_IDSourceId;
+} EDKII_PLATFORM_VTD_DEVICE_INFO;
+
+/**
+  Get the VTD SourceId from the device handler.
+  This function is required for non PCI device handler.
+
+  Pseudo-algo in Intel VTd driver:
+Status = PlatformGetVTdDeviceId ();
+if (EFI_ERROR(Status)) {
+  if (DeviceHandle is PCI) {
+Get SourceId from Bus/Device/Function
+  } else {
+return EFI_UNSUPPORTED
+  }
+}
+Get VTd engine by Segment/Bus/Device/Function.
+
+  @param[in]  This  The protocol instance pointer.
+  @param[in]  DeviceHandle  Device Identifier in UEFI.
+  @param[out] DeviceInfoDeviceInfo for indentify the VTd engine in 
ACPI Table
+and the VTd page entry.
+
+  @retval EFI_SUCCESS   The VtdIndex and SourceId are returned.
+  @retval EFI_INVALID_PARAMETER DeviceHandle is not a valid handler.
+  @retval EFI_INVALID_PARAMETER DeviceInfo is NULL.
+  @retval EFI_NOT_FOUND The Segment or SourceId information is NOT 
found.
+  @retval EFI_UNSUPPORTED   This function is not supported.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_PLATFORM_VTD_POLICY_GET_DEVICE_ID) (
+  IN  EDKII_PLATFORM_VTD_POLICY_PROTOCOL   *This,
+  IN  EFI_HANDLE   DeviceHandle,
+  OUT EDKII_PLATFORM_VTD_DEVICE_INFO   *DeviceInfo
+  );
+
+/**
+  Get a list of handles for the exception devices.
+
+  The VTd driver should always set ALLOW for the device in this list.
+
+  @param[in]  This  The protocol instance pointer.
+  @param[out] DeviceInfoCount   The count of the list of DeviceInfo.
+  @param[out] DeviceInfoA callee allocated buffer to hold a list 
of DeviceInfo.
+
+  @retval EFI_SUCCESS   The DeviceInfoCount and DeviceInfo are 
returned.
+  @retval EFI_INVALID_PARAMETER DeviceInfoCount is NULL, or DeviceInfo is NULL.
+  @retval EFI_UNSUPPORTED   This function is not supported.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_PLATFORM_VTD_POLICY_GET_EXCEPTION_DEVICE_LIST) (
+  IN  EDKII_PLATFORM_VTD_POLICY_PROTOCOL   *This,
+  OUT UINTN*DeviceInfoCount,
+  OUT EDKII_PLATFORM_VTD_DEVICE_INFO   **DeviceInfo
+  );
+
+struct _EDKII_PLATFORM_VTD_POLICY_PROTOCOL {
+  UINT64   Revision;
+  EDKII_PLATFORM_VTD_POLICY_GET_DEVICE_ID  GetDeviceId;
+  EDKII_PLATFORM_VTD_POLICY_GET_EXCEPTION_DEVICE_LIST  GetExceptionDeviceList;
+};
+
+extern EFI_GUID gEdkiiPlatformVTdPolicyProtocolGuid;
+
+#endif
+
-- 
2.7.4.windows.1

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[edk2] [PATCH 0/7] Add VTd as IOMMU for UEFI.

[Jiewen Yao]

This series patch adds Intel VTd as IOMMU for UEFI BIOS.

It can also be found at https://github.com/jyao1/edk2/tree/vtd.

EDKII IOMMU protocol is already defined in MdeModulePkg.
This patch use VTd to implement IOMMU protocol.

A platform may use VTd to harden the system to prevent DMA attack
once the DMAR table is produced. The VTd engine will be disabled
at EndOfDxe event.

Test:
1) The patch is tested on Intel Kabylake platform and Intel Broadwell platform.
System boot to X64 UEFI Windows 10 successfully, with VTd engine enabled in 
BIOS.

2) We tested USB XHCI, ATA AHCI and Intel Graphic with DMA protection.

3) If we do not enable DMA access correctly in translation table, the DMA
access is blocked, and the device driver will return error.

More platform tests are on the way.


This series patch includes 1 protocol.
1) EDKII_PLATFORM_VTD_POLICY_PROTOCOL
This protocol is produced by a platform policy module and consumed
by the IntelVTdDxe driver.

1.1) GetDeviceId() API provides ACPI device information for VTd
source ID conversion.

1.2) GetExceptionDeviceList() API provides a list of exception devices.
We notice that a UEFI device driver might not follow UEFI spec to call PCI
map/unmap function for DMA request.

A platform may choose to unsupport the request from exception devices
or add workaround to support these exception device by returning the
device information by using GetExceptionDeviceList().

IntelVTD driver will consume this API to enable all memory access
for the exception device.


This series patch includes below 2 drivers.

1) IntelVTdDxe
It produces IOMMU Protocol and provide DMA protection.

It registers ACPI_SDT callback to check DMAR table.
Once the DMAR table is installed, IntelVTdDxe will enable VTd engine
to start protecting.

In order to use this feature, a platform MUST publish DMAR table
before any DMA transaction. Typically, it is at PciEnumDone protocol
callback.

If a platform does not have VTd support, or VTd is disabled,
the DMA protection will not be activated.

2) PlatformVTdSampleDxe
This is just a sample driver to show how to produce GetDeviceId()
or GetExceptionDeviceList() API.

It should NOT be included directly by any production.

If a platform need produce EDKII_PLATFORM_VTD_POLICY_PROTOCOL, it
should have its own driver.

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>

Jiewen Yao (7):
  IntelSiliconPkg/Include: Add VTD industry standard.
  IntelSiliconPkg/Include: Add PlatformVtdPolicy Protocol
  IntelSiliconPkg/Dec: Add ProtocolGuid.
  IntelSiliconPkg: Add VTd driver.
  IntelSiliconPkg/dsc: Add Vtd driver.
  IntelSiliconPkg: Add PlatformVTdSample driver.
  IntelSiliconPkg/dsc: Add PlatformVtd sample driver.

 IntelSiliconPkg/Include/IndustryStandard/Vtd.h | 345 
+++
 IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h   | 100 ++
 IntelSiliconPkg/IntelSiliconPkg.dec|   3 +
 IntelSiliconPkg/IntelSiliconPkg.dsc|  32 +
 IntelSiliconPkg/IntelVTdDxe/BmDma.c| 441 
+
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.c| 367 
+++
 IntelSiliconPkg/IntelVTdDxe/DmaProtection.h| 501 
++
 IntelSiliconPkg/IntelVTdDxe/DmarAcpiTable.c| 998 

 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c  | 353 
+++
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf|  79 ++
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.uni|  20 +
 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxeExtra.uni   |  20 +
 IntelSiliconPkg/IntelVTdDxe/PciInfo.c  | 315 ++
 IntelSiliconPkg/IntelVTdDxe/TranslationTable.c | 969 
+++
 IntelSiliconPkg/IntelVTdDxe/TranslationTableEx.c   | 153 +++
 IntelSiliconPkg/IntelVTdDxe/VtdReg.c   | 602 

 IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.c| 339 
+++
 IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.inf  |  59 ++
 IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxe.uni  |  20 +
 IntelSiliconPkg/PlatformVTdSampleDxe/PlatformVTdSampleDxeExtra.uni |  20 +
 20 files changed, 5736 insertions(+)
 create mode 100644 IntelSiliconPkg/Include/IndustryStandard/Vtd.h
 create mode 100644 IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h
 create mode 100644 IntelSiliconPkg/IntelVTdDxe/BmDma.c
 create mode 100644 IntelSiliconPkg/IntelVTdDxe/DmaProtection.c
 create mode 100644 IntelSiliconPkg/IntelVTdDxe/DmaProtection.h
 create mode 100644 IntelSiliconPkg/IntelVTdDxe/DmarAcpiTable.c
 create mode 100644 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.c
 create mode 100644 IntelSiliconPkg/IntelVTdDxe/IntelVTdDxe.inf
 create

[edk2] [PATCH 1/7] IntelSiliconPkg/Include: Add VTD industry standard.

[Jiewen Yao]

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/Include/IndustryStandard/Vtd.h | 345 
 1 file changed, 345 insertions(+)

diff --git a/IntelSiliconPkg/Include/IndustryStandard/Vtd.h 
b/IntelSiliconPkg/Include/IndustryStandard/Vtd.h
new file mode 100644
index 000..573ff59
--- /dev/null
+++ b/IntelSiliconPkg/Include/IndustryStandard/Vtd.h
@@ -0,0 +1,345 @@
+/** @file
+  The definition for VTD register.
+  It is defined in "Intel VT for Direct IO Architecture Specification".
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __VTD_REG_H__
+#define __VTD_REG_H__
+
+#pragma pack(1)
+
+//
+// Translation Structure Formats
+//
+#define VTD_ROOT_ENTRY_NUMBER   256
+#define VTD_CONTEXT_ENTRY_NUMBER256
+
+typedef union {
+  struct {
+UINT64  Present:1;
+UINT64  Reserved_1:11;
+UINT64  ContextTablePointer:52;
+
+UINT64  Reserved_64;
+  } Bits;
+  struct {
+UINT64  Uint64Lo;
+UINT64  Uint64Hi;
+  } Uint128;
+} VTD_ROOT_ENTRY;
+
+typedef union {
+  struct {
+UINT64  LowerPresent:1;
+UINT64  Reserved_1:11;
+UINT64  LowerContextTablePointer:52;
+
+UINT64  UpperPresent:1;
+UINT64  Reserved_65:11;
+UINT64  UpperContextTablePointer:52;
+  } Bits;
+  struct {
+UINT64  Uint64Lo;
+UINT64  Uint64Hi;
+  } Uint128;
+} VTD_EXT_ROOT_ENTRY;
+
+typedef union {
+  struct {
+UINT64  Present:1;
+UINT64  FaultProcessingDisable:1;
+UINT64  TranslationType:2;
+UINT64  Reserved_4:8;
+UINT64  SecondLevelPageTranslationPointer:52;
+
+UINT64  AddressWidth:3;
+UINT64  Ignored_67:4;
+UINT64  Reserved_71:1;
+UINT64  DomainIdentifier:16;
+UINT64  Reserved_88:40;
+  } Bits;
+  struct {
+UINT64  Uint64Lo;
+UINT64  Uint64Hi;
+  } Uint128;
+} VTD_CONTEXT_ENTRY;
+
+typedef union {
+  struct {
+UINT64  Present:1;
+UINT64  FaultProcessingDisable:1;
+UINT64  TranslationType:3;
+UINT64  ExtendedMemoryType:3;
+UINT64  DeferredInvalidateEnable:1;
+UINT64  PageRequestEnable:1;
+UINT64  NestedTranslationEnable:1;
+UINT64  PASIDEnable:1;
+UINT64  SecondLevelPageTranslationPointer:52;
+
+UINT64  AddressWidth:3;
+UINT64  PageGlobalEnable:1;
+UINT64  NoExecuteEnable:1;
+UINT64  WriteProtectEnable:1;
+UINT64  CacheDisable:1;
+UINT64  ExtendedMemoryTypeEnable:1;
+UINT64  DomainIdentifier:16;
+UINT64  SupervisorModeExecuteProtection:1;
+UINT64  ExtendedAccessedFlagEnable:1;
+UINT64  ExecuteRequestsEnable:1;
+UINT64  SecondLevelExecuteEnable:1;
+UINT64  Reserved_92:4;
+UINT64  PageAttributeTable0:3;
+UINT64  Reserved_Pat0:1;
+UINT64  PageAttributeTable1:3;
+UINT64  Reserved_Pat1:1;
+UINT64  PageAttributeTable2:3;
+UINT64  Reserved_Pat2:1;
+UINT64  PageAttributeTable3:3;
+UINT64  Reserved_Pat3:1;
+UINT64  PageAttributeTable4:3;
+UINT64  Reserved_Pat4:1;
+UINT64  PageAttributeTable5:3;
+UINT64  Reserved_Pat5:1;
+UINT64  PageAttributeTable6:3;
+UINT64  Reserved_Pat6:1;
+UINT64  PageAttributeTable7:3;
+UINT64  Reserved_Pat7:1;
+
+UINT64  PASIDTableSize:4;
+UINT64  Reserved_132:8;
+UINT64  PASIDTablePointer:52;
+
+UINT64  Reserved_192:12;
+UINT64  PASIDStateTablePointer:52;
+  } Bits;
+  struct {
+UINT64  Uint64_1;
+UINT64  Uint64_2;
+UINT64  Uint64_3;
+UINT64  Uint64_4;
+  } Uint256;
+} VTD_EXT_CONTEXT_ENTRY;
+
+typedef union {
+  struct {
+UINT64  Present:1;
+UINT64  Reserved_1:2;
+UINT64  PageLevelCacheDisable:1;
+UINT64  PageLevelWriteThrough:1;
+UINT64  Reserved_5:6;
+UINT64  SupervisorRequestsEnable:1;
+UINT64  FirstLevelPageTranslationPointer:52;
+  } Bits;
+  UINT64Uint64;
+} VTD_PASID_ENTRY;
+
+typedef union {
+  struct {
+UINT64  Reserved_0:32;
+UINT64  ActiveReferenceCount:16;
+UINT64  Reserved_48:15;
+UINT64  DeferredInvalidate:1;
+  } Bits;
+  UINT64Uint64;
+} VTD_PASID_STATE_ENTRY;
+
+typedef union {
+  struct {
+UINT64  Present:1;
+UINT64  ReadWrite:1;
+UINT64  UserSupervisor:1;
+UINT64  PageLevelWriteThrough:1;
+UINT64  PageLevelCacheDisable:1;
+UINT64  Accessed:1;
+UINT64  Dirty:1;
+UINT64  PageSize:1; // It is PageAttribute:1 for 4K page entry
+UINT64  Global:1;
+UINT64  Ignored_9:1;
+UINT64  ExtendedAccessed:1;
+UINT64  Ignored_11:1;
+/

[edk2] [PATCH 3/7] IntelSiliconPkg/Dec: Add ProtocolGuid.

[Jiewen Yao]

Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 IntelSiliconPkg/IntelSiliconPkg.dec | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec 
b/IntelSiliconPkg/IntelSiliconPkg.dec
index 8819cb8..663a232 100644
--- a/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -33,6 +33,9 @@
   # Generic DXE Library / Driver can locate HOB(s) and add SMBIOS records into 
SMBIOS table
   gIntelSmbiosDataHobGuid = { 0x798e722e, 0x15b2, 0x4e13, { 0x8a, 
0xe9, 0x6b, 0xa3, 0x0f, 0xf7, 0xf1, 0x67 }}
 
+[Protocols]
+  gEdkiiPlatformVTdPolicyProtocolGuid = { 0x3d17e448, 0x466, 0x4e20, { 0x99, 
0x9f, 0xb2, 0xe1, 0x34, 0x88, 0xee, 0x22 }}
+
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
   ## This is the GUID of the FFS which contains the Graphics Video BIOS Table 
(VBT)
   # The VBT content is stored as a RAW section which is consumed by GOP 
PEI/UEFI driver.
-- 
2.7.4.windows.1

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[edk2] [PATCH V2] UefiCpuPkg/SmmCpuFeatureLib: Add more CPU ID for SmmFeatureControl.

[Jiewen Yao]

Add more CPU ID which can support SmmFeatureControl,
according to IA32 SDM.

Cc: Jeff Fan <jeff@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c 
b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
index 079baa4..2d2bc6d 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
@@ -296,7 +296,9 @@ SmmCpuFeaturesInitializeProcessor (
   // Intel(R) Core(TM) Processor Family MSRs.
   //
   if (FamilyId == 0x06) {
-if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) {
+if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46 ||
+ModelId == 0x3D || ModelId == 0x47 || ModelId == 0x4E || ModelId == 
0x4F ||
+ModelId == 0x3F || ModelId == 0x56 || ModelId == 0x57 || ModelId == 
0x5C) {
   //
   // Check to see if the CPU supports the SMM Code Access Check feature
   // Do not access this MSR unless the CPU supports the 
SmmRegFeatureControl
-- 
2.7.4.windows.1

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[edk2] [PATCH] UefiCpuPkg/SmmCpuFeatureLib: Add more CPU ID for SmmFeatureControl.

[Jiewen Yao]

Add more CPU ID which can support SmmFeatureControl,
according to IA32 SDM.

Cc: Jeff Fan <jeff@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c 
b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
index 079baa4..b0c442e 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
@@ -296,7 +296,8 @@ SmmCpuFeaturesInitializeProcessor (
   // Intel(R) Core(TM) Processor Family MSRs.
   //
   if (FamilyId == 0x06) {
-if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) {
+if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46 ||
+ModelId == 0x3D || ModelId == 0x47 || ModelId == 0x4E || ModelId == 
0x4F) {
   //
   // Check to see if the CPU supports the SMM Code Access Check feature
   // Do not access this MSR unless the CPU supports the 
SmmRegFeatureControl
-- 
2.7.4.windows.1

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[edk2] [PATCH V5 3/3] MdeModulePkg/PciBus: Add IOMMU support.

[Jiewen Yao]

If IOMMU protocol is installed, PciBus need call IOMMU
to set access attribute for the PCI device in Map/Ummap.

Only after the access attribute is set, the PCI device can
access the DMA memory.

Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Leo Duran <leo.du...@amd.com>
Cc: Brijesh Singh <brijesh.si...@amd.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c  |  9 
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h  |  1 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf |  1 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c   | 47 ++--
 4 files changed, 54 insertions(+), 4 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c
index f3be47a..950cacc 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c
@@ -42,6 +42,7 @@ UINT64gAllZero
 = 0;
 
 EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
 EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
+EDKII_IOMMU_PROTOCOL  *mIoMmuProtocol;
 
 
 GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL 
mPciHotPlugRequest = {
@@ -284,6 +285,14 @@ PciBusDriverBindingStart (
   );
   }  
 
+  if (mIoMmuProtocol == NULL) {
+gBS->LocateProtocol (
+  ,
+  NULL,
+  (VOID **) 
+  );
+  }
+
   if (PcdGetBool (PcdPciDisableBusEnumeration)) {
 gFullEnumeration = FALSE;
   } else {
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
index 39ba8b9..3bcc134 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
@@ -32,6 +32,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
index a3ab11f..5da094f 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
@@ -95,6 +95,7 @@
   gEfiPciRootBridgeIoProtocolGuid ## TO_START
   gEfiIncompatiblePciDeviceSupportProtocolGuid## SOMETIMES_CONSUMES
   gEfiLoadFile2ProtocolGuid   ## SOMETIMES_PRODUCES
+  gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES
 
 [FeaturePcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport  ## CONSUMES
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
index f72598d..3b3b53a 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
@@ -14,6 +14,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 
 #include "PciBus.h"
 
+extern EDKII_IOMMU_PROTOCOL  *mIoMmuProtocol;
+
 //
 // Pci Io Protocol Interface
 //
@@ -965,8 +967,10 @@ PciIoMap (
   OUTVOID   **Mapping
   )
 {
-  EFI_STATUSStatus;
-  PCI_IO_DEVICE *PciIoDevice;
+  EFI_STATUS Status;
+  PCI_IO_DEVICE  *PciIoDevice;
+  UINT64 IoMmuAttribute;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  RootBridgeIoOperation;
 
   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
 
@@ -978,13 +982,14 @@ PciIoMap (
 return EFI_INVALID_PARAMETER;
   }
 
+  RootBridgeIoOperation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)Operation;
   if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 
0) {
-Operation = (EFI_PCI_IO_PROTOCOL_OPERATION) (Operation + 
EfiPciOperationBusMasterRead64);
+RootBridgeIoOperation = 
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)(Operation + 
EfiPciOperationBusMasterRead64);
   }
 
   Status = PciIoDevice->PciRootBridgeIo->Map (
   PciIoDevice->PciRootBridgeIo,
-  
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) Operation,
+  RootBridgeIoOperation,
   HostAddress,
   NumberOfBytes,
   DeviceAddress,
@@ -999,6 +1004,31 @@ PciIoMap (
   );
   }
 
+  if (mIoMmuProtocol != NULL) {
+if (!EFI_ERROR (Status)) {
+  switch (Operation) {
+  case EfiPciIoOperationBusMasterRead:
+IoMmuAttribute = EDKII_IOMMU_ACCESS_READ;
+break;
+  case EfiPciIoOperationBusMasterWrite:
+IoMmuAttribute = EDKII_IOMMU_ACCESS_WRITE;
+break;
+  case EfiPciIoOperationBusMasterCommonBuffer:
+IoMmuAtt

[edk2] [PATCH V5 2/3] MdeModulePkg/PciHostBridge: Add IOMMU support.

[Jiewen Yao]

If IOMMU protocol is installed, PciHostBridge just calls
IOMMU AllocateBuffer/FreeBuffer/Map/Unmap.

PciHostBridge does not set IOMMU access attribute,
because it does not know which device request the DMA.
This work is done by PciBus driver.

Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Leo Duran <leo.du...@amd.com>
Cc: Brijesh Singh <brijesh.si...@amd.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c  | 37 
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf |  2 +
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h  |  2 +
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c| 61 

 4 files changed, 102 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
index 9005dee..70726a6 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
@@ -28,6 +28,10 @@ GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mPciResourceTypeStr[] 
= {
   L"I/O", L"Mem", L"PMem", L"Mem64", L"PMem64", L"Bus"
 };
 
+EDKII_IOMMU_PROTOCOL*mIoMmuProtocol;
+EFI_EVENT   mIoMmuEvent;
+VOID*mIoMmuRegistration;
+
 /**
   Ensure the compatibility of an IO space descriptor with the IO aperture.
 
@@ -313,6 +317,28 @@ FreeMemorySpaceMap:
 }
 
 /**
+  Event notification that is fired when IOMMU protocol is installed.
+
+  @param  Event The Event that is being processed.
+  @param  Context   Event Context.
+
+**/
+VOID
+EFIAPI
+IoMmuProtocolCallback (
+  IN  EFI_EVENT   Event,
+  IN  VOID*Context
+  )
+{
+  EFI_STATUS   Status;
+
+  Status = gBS->LocateProtocol (, NULL, (VOID 
**));
+  if (!EFI_ERROR(Status)) {
+gBS->CloseEvent (mIoMmuEvent);
+  }
+}
+
+/**
 
   Entry point of this driver.
 
@@ -489,6 +515,17 @@ InitializePciHostBridge (
 ASSERT_EFI_ERROR (Status);
   }
   PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount);
+
+  if (!EFI_ERROR (Status)) {
+mIoMmuEvent = EfiCreateProtocolNotifyEvent (
+,
+TPL_CALLBACK,
+IoMmuProtocolCallback,
+NULL,
+
+);
+  }
+
   return Status;
 }
 
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
index d8b0439..42bd8a2 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
@@ -41,6 +41,7 @@
   BaseMemoryLib
   BaseLib
   PciSegmentLib
+  UefiLib
   PciHostBridgeLib
 
 [Protocols]
@@ -49,6 +50,7 @@
   gEfiDevicePathProtocolGuid  ## BY_START
   gEfiPciRootBridgeIoProtocolGuid ## BY_START
   gEfiPciHostBridgeResourceAllocationProtocolGuid ## BY_START
+  gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES
 
 [Depex]
   gEfiCpuIo2ProtocolGuid AND
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h
index 13185b4..1fec88b 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h
@@ -27,6 +27,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -34,6 +35,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include 
 #include "PciHostResource.h"
 
 
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index 8af131b..068295b 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -17,6 +17,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include "PciRootBridge.h"
 #include "PciHostResource.h"
 
+extern EDKII_IOMMU_PROTOCOL*mIoMmuProtocol;
+
 #define NO_MAPPING  (VOID *) (UINTN) -1
 
 //
@@ -1072,6 +1074,26 @@ RootBridgeIoMap (
 
   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 
+  if (mIoMmuProtocol != NULL) {
+if (!RootBridge->DmaAbove4G) {
+  //
+  // Clear 64bit support
+  //
+  if (Operation > EfiPciOperationBusMasterCommonBuffer) {
+Operation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) (Operation - 
EfiPciOperationBusMasterRead64);
+  }
+}
+Status = mIoMmuProtocol->Map (
+   mIoMmuProtocol

[edk2] [PATCH V5 0/3] Add IOMMU support.

[Jiewen Yao]

 V5 ==
Minor update from V4.

1) Remove unused SetAttribute() API in IOMMU protocol.
(Feedback from Ruiyu and Ard)
2) Rename SetMappingAttribute() to SetAttribute().
(Feedback from Ruiyu)
3) Fix the bug in PciBus driver for Operation
(Thanks to Ard to catch it)

V4:
Tested-by: Brijesh Singh <brijesh.si...@amd.com>
With the issue in 3/3 addressed:
Tested-by: Ard Biesheuvel <ard.biesheu...@linaro.org>

 V4 ==
Refine the EDKII_IOMMU_PROTOCOL.

1) Add AllocateBuffer/FreeBuffer/Map/Unmap() API.
They are similar to DmaLib in EmbeddedPkg and
similar to the previous BmDmaLib (by leo.du...@amd.com).

These APIs are invoked by PciHostBridge driver
to allocate DMA memory.

The PciHostBridge driver (IOMMU consumer) is simplified:
It uses IOMMU, if IOMMU protocol is present.
Else it uses original logic.

2) Add SetMappingAttribute() API.
It is similar to SetAttribute() API in V1.

This API is invoked by PciBus driver to set DMA
access attribute (read/write) for device.

The PciBus driver (IOMMU consumer) is simplified:
It sets access attribute in Map/Unmap,
if IOMMU protocol is present.

3) Remove SetRemapAddress/GetRemapAddress() API.
Because PciHostBridge/PciBus can call the APIs defined
above, there is no need to provide remap capability.

-- Sample producer drivers:
1) The sample VTd driver (IOMMU producer)
is at https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/IntelVTdDxe

It is added to show the concept. It is not fully implemented yet.
It will not be checked in in this patch.

2) The sample AMD SEV driver (IOMMU producer)
is at https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/SampleAmdSevDxe
(code is borrowed from leo.du...@amd.com and brijesh.si...@amd.com)

This is not a right place to put this driver.

It is added to show the concept.
It is not fully implemented. It will not be checked in.
Please do not use it directly.

3) The sample STYX driver (IOMMU producer)
is at https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/SampleStyxDxe
(code is borrowed from ard.biesheu...@linaro.org)

This is not a right place to put this driver.

It is added to show the concept.
It is not fully implemented. It will not be checked in.
Please do not use it directly.


 V3 ==
1) Add Remap capability (from Ard Biesheuvel)
Add EDKII_IOMMU_REMAP_ADDRESS API in IOMMU_PROTOCOL.

NOTE: The code is not fully validated yet.
The purpose is to collect feedback to decide the next step.

 V2 ==
1) Enhance Unmap() in PciIo (From Ruiyu Ni)
Maintain a local list of MapInfo and match it in Unmap.

2) CopyMem for ReadOperation in PciIo after SetAttribute (Leo Duran)
Fix a bug in V1 that copy mem for read happen before SetAttribute,
which will break AMD SEV solution.

 V1 ==

This patch series adds IOMMU protocol and updates the consumer
to support IOMMU based DMA access in UEFI.

This patch series can support the BmDmaLib request for AMD SEV.
submitted by Duran, Leo <leo.du...@amd.com> and Brijesh Singh 
<brijesh.ksi...@gmail.com>.
https://lists.01.org/pipermail/edk2-devel/2017-March/008109.html, and
https://lists.01.org/pipermail/edk2-devel/2017-March/008820.html.
We can have an AMD SEV specific IOMMU driver to produce IOMMU protocol,
and clear SEV in IOMMU->SetAttribute().

This patch series can also support Intel VTd based DMA protection,
requested by Jiewen Yao <jiewen@intel.com>, discussed in
https://lists.01.org/pipermail/edk2-devel/2017-March/008157.html.
We can have an Intel VTd specific IOMMU driver to produce IOMMU protocol,
and update VTd engine to grant or deny access in IOMMU->SetAttribute().

This patch series does not provide a full Intel VTd driver, which
will be provide in other patch in the future.

The purpose of this patch series to review if this IOMMU protocol design
can meet all DMA access and management requirement.

Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Leo Duran <leo.du...@amd.com>
Cc: Brijesh Singh <brijesh.si...@amd.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>

Jiewen Yao (3):
  MdeModulePkg/Include: Add IOMMU protocol definition.
  MdeModulePkg/PciHostBridge: Add IOMMU support.
  MdeModulePkg/PciBus: Add IOMMU support.

 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c|   9 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h|   1 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf   |   1 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c |  47 +++-
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c  |  37 +++
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf |   2 +
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h  |   2 +
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c|  61 +

[edk2] [PATCH V5 1/3] MdeModulePkg/Include: Add IOMMU protocol definition.

[Jiewen Yao]

This protocol is to abstract DMA access from IOMMU.
1) Intel "DMAR" ACPI table.
2) AMD "IVRS" ACPI table
3) ARM "IORT" ACPI table.

There might be multiple IOMMU engines on one platform.
For example, one for graphic and one for rest PCI devices
(such as ATA/USB).
All IOMMU engines are reported by one ACPI table.

All IOMMU protocol provider should be based upon ACPI table.
This single IOMMU protocol can handle multiple IOMMU engines on one system.

This IOMMU protocol provider can use UEFI device path to distinguish
if the device is graphic or ATA/USB, and find out corresponding
IOMMU engine.

The IOMMU protocol provides 2 capabilities:
A) Set DMA access attribute - such as write/read control.
B) Remap DMA memory - such as remap above 4GiB system memory address
to below 4GiB device address.
It provides AllocateBuffer/FreeBuffer/Map/Unmap for DMA memory.
The remapping can be static (fixed at build time) or dynamic (allocate
at runtime).

4) AMD "SEV" feature.
We can have an AMD SEV specific IOMMU driver to produce IOMMU protocol,
and manage SEV bit.

Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Leo Duran <leo.du...@amd.com>
Cc: Brijesh Singh <brijesh.si...@amd.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdeModulePkg/Include/Protocol/IoMmu.h | 259 
 MdeModulePkg/MdeModulePkg.dec |   3 +
 2 files changed, 262 insertions(+)

diff --git a/MdeModulePkg/Include/Protocol/IoMmu.h 
b/MdeModulePkg/Include/Protocol/IoMmu.h
new file mode 100644
index 000..9d25c17
--- /dev/null
+++ b/MdeModulePkg/Include/Protocol/IoMmu.h
@@ -0,0 +1,259 @@
+/** @file
+  EFI IOMMU Protocol.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available 
under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef __IOMMU_H__
+#define __IOMMU_H__
+
+//
+// IOMMU Protocol GUID value
+//
+#define EDKII_IOMMU_PROTOCOL_GUID \
+{ \
+  0x4e939de9, 0xd948, 0x4b0f, { 0x88, 0xed, 0xe6, 0xe1, 0xce, 0x51, 0x7c, 
0x1e } \
+}
+
+//
+// Forward reference for pure ANSI compatability
+//
+typedef struct _EDKII_IOMMU_PROTOCOL  EDKII_IOMMU_PROTOCOL;
+
+//
+// Revision The revision to which the IOMMU interface adheres.
+//  All future revisions must be backwards compatible.
+//  If a future version is not back wards compatible it is not the 
same GUID.
+//
+#define EDKII_IOMMU_PROTOCOL_REVISION 0x0001
+
+//
+// IOMMU Access for SetAttribute
+//
+// These types can be "ORed" together as needed.
+// Any undefined bits are reserved and must be zero.
+//
+#define EDKII_IOMMU_ACCESS_READ   0x1
+#define EDKII_IOMMU_ACCESS_WRITE  0x2
+
+//
+// IOMMU Operation for Map
+//
+typedef enum {
+  ///
+  /// A read operation from system memory by a bus master that is not capable 
of producing
+  /// PCI dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterRead,
+  ///
+  /// A write operation from system memory by a bus master that is not capable 
of producing
+  /// PCI dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterWrite,
+  ///
+  /// Provides both read and write access to system memory by both the 
processor and a bus
+  /// master that is not capable of producing PCI dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterCommonBuffer,
+  ///
+  /// A read operation from system memory by a bus master that is capable of 
producing PCI
+  /// dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterRead64,
+  ///
+  /// A write operation to system memory by a bus master that is capable of 
producing PCI
+  /// dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterWrite64,
+  ///
+  /// Provides both read and write access to system memory by both the 
processor and a bus
+  /// master that is capable of producing PCI dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterCommonBuffer64,
+  EdkiiIoMmuOperationMaximum
+} EDKII_IOMMU_OPERATION;
+
+//
+// IOMMU attribute for AllocateBuffer
+// Any undefined bits are reserved and must be zero.
+//
+#define EDKII_IOMMU_ATTRIBUTE_MEMORY_WRITE_COMBINE0x0080
+#define EDKII_IOMMU_ATTRIBUTE_MEMORY_CACHED   0x0800
+#define EDKII_IOMMU_ATTRIBUTE_DUAL_ADDRESS_CYCLE  0x8000
+
+#define EDKII_IOMMU_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER   
(EDKII_IOMMU_ATTRIBUTE_MEMORY_WRITE_COMBINE | 
EDKII_IOMMU_ATTRIBUTE_MEMORY_CACHED | EDKII_IOMMU_ATTRIBUTE_DUAL_ADDRESS_CYCLE)
+
+#define EDKII_IOMMU_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER 
(~EDKII_IOMMU_ATTRIBUTE_VALID

[edk2] [RFC] [PATCH V4 2/3] MdeModulePkg/PciHostBridge: Add IOMMU support.

[Jiewen Yao]

If IOMMU protocol is installed, PciHostBridge just calls
IOMMU AllocateBuffer/FreeBuffer/Map/Unmap.

PciHostBridge does not set IOMMU access attribute,
because it does not know which device request the DMA.
This work is done by PciBus driver.

Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Leo Duran <leo.du...@amd.com>
Cc: Brijesh Singh <brijesh.si...@amd.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c  | 37 
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf |  2 +
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h  |  2 +
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c| 61 

 4 files changed, 102 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
index 9005dee..70726a6 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
@@ -28,6 +28,10 @@ GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mPciResourceTypeStr[] 
= {
   L"I/O", L"Mem", L"PMem", L"Mem64", L"PMem64", L"Bus"
 };
 
+EDKII_IOMMU_PROTOCOL*mIoMmuProtocol;
+EFI_EVENT   mIoMmuEvent;
+VOID*mIoMmuRegistration;
+
 /**
   Ensure the compatibility of an IO space descriptor with the IO aperture.
 
@@ -313,6 +317,28 @@ FreeMemorySpaceMap:
 }
 
 /**
+  Event notification that is fired when IOMMU protocol is installed.
+
+  @param  Event The Event that is being processed.
+  @param  Context   Event Context.
+
+**/
+VOID
+EFIAPI
+IoMmuProtocolCallback (
+  IN  EFI_EVENT   Event,
+  IN  VOID*Context
+  )
+{
+  EFI_STATUS   Status;
+
+  Status = gBS->LocateProtocol (, NULL, (VOID 
**));
+  if (!EFI_ERROR(Status)) {
+gBS->CloseEvent (mIoMmuEvent);
+  }
+}
+
+/**
 
   Entry point of this driver.
 
@@ -489,6 +515,17 @@ InitializePciHostBridge (
 ASSERT_EFI_ERROR (Status);
   }
   PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount);
+
+  if (!EFI_ERROR (Status)) {
+mIoMmuEvent = EfiCreateProtocolNotifyEvent (
+,
+TPL_CALLBACK,
+IoMmuProtocolCallback,
+NULL,
+
+);
+  }
+
   return Status;
 }
 
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
index d8b0439..42bd8a2 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
@@ -41,6 +41,7 @@
   BaseMemoryLib
   BaseLib
   PciSegmentLib
+  UefiLib
   PciHostBridgeLib
 
 [Protocols]
@@ -49,6 +50,7 @@
   gEfiDevicePathProtocolGuid  ## BY_START
   gEfiPciRootBridgeIoProtocolGuid ## BY_START
   gEfiPciHostBridgeResourceAllocationProtocolGuid ## BY_START
+  gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES
 
 [Depex]
   gEfiCpuIo2ProtocolGuid AND
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h
index 13185b4..1fec88b 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h
@@ -27,6 +27,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -34,6 +35,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include 
 #include "PciHostResource.h"
 
 
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index 8af131b..068295b 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -17,6 +17,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include "PciRootBridge.h"
 #include "PciHostResource.h"
 
+extern EDKII_IOMMU_PROTOCOL*mIoMmuProtocol;
+
 #define NO_MAPPING  (VOID *) (UINTN) -1
 
 //
@@ -1072,6 +1074,26 @@ RootBridgeIoMap (
 
   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 
+  if (mIoMmuProtocol != NULL) {
+if (!RootBridge->DmaAbove4G) {
+  //
+  // Clear 64bit support
+  //
+  if (Operation > EfiPciOperationBusMasterCommonBuffer) {
+Operation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) (Operation - 
EfiPciOperationBusMasterRead64);
+  }
+}
+Status = mIoMmuProtocol->Map (
+   mIoMmuProtocol

[edk2] [RFC] [PATCH V4 0/3] Add IOMMU support.

[Jiewen Yao]

 V4 ==
Refine the EDKII_IOMMU_PROTOCOL.

1) Add AllocateBuffer/FreeBuffer/Map/Unmap() API.
They are similar to DmaLib in EmbeddedPkg and
similar to the previous BmDmaLib (by leo.du...@amd.com).

These APIs are invoked by PciHostBridge driver
to allocate DMA memory.

The PciHostBridge driver (IOMMU consumer) is simplified:
It uses IOMMU, if IOMMU protocol is present.
Else it uses original logic.

2) Add SetMappingAttribute() API.
It is similar to SetAttribute() API in V1.

This API is invoked by PciBus driver to set DMA
access attribute (read/write) for device.

The PciBus driver (IOMMU consumer) is simplified:
It sets access attribute in Map/Unmap,
if IOMMU protocol is present.

3) Remove SetRemapAddress/GetRemapAddress() API.
Because PciHostBridge/PciBus can call the APIs defined
above, there is no need to provide remap capability.

-- Sample producer drivers:
1) The sample VTd driver (IOMMU producer)
is at https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/IntelVTdDxe

It is added to show the concept. It is not fully implemented yet.
It will not be checked in in this patch.

2) The sample AMD SEV driver (IOMMU producer)
is at https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/SampleAmdSevDxe
(code is borrowed from leo.du...@amd.com and brijesh.si...@amd.com)

This is not a right place to put this driver.

It is added to show the concept.
It is not fully implemented. It will not be checked in.
Please do not use it directly.

3) The sample STYX driver (IOMMU producer)
is at https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/SampleStyxDxe
(code is borrowed from ard.biesheu...@linaro.org)

This is not a right place to put this driver.

It is added to show the concept.
It is not fully implemented. It will not be checked in.
Please do not use it directly.


 V3 ==
1) Add Remap capability (from Ard Biesheuvel)
Add EDKII_IOMMU_REMAP_ADDRESS API in IOMMU_PROTOCOL.

NOTE: The code is not fully validated yet.
The purpose is to collect feedback to decide the next step.

 V2 ==
1) Enhance Unmap() in PciIo (From Ruiyu Ni)
Maintain a local list of MapInfo and match it in Unmap.

2) CopyMem for ReadOperation in PciIo after SetAttribute (Leo Duran)
Fix a bug in V1 that copy mem for read happen before SetAttribute,
which will break AMD SEV solution.

 V1 ==

This patch series adds IOMMU protocol and updates the consumer
to support IOMMU based DMA access in UEFI.

This patch series can support the BmDmaLib request for AMD SEV.
submitted by Duran, Leo <leo.du...@amd.com> and Brijesh Singh 
<brijesh.ksi...@gmail.com>.
https://lists.01.org/pipermail/edk2-devel/2017-March/008109.html, and
https://lists.01.org/pipermail/edk2-devel/2017-March/008820.html.
We can have an AMD SEV specific IOMMU driver to produce IOMMU protocol,
and clear SEV in IOMMU->SetAttribute().

This patch series can also support Intel VTd based DMA protection,
requested by Jiewen Yao <jiewen@intel.com>, discussed in
https://lists.01.org/pipermail/edk2-devel/2017-March/008157.html.
We can have an Intel VTd specific IOMMU driver to produce IOMMU protocol,
and update VTd engine to grant or deny access in IOMMU->SetAttribute().

This patch series does not provide a full Intel VTd driver, which
will be provide in other patch in the future.

The purpose of this patch series to review if this IOMMU protocol design
can meet all DMA access and management requirement.

Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Leo Duran <leo.du...@amd.com>
Cc: Brijesh Singh <brijesh.si...@amd.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>

Jiewen Yao (3):
  MdeModulePkg/Include: Add IOMMU protocol definition.
  MdeModulePkg/PciHostBridge: Add IOMMU support.
  MdeModulePkg/PciBus: Add IOMMU support.

 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c|   9 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h|   1 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf   |   1 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c |  37 +++
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c  |  37 +++
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf |   2 +
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h  |   2 +
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c|  61 
 MdeModulePkg/Include/Protocol/IoMmu.h  | 310 

 MdeModulePkg/MdeModulePkg.dec  |   3 +
 10 files changed, 463 insertions(+)
 create mode 100644 MdeModulePkg/Include/Protocol/IoMmu.h

-- 
2.7.4.windows.1

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edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [RFC] [PATCH V4 1/3] MdeModulePkg/Include: Add IOMMU protocol definition.

[Jiewen Yao]

This protocol is to abstract DMA access from IOMMU.
1) Intel "DMAR" ACPI table.
2) AMD "IVRS" ACPI table
3) ARM "IORT" ACPI table.

There might be multiple IOMMU engines on one platform.
For example, one for graphic and one for rest PCI devices
(such as ATA/USB).
All IOMMU engines are reported by one ACPI table.

All IOMMU protocol provider should be based upon ACPI table.
This single IOMMU protocol can handle multiple IOMMU engines on one system.

This IOMMU protocol provider can use UEFI device path to distinguish
if the device is graphic or ATA/USB, and find out corresponding
IOMMU engine.

The IOMMU protocol provides 2 capabilities:
A) Set DMA access attribute - such as write/read control.
B) Remap DMA memory - such as remap above 4GiB system memory address
to below 4GiB device address.
It provides AllocateBuffer/FreeBuffer/Map/Unmap for DMA memory.
The remapping can be static (fixed at build time) or dynamic (allocate
at runtime).

4) AMD "SEV" feature.
We can have an AMD SEV specific IOMMU driver to produce IOMMU protocol,
and manage SEV bit.

Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Leo Duran <leo.du...@amd.com>
Cc: Brijesh Singh <brijesh.si...@amd.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdeModulePkg/Include/Protocol/IoMmu.h | 310 
 MdeModulePkg/MdeModulePkg.dec |   3 +
 2 files changed, 313 insertions(+)

diff --git a/MdeModulePkg/Include/Protocol/IoMmu.h 
b/MdeModulePkg/Include/Protocol/IoMmu.h
new file mode 100644
index 000..3f62f46
--- /dev/null
+++ b/MdeModulePkg/Include/Protocol/IoMmu.h
@@ -0,0 +1,310 @@
+/** @file
+  EFI IOMMU Protocol.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available 
under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef __IOMMU_H__
+#define __IOMMU_H__
+
+//
+// IOMMU Protocol GUID value
+//
+#define EDKII_IOMMU_PROTOCOL_GUID \
+{ \
+  0x4e939de9, 0xd948, 0x4b0f, { 0x88, 0xed, 0xe6, 0xe1, 0xce, 0x51, 0x7c, 
0x1e } \
+}
+
+//
+// Forward reference for pure ANSI compatability
+//
+typedef struct _EDKII_IOMMU_PROTOCOL  EDKII_IOMMU_PROTOCOL;
+
+//
+// Revision The revision to which the IOMMU interface adheres.
+//  All future revisions must be backwards compatible.
+//  If a future version is not back wards compatible it is not the 
same GUID.
+//
+#define EDKII_IOMMU_PROTOCOL_REVISION 0x0001
+
+//
+// IOMMU Access for SetAttribute
+//
+// These types can be "ORed" together as needed.
+// Any undefined bits are reserved and must be zero.
+//
+#define EDKII_IOMMU_ACCESS_READ   0x1
+#define EDKII_IOMMU_ACCESS_WRITE  0x2
+
+//
+// IOMMU Operation for Map
+//
+typedef enum {
+  ///
+  /// A read operation from system memory by a bus master that is not capable 
of producing
+  /// PCI dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterRead,
+  ///
+  /// A write operation from system memory by a bus master that is not capable 
of producing
+  /// PCI dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterWrite,
+  ///
+  /// Provides both read and write access to system memory by both the 
processor and a bus
+  /// master that is not capable of producing PCI dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterCommonBuffer,
+  ///
+  /// A read operation from system memory by a bus master that is capable of 
producing PCI
+  /// dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterRead64,
+  ///
+  /// A write operation to system memory by a bus master that is capable of 
producing PCI
+  /// dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterWrite64,
+  ///
+  /// Provides both read and write access to system memory by both the 
processor and a bus
+  /// master that is capable of producing PCI dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterCommonBuffer64,
+  EdkiiIoMmuOperationMaximum
+} EDKII_IOMMU_OPERATION;
+
+//
+// IOMMU attribute for AllocateBuffer
+// Any undefined bits are reserved and must be zero.
+//
+#define EDKII_IOMMU_ATTRIBUTE_MEMORY_WRITE_COMBINE0x0080
+#define EDKII_IOMMU_ATTRIBUTE_MEMORY_CACHED   0x0800
+#define EDKII_IOMMU_ATTRIBUTE_DUAL_ADDRESS_CYCLE  0x8000
+
+#define EDKII_IOMMU_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER   
(EDKII_IOMMU_ATTRIBUTE_MEMORY_WRITE_COMBINE | 
EDKII_IOMMU_ATTRIBUTE_MEMORY_CACHED | EDKII_IOMMU_ATTRIBUTE_DUAL_ADDRESS_CYCLE)
+
+#define EDKII_IOMMU_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER 
(~EDKII_IOMMU_ATTRIBUTE_VALID

[edk2] [RFC] [PATCH V4 3/3] MdeModulePkg/PciBus: Add IOMMU support.

[Jiewen Yao]

If IOMMU protocol is installed, PciBus need call IOMMU
to set access attribute for the PCI device in Map/Ummap.

Only after the access attribute is set, the PCI device can
access the DMA memory.

Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Leo Duran <leo.du...@amd.com>
Cc: Brijesh Singh <brijesh.si...@amd.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c  |  9 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h  |  1 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf |  1 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c   | 37 
 4 files changed, 48 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c
index f3be47a..950cacc 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c
@@ -42,6 +42,7 @@ UINT64gAllZero
 = 0;
 
 EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
 EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
+EDKII_IOMMU_PROTOCOL  *mIoMmuProtocol;
 
 
 GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL 
mPciHotPlugRequest = {
@@ -284,6 +285,14 @@ PciBusDriverBindingStart (
   );
   }  
 
+  if (mIoMmuProtocol == NULL) {
+gBS->LocateProtocol (
+  ,
+  NULL,
+  (VOID **) 
+  );
+  }
+
   if (PcdGetBool (PcdPciDisableBusEnumeration)) {
 gFullEnumeration = FALSE;
   } else {
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
index 39ba8b9..3bcc134 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
@@ -32,6 +32,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
index a3ab11f..5da094f 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
@@ -95,6 +95,7 @@
   gEfiPciRootBridgeIoProtocolGuid ## TO_START
   gEfiIncompatiblePciDeviceSupportProtocolGuid## SOMETIMES_CONSUMES
   gEfiLoadFile2ProtocolGuid   ## SOMETIMES_PRODUCES
+  gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES
 
 [FeaturePcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport  ## CONSUMES
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
index f72598d..c0251c0 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
@@ -14,6 +14,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 
 #include "PciBus.h"
 
+extern EDKII_IOMMU_PROTOCOL  *mIoMmuProtocol;
+
 //
 // Pci Io Protocol Interface
 //
@@ -967,6 +969,7 @@ PciIoMap (
 {
   EFI_STATUSStatus;
   PCI_IO_DEVICE *PciIoDevice;
+  UINT64IoMmuAttribute;
 
   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
 
@@ -999,6 +1002,31 @@ PciIoMap (
   );
   }
 
+  if (mIoMmuProtocol != NULL) {
+if (!EFI_ERROR (Status)) {
+  switch (Operation) {
+  case EfiPciIoOperationBusMasterRead:
+IoMmuAttribute = EDKII_IOMMU_ACCESS_READ;
+break;
+  case EfiPciIoOperationBusMasterWrite:
+IoMmuAttribute = EDKII_IOMMU_ACCESS_WRITE;
+break;
+  case EfiPciIoOperationBusMasterCommonBuffer:
+IoMmuAttribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
+break;
+  default:
+ASSERT(FALSE);
+return EFI_INVALID_PARAMETER;
+  }
+  mIoMmuProtocol->SetMappingAttribute (
+mIoMmuProtocol,
+PciIoDevice->Handle,
+*Mapping,
+IoMmuAttribute
+);
+}
+  }
+
   return Status;
 }
 
@@ -1024,6 +1052,15 @@ PciIoUnmap (
 
   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
 
+  if (mIoMmuProtocol != NULL) {
+mIoMmuProtocol->SetMappingAttribute (
+  mIoMmuProtocol,
+  PciIoDevice->Handle,
+  Mapping,
+  0
+  );
+  }
+
   Status = PciIoDevice->PciRootBridgeIo->Unmap (
   PciIoDevice->PciRootBridgeIo,
   Mapping
-- 
2.7.4.windows.1

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[edk2] [PATCH 3/3] MdeModulePkg/PciBus: Add IOMMU support.

[Jiewen Yao]

If IOMMU protocol is installed, PciBus need call IOMMU
to set access attribute for the PCI device in Map/Ummap.

Only after the access attribute is set, the PCI device can
access the DMA memory.

Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Leo Duran <leo.du...@amd.com>
Cc: Brijesh Singh <brijesh.si...@amd.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c  |  9 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h  |  1 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf |  1 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c   | 37 
 4 files changed, 48 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c
index f3be47a..950cacc 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c
@@ -42,6 +42,7 @@ UINT64gAllZero
 = 0;
 
 EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
 EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
+EDKII_IOMMU_PROTOCOL  *mIoMmuProtocol;
 
 
 GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL 
mPciHotPlugRequest = {
@@ -284,6 +285,14 @@ PciBusDriverBindingStart (
   );
   }  
 
+  if (mIoMmuProtocol == NULL) {
+gBS->LocateProtocol (
+  ,
+  NULL,
+  (VOID **) 
+  );
+  }
+
   if (PcdGetBool (PcdPciDisableBusEnumeration)) {
 gFullEnumeration = FALSE;
   } else {
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
index 39ba8b9..3bcc134 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
@@ -32,6 +32,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
index a3ab11f..5da094f 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
@@ -95,6 +95,7 @@
   gEfiPciRootBridgeIoProtocolGuid ## TO_START
   gEfiIncompatiblePciDeviceSupportProtocolGuid## SOMETIMES_CONSUMES
   gEfiLoadFile2ProtocolGuid   ## SOMETIMES_PRODUCES
+  gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES
 
 [FeaturePcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport  ## CONSUMES
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
index f72598d..c0251c0 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
@@ -14,6 +14,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 
 #include "PciBus.h"
 
+extern EDKII_IOMMU_PROTOCOL  *mIoMmuProtocol;
+
 //
 // Pci Io Protocol Interface
 //
@@ -967,6 +969,7 @@ PciIoMap (
 {
   EFI_STATUSStatus;
   PCI_IO_DEVICE *PciIoDevice;
+  UINT64IoMmuAttribute;
 
   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
 
@@ -999,6 +1002,31 @@ PciIoMap (
   );
   }
 
+  if (mIoMmuProtocol != NULL) {
+if (!EFI_ERROR (Status)) {
+  switch (Operation) {
+  case EfiPciIoOperationBusMasterRead:
+IoMmuAttribute = EDKII_IOMMU_ACCESS_READ;
+break;
+  case EfiPciIoOperationBusMasterWrite:
+IoMmuAttribute = EDKII_IOMMU_ACCESS_WRITE;
+break;
+  case EfiPciIoOperationBusMasterCommonBuffer:
+IoMmuAttribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
+break;
+  default:
+ASSERT(FALSE);
+return EFI_INVALID_PARAMETER;
+  }
+  mIoMmuProtocol->SetMappingAttribute (
+mIoMmuProtocol,
+PciIoDevice->Handle,
+*Mapping,
+IoMmuAttribute
+);
+}
+  }
+
   return Status;
 }
 
@@ -1024,6 +1052,15 @@ PciIoUnmap (
 
   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
 
+  if (mIoMmuProtocol != NULL) {
+mIoMmuProtocol->SetMappingAttribute (
+  mIoMmuProtocol,
+  PciIoDevice->Handle,
+  Mapping,
+  0
+  );
+  }
+
   Status = PciIoDevice->PciRootBridgeIo->Unmap (
   PciIoDevice->PciRootBridgeIo,
   Mapping
-- 
2.7.4.windows.1

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[edk2] [PATCH 2/3] MdeModulePkg/PciHostBridge: Add IOMMU support.

[Jiewen Yao]

If IOMMU protocol is installed, PciHostBridge just calls
IOMMU AllocateBuffer/FreeBuffer/Map/Unmap.

PciHostBridge does not set IOMMU access attribute,
because it does not know which device request the DMA.
This work is done by PciBus driver.

Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Leo Duran <leo.du...@amd.com>
Cc: Brijesh Singh <brijesh.si...@amd.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c  | 37 
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf |  2 +
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h  |  2 +
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c| 61 

 4 files changed, 102 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
index 9005dee..70726a6 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
@@ -28,6 +28,10 @@ GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mPciResourceTypeStr[] 
= {
   L"I/O", L"Mem", L"PMem", L"Mem64", L"PMem64", L"Bus"
 };
 
+EDKII_IOMMU_PROTOCOL*mIoMmuProtocol;
+EFI_EVENT   mIoMmuEvent;
+VOID*mIoMmuRegistration;
+
 /**
   Ensure the compatibility of an IO space descriptor with the IO aperture.
 
@@ -313,6 +317,28 @@ FreeMemorySpaceMap:
 }
 
 /**
+  Event notification that is fired when IOMMU protocol is installed.
+
+  @param  Event The Event that is being processed.
+  @param  Context   Event Context.
+
+**/
+VOID
+EFIAPI
+IoMmuProtocolCallback (
+  IN  EFI_EVENT   Event,
+  IN  VOID*Context
+  )
+{
+  EFI_STATUS   Status;
+
+  Status = gBS->LocateProtocol (, NULL, (VOID 
**));
+  if (!EFI_ERROR(Status)) {
+gBS->CloseEvent (mIoMmuEvent);
+  }
+}
+
+/**
 
   Entry point of this driver.
 
@@ -489,6 +515,17 @@ InitializePciHostBridge (
 ASSERT_EFI_ERROR (Status);
   }
   PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount);
+
+  if (!EFI_ERROR (Status)) {
+mIoMmuEvent = EfiCreateProtocolNotifyEvent (
+,
+TPL_CALLBACK,
+IoMmuProtocolCallback,
+NULL,
+
+);
+  }
+
   return Status;
 }
 
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
index d8b0439..42bd8a2 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
@@ -41,6 +41,7 @@
   BaseMemoryLib
   BaseLib
   PciSegmentLib
+  UefiLib
   PciHostBridgeLib
 
 [Protocols]
@@ -49,6 +50,7 @@
   gEfiDevicePathProtocolGuid  ## BY_START
   gEfiPciRootBridgeIoProtocolGuid ## BY_START
   gEfiPciHostBridgeResourceAllocationProtocolGuid ## BY_START
+  gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES
 
 [Depex]
   gEfiCpuIo2ProtocolGuid AND
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h
index 13185b4..1fec88b 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h
@@ -27,6 +27,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -34,6 +35,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include 
 #include "PciHostResource.h"
 
 
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index 8af131b..068295b 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -17,6 +17,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include "PciRootBridge.h"
 #include "PciHostResource.h"
 
+extern EDKII_IOMMU_PROTOCOL*mIoMmuProtocol;
+
 #define NO_MAPPING  (VOID *) (UINTN) -1
 
 //
@@ -1072,6 +1074,26 @@ RootBridgeIoMap (
 
   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 
+  if (mIoMmuProtocol != NULL) {
+if (!RootBridge->DmaAbove4G) {
+  //
+  // Clear 64bit support
+  //
+  if (Operation > EfiPciOperationBusMasterCommonBuffer) {
+Operation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) (Operation - 
EfiPciOperationBusMasterRead64);
+  }
+}
+Status = mIoMmuProtocol->Map (
+   mIoMmuProtocol

[edk2] [PATCH 1/3] MdeModulePkg/Include: Add IOMMU protocol definition.

[Jiewen Yao]

This protocol is to abstract DMA access from IOMMU.
1) Intel "DMAR" ACPI table.
2) AMD "IVRS" ACPI table
3) ARM "IORT" ACPI table.

There might be multiple IOMMU engines on one platform.
For example, one for graphic and one for rest PCI devices
(such as ATA/USB).
All IOMMU engines are reported by one ACPI table.

All IOMMU protocol provider should be based upon ACPI table.
This single IOMMU protocol can handle multiple IOMMU engines on one system.

This IOMMU protocol provider can use UEFI device path to distinguish
if the device is graphic or ATA/USB, and find out corresponding
IOMMU engine.

The IOMMU protocol provides 2 capabilities:
A) Set DMA access attribute - such as write/read control.
B) Remap DMA memory - such as remap above 4GiB system memory address
to below 4GiB device address.
It provides AllocateBuffer/FreeBuffer/Map/Unmap for DMA memory.
The remapping can be static (fixed at build time) or dynamic (allocate
at runtime).

4) AMD "SEV" feature.
We can have an AMD SEV specific IOMMU driver to produce IOMMU protocol,
and manage SEV bit.

Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Leo Duran <leo.du...@amd.com>
Cc: Brijesh Singh <brijesh.si...@amd.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdeModulePkg/Include/Protocol/IoMmu.h | 310 
 MdeModulePkg/MdeModulePkg.dec |   3 +
 2 files changed, 313 insertions(+)

diff --git a/MdeModulePkg/Include/Protocol/IoMmu.h 
b/MdeModulePkg/Include/Protocol/IoMmu.h
new file mode 100644
index 000..3f62f46
--- /dev/null
+++ b/MdeModulePkg/Include/Protocol/IoMmu.h
@@ -0,0 +1,310 @@
+/** @file
+  EFI IOMMU Protocol.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available 
under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef __IOMMU_H__
+#define __IOMMU_H__
+
+//
+// IOMMU Protocol GUID value
+//
+#define EDKII_IOMMU_PROTOCOL_GUID \
+{ \
+  0x4e939de9, 0xd948, 0x4b0f, { 0x88, 0xed, 0xe6, 0xe1, 0xce, 0x51, 0x7c, 
0x1e } \
+}
+
+//
+// Forward reference for pure ANSI compatability
+//
+typedef struct _EDKII_IOMMU_PROTOCOL  EDKII_IOMMU_PROTOCOL;
+
+//
+// Revision The revision to which the IOMMU interface adheres.
+//  All future revisions must be backwards compatible.
+//  If a future version is not back wards compatible it is not the 
same GUID.
+//
+#define EDKII_IOMMU_PROTOCOL_REVISION 0x0001
+
+//
+// IOMMU Access for SetAttribute
+//
+// These types can be "ORed" together as needed.
+// Any undefined bits are reserved and must be zero.
+//
+#define EDKII_IOMMU_ACCESS_READ   0x1
+#define EDKII_IOMMU_ACCESS_WRITE  0x2
+
+//
+// IOMMU Operation for Map
+//
+typedef enum {
+  ///
+  /// A read operation from system memory by a bus master that is not capable 
of producing
+  /// PCI dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterRead,
+  ///
+  /// A write operation from system memory by a bus master that is not capable 
of producing
+  /// PCI dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterWrite,
+  ///
+  /// Provides both read and write access to system memory by both the 
processor and a bus
+  /// master that is not capable of producing PCI dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterCommonBuffer,
+  ///
+  /// A read operation from system memory by a bus master that is capable of 
producing PCI
+  /// dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterRead64,
+  ///
+  /// A write operation to system memory by a bus master that is capable of 
producing PCI
+  /// dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterWrite64,
+  ///
+  /// Provides both read and write access to system memory by both the 
processor and a bus
+  /// master that is capable of producing PCI dual address cycles.
+  ///
+  EdkiiIoMmuOperationBusMasterCommonBuffer64,
+  EdkiiIoMmuOperationMaximum
+} EDKII_IOMMU_OPERATION;
+
+//
+// IOMMU attribute for AllocateBuffer
+// Any undefined bits are reserved and must be zero.
+//
+#define EDKII_IOMMU_ATTRIBUTE_MEMORY_WRITE_COMBINE0x0080
+#define EDKII_IOMMU_ATTRIBUTE_MEMORY_CACHED   0x0800
+#define EDKII_IOMMU_ATTRIBUTE_DUAL_ADDRESS_CYCLE  0x8000
+
+#define EDKII_IOMMU_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER   
(EDKII_IOMMU_ATTRIBUTE_MEMORY_WRITE_COMBINE | 
EDKII_IOMMU_ATTRIBUTE_MEMORY_CACHED | EDKII_IOMMU_ATTRIBUTE_DUAL_ADDRESS_CYCLE)
+
+#define EDKII_IOMMU_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER 
(~EDKII_IOMMU_ATTRIBUTE_VALID

[edk2] [RFC] [PATCH V4 0/3] Add IOMMU support.

[Jiewen Yao]

 V4 ==
Refine the EDKII_IOMMU_PROTOCOL.

1) Add AllocateBuffer/FreeBuffer/Map/Unmap() API.
They are similar to DmaLib in EmbeddedPkg and
similar to the previous BmDmaLib (by leo.du...@amd.com).

These APIs are invoked by PciHostBridge driver
to allocate DMA memory.

The PciHostBridge driver (IOMMU consumer) is simplified:
It uses IOMMU, if IOMMU protocol is present.
Else it uses original logic.

2) Add SetMappingAttribute() API.
It is similar to SetAttribute() API in V1.

This API is invoked by PciBus driver to set DMA
access attribute (read/write) for device.

The PciBus driver (IOMMU consumer) is simplified:
It sets access attribute in Map/Unmap,
if IOMMU protocol is present.

3) Remove SetRemapAddress/GetRemapAddress() API.
Because PciHostBridge/PciBus can call the APIs defined
above, there is no need to provide remap capability.

-- Sample producer drivers:
1) The sample VTd driver (IOMMU producer)
is at https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/IntelVTdDxe

It is added to show the concept. It is not fully implemented yet.
It will not be checked in in this patch.

2) The sample AMD SEV driver (IOMMU producer)
is at https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/SampleAmdSevDxe
(code is borrowed from leo.du...@amd.com and brijesh.si...@amd.com)

This is not a right place to put this driver.

It is added to show the concept.
It is not fully implemented. It will not be checked in.
Please do not use it directly.

3) The sample STYX driver (IOMMU producer)
is at https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/SampleStyxDxe
(code is borrowed from ard.biesheu...@linaro.org)

This is not a right place to put this driver.

It is added to show the concept.
It is not fully implemented. It will not be checked in.
Please do not use it directly.


 V3 ==
1) Add Remap capability (from Ard Biesheuvel)
Add EDKII_IOMMU_REMAP_ADDRESS API in IOMMU_PROTOCOL.

NOTE: The code is not fully validated yet.
The purpose is to collect feedback to decide the next step.

 V2 ==
1) Enhance Unmap() in PciIo (From Ruiyu Ni)
Maintain a local list of MapInfo and match it in Unmap.

2) CopyMem for ReadOperation in PciIo after SetAttribute (Leo Duran)
Fix a bug in V1 that copy mem for read happen before SetAttribute,
which will break AMD SEV solution.

 V1 ==

This patch series adds IOMMU protocol and updates the consumer
to support IOMMU based DMA access in UEFI.

This patch series can support the BmDmaLib request for AMD SEV.
submitted by Duran, Leo <leo.du...@amd.com> and Brijesh Singh 
<brijesh.ksi...@gmail.com>.
https://lists.01.org/pipermail/edk2-devel/2017-March/008109.html, and
https://lists.01.org/pipermail/edk2-devel/2017-March/008820.html.
We can have an AMD SEV specific IOMMU driver to produce IOMMU protocol,
and clear SEV in IOMMU->SetAttribute().

This patch series can also support Intel VTd based DMA protection,
requested by Jiewen Yao <jiewen@intel.com>, discussed in
https://lists.01.org/pipermail/edk2-devel/2017-March/008157.html.
We can have an Intel VTd specific IOMMU driver to produce IOMMU protocol,
and update VTd engine to grant or deny access in IOMMU->SetAttribute().

This patch series does not provide a full Intel VTd driver, which
will be provide in other patch in the future.

The purpose of this patch series to review if this IOMMU protocol design
can meet all DMA access and management requirement.

Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Leo Duran <leo.du...@amd.com>
Cc: Brijesh Singh <brijesh.si...@amd.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>

Jiewen Yao (3):
  MdeModulePkg/Include: Add IOMMU protocol definition.
  MdeModulePkg/PciHostBridge: Add IOMMU support.
  MdeModulePkg/PciBus: Add IOMMU support.

 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c|   9 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h|   1 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf   |   1 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c |  37 +++
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c  |  37 +++
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf |   2 +
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h  |   2 +
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c|  61 
 MdeModulePkg/Include/Protocol/IoMmu.h  | 310 

 MdeModulePkg/MdeModulePkg.dec  |   3 +
 10 files changed, 463 insertions(+)
 create mode 100644 MdeModulePkg/Include/Protocol/IoMmu.h

-- 
2.7.4.windows.1

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[edk2] [PATCH V2 4/4] MdePkg/dsc: add SmmIoLib

[Jiewen Yao]

Cc: Jeff Fan <jeff@intel.com>
Cc: Liming Gao <liming@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdePkg/MdePkg.dsc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index 8b69de3..d9c2c32 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -154,6 +154,7 @@
   MdePkg/Library/BaseS3SmbusLib/BaseS3SmbusLib.inf
   MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf
   MdePkg/Library/SmmMemLib/SmmMemLib.inf
+  MdePkg/Library/SmmIoLib/SmmIoLib.inf
   MdePkg/Library/BaseRngLib/BaseRngLib.inf
   MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf
   MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf
-- 
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[edk2] [PATCH V2 1/4] MdePkg/SmmIoLib: Add header file.

[Jiewen Yao]

This SmmIoLib is used to check if an IO resource
is valid in SMM.

Cc: Jeff Fan <jeff@intel.com>
Cc: Liming Gao <liming@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdePkg/Include/Library/SmmIoLib.h | 42 
 1 file changed, 42 insertions(+)

diff --git a/MdePkg/Include/Library/SmmIoLib.h 
b/MdePkg/Include/Library/SmmIoLib.h
new file mode 100644
index 000..7820f1e
--- /dev/null
+++ b/MdePkg/Include/Library/SmmIoLib.h
@@ -0,0 +1,42 @@
+/** @file
+  Provides services for SMM IO Operation.
+
+  The SMM IO Library provides function for checking if IO resource is 
accessible inside of SMM.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SMM_IO_LIB_H_
+#define _SMM_IO_LIB_H_
+
+/**
+  This function check if the MMIO resource is valid per processor architecture 
and
+  valid per platform design.
+
+  @param BaseAddress  The MMIO start address to be checked.
+  @param Length   The MMIO length to be checked.
+  @param OwnerA GUID representing the owner of the resource.
+  This GUID may be used by producer to correlate the 
device ownership of the resource.
+  NULL means no specific owner.
+
+  @retval TRUE  This MMIO resource is valid per processor architecture and 
valid per platform design.
+  @retval FALSE This MMIO resource is not valid per processor architecture or 
valid per platform design.
+**/
+BOOLEAN
+EFIAPI
+SmmIsMmioValid (
+  IN EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN UINT64Length,
+  IN EFI_GUID  *Owner  OPTIONAL
+  );
+
+#endif
+
-- 
2.7.4.windows.1

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[edk2] [PATCH V2 2/4] MdePkg/SmmIoLib: Add sample instance.

[Jiewen Yao]

The sample instance check if IO resource is valid
one defined in GCD.
A platform may choose add more check to exclude some
other IO resource.

Cc: Jeff Fan <jeff@intel.com>
Cc: Liming Gao <liming@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdePkg/Library/SmmIoLib/SmmIoLib.c   | 330 
 MdePkg/Library/SmmIoLib/SmmIoLib.inf |  53 
 MdePkg/Library/SmmIoLib/SmmIoLib.uni |  23 ++
 3 files changed, 406 insertions(+)

diff --git a/MdePkg/Library/SmmIoLib/SmmIoLib.c 
b/MdePkg/Library/SmmIoLib/SmmIoLib.c
new file mode 100644
index 000..181abb8
--- /dev/null
+++ b/MdePkg/Library/SmmIoLib/SmmIoLib.c
@@ -0,0 +1,330 @@
+/** @file
+  Instance of SMM IO check library.
+
+  SMM IO check library library implementation. This library consumes GCD to 
collect all valid
+  IO space defined by a platform.
+  A platform may have its own SmmIoLib instance to exclude more IO space.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+EFI_GCD_MEMORY_SPACE_DESCRIPTOR   *mSmmIoLibGcdMemSpace   = NULL;
+UINTN mSmmIoLibGcdMemNumberOfDesc = 0;
+
+EFI_PHYSICAL_ADDRESS  mSmmIoLibInternalMaximumSupportMemAddress = 0;
+
+VOID  *mSmmIoLibRegistrationEndOfDxe;
+VOID  *mSmmIoLibRegistrationReadyToLock;
+
+BOOLEAN   mSmmIoLibReadyToLock = FALSE;
+
+/**
+  Calculate and save the maximum support address.
+
+**/
+VOID
+SmmIoLibInternalCalculateMaximumSupportAddress (
+  VOID
+  )
+{
+  VOID *Hob;
+  UINT32   RegEax;
+  UINT8MemPhysicalAddressBits;
+
+  //
+  // Get physical address bits supported.
+  //
+  Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
+  if (Hob != NULL) {
+MemPhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
+  } else {
+AsmCpuid (0x8000, , NULL, NULL, NULL);
+if (RegEax >= 0x8008) {
+  AsmCpuid (0x8008, , NULL, NULL, NULL);
+  MemPhysicalAddressBits = (UINT8) RegEax;
+} else {
+  MemPhysicalAddressBits = 36;
+}
+  }
+  //
+  // IA-32e paging translates 48-bit linear addresses to 52-bit physical 
addresses.
+  //
+  ASSERT (MemPhysicalAddressBits <= 52);
+  if (MemPhysicalAddressBits > 48) {
+MemPhysicalAddressBits = 48;
+  }
+
+  //
+  // Save the maximum support address in one global variable
+  //
+  mSmmIoLibInternalMaximumSupportMemAddress = 
(EFI_PHYSICAL_ADDRESS)(UINTN)(LShiftU64 (1, MemPhysicalAddressBits) - 1);
+  DEBUG ((DEBUG_INFO, "mSmmIoLibInternalMaximumSupportMemAddress = 0x%lx\n", 
mSmmIoLibInternalMaximumSupportMemAddress));
+}
+
+/**
+  This function check if the MMIO resource is valid per processor architecture 
and
+  valid per platform design.
+
+  @param BaseAddress  The MMIO start address to be checked.
+  @param Length   The MMIO length to be checked.
+  @param OwnerA GUID representing the owner of the resource.
+  This GUID may be used by producer to correlate the 
device ownership of the resource.
+  NULL means no specific owner.
+
+  @retval TRUE  This MMIO resource is valid per processor architecture and 
valid per platform design.
+  @retval FALSE This MMIO resource is not valid per processor architecture or 
valid per platform design.
+**/
+BOOLEAN
+EFIAPI
+SmmIsMmioValid (
+  IN EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN UINT64Length,
+  IN EFI_GUID  *Owner  OPTIONAL
+  )
+{
+  UINTN   Index;
+  EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Desc;
+  BOOLEAN InValidRegion;
+
+  //
+  // Check override.
+  // NOTE: (B:0->L:4G) is invalid for IA32, but (B:1->L:4G-1)/(B:4G-1->L:1) is 
valid.
+  //
+  if ((Length > mSmmIoLibInternalMaximumSupportMemAddress) ||
+  (BaseAddress > mSmmIoLibInternalMaximumSupportMemAddress) ||
+  ((Length != 0) && (BaseAddress > 
(mSmmIoLibInternalMaximumSupportMemAddress - (Length - 1 ) {
+//
+// Overflow happen
+//
+DEBUG ((
+  DEBUG_ERROR,
+  "SmmIsMmioValid: Overflow: BaseAddress (0x%lx) - Length (0x%lx), 
MaximumSupportMemAddress (0x%lx)\n",
+  BaseAddress,
+  Length,
+  mSmmIoLibInternalMaximumSupportMemAddress
+  ));
+return FALSE;
+  }
+
+  //
+  // Check override for valid MMIO region
+  //

[edk2] [PATCH V2 3/4] MdePkg/dec: Add SmmIoLib.

[Jiewen Yao]

Cc: Jeff Fan <jeff@intel.com>
Cc: Liming Gao <liming@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdePkg/MdePkg.dec | 4 
 1 file changed, 4 insertions(+)

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 3310029..5774417 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -246,6 +246,10 @@
   #
   SmmMemLib|Include/Library/SmmMemLib.h
 
+  ##  @libraryclass  Provides services for Smm IO Operation.
+  #
+  SmmIoLib|Include/Library/SmmIoLib.h
+
   ##  @libraryclass  Provides services to enable/disable periodic SMI handlers.
   #
   SmmPeriodicSmiLib|Include/Library/SmmPeriodicSmiLib.h
-- 
2.7.4.windows.1

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[edk2] [PATCH V2 0/4] Add SmmIoLib

[Jiewen Yao]

 V2 
Remove ASSERT(FALSE). (From Jeff Fan)

 V1 

This patch series add SmmIoLib.
It is the first part of bugzillar 491.
https://bugzilla.tianocore.org/show_bug.cgi?id=491
Move generic function - OpalIsValidMmioSpace from OPAL
driver to library.

This SmmIoLib is similar to SmmMemLib.

The second part of bugzillar 491 is to update consumer
SecurityPkg/Tcg/Opal/OpalPasswordSmm. It will be
handled in future patch series.

Jiewen Yao (4):
  MdePkg/SmmIoLib: Add header file.
  MdePkg/SmmIoLib: Add sample instance.
  MdePkg/dec: Add SmmIoLib.
  MdePkg/dsc: add SmmIoLib

 MdePkg/Include/Library/SmmIoLib.h|  42 +++
 MdePkg/Library/SmmIoLib/SmmIoLib.c   | 330 
 MdePkg/Library/SmmIoLib/SmmIoLib.inf |  53 
 MdePkg/Library/SmmIoLib/SmmIoLib.uni |  23 ++
 MdePkg/MdePkg.dec|   4 +
 MdePkg/MdePkg.dsc|   1 +
 6 files changed, 453 insertions(+)
 create mode 100644 MdePkg/Include/Library/SmmIoLib.h
 create mode 100644 MdePkg/Library/SmmIoLib/SmmIoLib.c
 create mode 100644 MdePkg/Library/SmmIoLib/SmmIoLib.inf
 create mode 100644 MdePkg/Library/SmmIoLib/SmmIoLib.uni

-- 
2.7.4.windows.1

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[edk2] [PATCH 4/4] MdePkg/dsc: add SmmIoLib

[Jiewen Yao]

Cc: Jeff Fan <jeff@intel.com>
Cc: Liming Gao <liming@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen@intel.com>
---
 MdePkg/MdePkg.dsc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index 8b69de3..d9c2c32 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -154,6 +154,7 @@
   MdePkg/Library/BaseS3SmbusLib/BaseS3SmbusLib.inf
   MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf
   MdePkg/Library/SmmMemLib/SmmMemLib.inf
+  MdePkg/Library/SmmIoLib/SmmIoLib.inf
   MdePkg/Library/BaseRngLib/BaseRngLib.inf
   MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf
   MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf
-- 
2.7.4.windows.1

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