from:"graeme . gregory"

Re: [edk2] [PATCH edk2-platforms v1 00/38] Upload for D06 platform

2018-08-02 Thread Graeme Gregory

On Thu, Aug 02, 2018 at 11:12:56AM +0100, Leif Lindholm wrote:
> On Thu, Aug 02, 2018 at 09:46:13AM +0800, Ming wrote:
> > I am sorry for the first issue, the modify FIRMWARE_VER patch is add
> > alone just befor send out the patchset.
> > 
> > For generating acpi table, I use acpica-tools 20180508 version and it works.
> > I think acpica-tools are not backward compatibility and confused about 
> > acpica-tools.
> 
> Yes, it's a real pain. We used to have lots of issues with this, but
> the last couple of years have been less bad.
> Some platforms moved from .asl to .aslc to get around this.
> 
> I can confirm using 20180508 version resolves this issue.
> And that 20180629 does not work :(
> Unfortunately that won't currently work with our AMD overdrive
> platforms. But we'll have to live with that for now.
> 
This sounds like a bug in IORT support in acpica tools as it works for
other tables.

Graeme

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Re: [edk2] [PATCH edk2-platforms v2 0/7] SynQuacer ACPI support

2018-03-01 Thread Graeme Gregory (Linaro)

On Wed, Feb 28, 2018 at 07:24:14PM +, Ard Biesheuvel wrote:
> This implements ACPI support for the SynQuacer platforms.
> 
> Changes since v1:
> - improve commit log (#1, #2)
> - replace bare numbers with symbolic constants (#2)
> - add Leif's R-b (#4)
> - add patches #6 and #7
> 
> Note that supporting ACPI on this SoC is non-trivial, due to the quirky
> DesignWare RCs and the pre-ITS that sits between the PCIe RCs and the GICv3.
> However, the most important issue has been addressed by modifying the static
> SMMU mapping that sits between the CPUs and the PCIe config space, working
> around the ghosting issue that occurs on these RCs, due the complete lack of
> type 0 config TLP filtering by the [non-existent] root port. (This was tested
> using the 20180226-LB1.1-ACPI-ramfw.bin SCP firmware image, which is not [yet]
> installed by default on DeveloperBox hardware)
> 
> That leaves the MSI issue, which is worked around by limiting MSI support to a
> single RC. In the presented configuration, this is RC #1, which connects to 
> the
> x16 slot [and nothing else] on the DeveloperBox PCB. The onboard PCIe devices
> (XHCI + SATA) work without problem using wired interrupts only, and so RC #0
> has MSI support disabled. This means cards that require MSI support should
> be inserted into the x16 slot, which is likely to be the preferred slot in
> such cases anwyay (e.g., when using NVME or high end networking plugin cards)
> 
> Patch #1 fixes a minor issue in the slot-to-BDF mapping.
> 
> Patch #2 modifies the static PCIe window configuration so it can be described
> using ACPI as well as DT.
> 
> Patch #3 introduces the static ACPI tables that describe the fixed platform
> devices and peripherals to the OS.
> 
> Patch #4 adds a menu option to the platform driver to make ACPI vs DT user
> selectable.
> 
> Patch #5 adds support for describing the eMMC controller using a SSDT table
> which is only installed if eMMC support is enabled.
> 
> Patch #6 adds a _STA method implementation to the PCIe RC devices so that
> they are only exposed to the OS when running on a platform that has one of
> the several ECAM workarounds enabled. Otherwise, we can still boot via ACPI
> using platform devices, but the PCIe RCs are unavailable.
> 
> Patch #7 extends the _STA method for PCI0 to take the presence detect GPIO
> into account. This is necessary because on the SynQuacer evaluation board,
> any attempt to access the device registers will lock up the system if no
> card is inserted into the slot.
> 
> Note that driver support for the eMMC and network controller only landed in
> v4.15, but when using a SATA driver and a plugin network card that does have
> driver support, these patches should allow the SynQuacer based platforms to
> boot stock Debian Stretch/Fedora/Centos etc installers.
> 

The ACPI parts look good to me.

Reviewed-by: Graeme Gregory <graeme.greg...@linaro.org>

> Ard Biesheuvel (7):
>   Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping
>   Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support
>   Silicon/SynQuacer: add ACPI drivers and tables
>   Silicon/SynQuacer/PlatformDxe: add option to enable ACPI mode
>   Silicon/SynQuacer/PlatformDxe: add ACPI description of eMMC
>   Silicon/SynQuacer/AcpiTables: disable PCI RCs if ECAM ghosts are
> detected
>   Silicon/SynQuacer/AcpiTables: take presence detect of PCI0 into
> account
> 
>  Platform/Socionext/DeveloperBox/DeveloperBox.dsc 
> |   2 +
>  Platform/Socionext/DeveloperBox/DeveloperBox.fdf 
> |  14 +
>  Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc 
> |   2 +
>  Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf 
> |  14 +
>  Silicon/Socionext/SynQuacer/Acpi.dsc.inc 
> |  48 +++
>  Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl   
> | 317 
>  Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h  
> |  73 +
>  Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf
> |  65 
>  Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl  
> | 187 
>  Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc 
> |  91 ++
>  Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc 
>

Re: [edk2] [PATCH edk2-platforms v3 13/15] Hisilicon/D05/ACPI: Add ITS PXM

2018-02-07 Thread graeme . gregory

On Tue, Feb 06, 2018 at 03:04:48PM +, Leif Lindholm wrote:
> On Fri, Feb 02, 2018 at 08:05:41PM +0800, Heyi Guo wrote:
> > Add ITS affinity structure in SRAT.
> > 
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Ming Huang <huangmin...@huawei.com>
> > Signed-off-by: Heyi Guo <heyi@linaro.org>
> > Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
> > Reviewed-by: Graeme Gregory <gra...@xora.org.uk>
> 
> Err, a comment - and apologies if I missed this in other patches: this
> should probably be
> Graeme Gregory <graeme.greg...@linaro.org>
> 
> For my part:
> Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
> 

Apologies yes, it should be the @linaro.org version, I must have
kicked off the wrong macro in vi.

Graeme

> > ---
> >  Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 10 ++
> >  Silicon/Hisilicon/Include/Library/AcpiNextLib.h | 10 +-
> >  2 files changed, 19 insertions(+), 1 deletion(-)
> > 
> > diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc 
> > b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
> > index b448a29..8ea0c4b 100644
> > --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
> > +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
> > @@ -121,6 +121,16 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
> >  
> > EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x0003,0x003E,0x0001,0x),
> >//GICC Affinity Processor 62
> >  
> > EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x0003,0x003F,0x0001,0x)
> > //GICC Affinity Processor 63
> >},
> > +  {
> > +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x, 0x),
> > +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0001, 0x0001),
> > +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x, 0x0002),
> > +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0001, 0x0003),
> > +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0002, 0x0004),
> > +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0003, 0x0005),
> > +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0002, 0x0006),
> > +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0003, 0x0007)
> > +  },
> >  };
> >  
> >  //
> > diff --git a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h 
> > b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
> > index 60f9925..fd05a3b 100644
> > --- a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
> > +++ b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
> > @@ -39,6 +39,13 @@
> >   ACPIProcessorUID,  Flags,  ClockDomain
> >  \
> >}
> >  
> > +#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(  
> >  \
> > +ProximityDomain, ItsId)
> >  \
> > +  {
> >  \
> > +4, sizeof (EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE), ProximityDomain,  
> >  \
> > +{EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, ItsId
> >\
> > +  }
> > +
> >  #define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(   
> >\
> >  ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, 
> > LengthHigh, Flags)   \
> >{
> >\
> > @@ -70,12 +77,13 @@
> >  //
> >  #define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT  64
> >  #define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT10
> > -
> > +#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT   8
> >  
> >  typedef struct {
> >EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER  Header;
> >EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE  
> > Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT];
> >EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE
> > Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
> > +  EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE 
> > Its[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT];
> >  } EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
> >  
> >  #pragma pack()
> > -- 
> > 1.9.1
> > 
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Re: [edk2] [PATCH edk2-platforms v2 14/15] Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM

2018-01-30 Thread graeme . gregory

On Fri, Jan 26, 2018 at 04:00:49PM +0800, Ming Huang wrote:
> Add PXM method for Pcie device, HNS device and SAS device.
> Add STA method for HNS.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: hensonwang <wanghuiqi...@huawei.com>
> Signed-off-by: Ming Huang <huangmin...@huawei.com>
> Signed-off-by: Heyi Guo <heyi@linaro.org>
> ---

Looks sane to me

Reviewed-by: Graeme Gregory <gra...@xora.org.uk>

>  Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl |  9 ++
>  Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 34 
> ++--
>  Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 19 +--
>  3 files changed, 57 insertions(+), 5 deletions(-)
> 
> diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl 
> b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
> index 11c28ba..7aa04af 100644
> --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
> +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
> @@ -233,6 +233,15 @@ Scope(_SB)
>}
>  })
>  
> +Method (_PXM, 0, NotSerialized)
> +{
> +  Return(0x00)
> +}
> +Method (_STA, 0, NotSerialized)
> +{
> +  Return(0x0F)
> +}
> +
>  //reset XGE port
>  //Arg0 : XGE port index in dsaf
>  //Arg1 : 0 reset, 1 cancle reset
> diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl 
> b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
> index 55c7f50..122e4f0 100644
> --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
> +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
> @@ -141,7 +141,10 @@ Scope(_SB)
>  {
>Return (0xf)
>  }
> -
> +Method (_PXM, 0, NotSerialized)
> +{
> +  Return(0x00)
> +}
>} // Device(PCI2)
>  
>Device (RES2)
> @@ -240,7 +243,10 @@ Scope(_SB)
>  {
>Return (RBYV())
>  }
> -
> +Method (_PXM, 0, NotSerialized)
> +{
> +  Return(0x01)
> +}
>} // Device(PCI4)
>Device (RES4)
>{
> @@ -338,6 +344,10 @@ Scope(_SB)
>  {
>Return (RBYV())
>  }
> +Method (_PXM, 0, NotSerialized)
> +{
> +  Return(0x01)
> +}
>} // Device(PCI5)
>Device (RES5)
>{
> @@ -435,6 +445,10 @@ Scope(_SB)
>  {
>Return (RBYV())
>  }
> +Method (_PXM, 0, NotSerialized)
> +{
> +  Return(0x01)
> +}
>} // Device(PCI6)
>Device (RES6)
>{
> @@ -531,6 +545,10 @@ Scope(_SB)
>  {
>Return (RBYV())
>  }
> +Method (_PXM, 0, NotSerialized)
> +{
> +  Return(0x01)
> +}
>} // Device(PCI7)
>Device (RES7)
>{
> @@ -690,6 +708,10 @@ Scope(_SB)
>  {
>Return (0xf)
>  }
> +Method (_PXM, 0, NotSerialized)
> +{
> +  Return(0x02)
> +}
>} // Device(PCIa)
>Device (RESa)
>{
> @@ -810,6 +832,10 @@ Scope(_SB)
>  {
>Return (RBYV())
>  }
> +Method (_PXM, 0, NotSerialized)
> +{
> +  Return(0x03)
> +}
>} // Device(PCIc)
>  
>Device (RESc)
> @@ -907,6 +933,10 @@ Scope(_SB)
>  {
>Return (RBYV())
>  }
> +Method (_PXM, 0, NotSerialized)
> +{
> +  Return(0x03)
> +}
>} // Device(PCId)
>Device (RESd)
>{
> diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl 
> b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
> index 6455130..d5b7e2f 100644
> --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
> +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
> @@ -88,7 +88,10 @@ Scope(_SB)
>Store(0x7, CLK)
>Sleep(1)
>  }
> -
> +Method (_PXM, 0, NotSerialized)
> +{
> +  Return(0x00)
> +}
>   Method (_STA, 0, NotSerialized)
>   {
> Return (0x0)
> @@ -169,8 +172,15 @@ Scope(_SB)
>Store(0x7, CLK)
>Sleep(1)
>  }
> +Method (_PXM, 0, NotSerialized)
> +{
> +  Return(0x00)
> +}
> +Method (_STA, 0, NotSerialized)
> +{
> +  Return(0x0F)
> +}
>}
> -
>Device(SAS2) {
>  Name(_HID, "HISI0162")
>  Name(_CCA, 1)
> @@ -244,7 +254,10 @@ Scope(_SB)
>Store(0x7, CLK)
>Sleep(1)
>  }
> -
> +Method (_PXM, 0, NotSerialized)
> +{
> +  Return(0x00)
> +}
>   Method (_STA, 0, NotSerialized)
>   {
> Return (0x0)
> -- 
> 1.9.1
> 


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Re: [edk2] [PATCH edk2-platforms v2 13/15] Hisilicon/D05/ACPI: Add ITS PXM

2018-01-30 Thread graeme . gregory

On Fri, Jan 26, 2018 at 04:00:48PM +0800, Ming Huang wrote:
> Add ITS affinity structure in SRAT.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang <huangmin...@huawei.com>
> Signed-off-by: Heyi Guo <heyi@linaro.org>
> ---

Looks sane to me.

Reviewed-by: Graeme Gregory <gra...@xora.org.uk>

>  Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 10 ++
>  Silicon/Hisilicon/Include/Library/AcpiNextLib.h | 10 +-
>  2 files changed, 19 insertions(+), 1 deletion(-)
> 
> diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc 
> b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
> index b448a29..8ea0c4b 100644
> --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
> +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
> @@ -121,6 +121,16 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
>  
> EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x0003,0x003E,0x0001,0x),
>//GICC Affinity Processor 62
>  
> EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x0003,0x003F,0x0001,0x)
> //GICC Affinity Processor 63
>},
> +  {
> +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x, 0x),
> +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0001, 0x0001),
> +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x, 0x0002),
> +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0001, 0x0003),
> +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0002, 0x0004),
> +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0003, 0x0005),
> +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0002, 0x0006),
> +EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0003, 0x0007)
> +  },
>  };
>  
>  //
> diff --git a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h 
> b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
> index 60f9925..fd05a3b 100644
> --- a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
> +++ b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
> @@ -39,6 +39,13 @@
>   ACPIProcessorUID,  Flags,  ClockDomain  
>\
>}
>  
> +#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(
>\
> +ProximityDomain, ItsId)  
>\
> +  {  
>\
> +4, sizeof (EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE), ProximityDomain,
>\
> +{EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, ItsId  
>  \
> +  }
> +
>  #define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( 
>  \
>  ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, 
> Flags)   \
>{  
>  \
> @@ -70,12 +77,13 @@
>  //
>  #define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT  64
>  #define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT10
> -
> +#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT   8
>  
>  typedef struct {
>EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER  Header;
>EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE  
> Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT];
>EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE
> Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
> +  EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE 
> Its[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT];
>  } EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
>  
>  #pragma pack()
> -- 
> 1.9.1
> 


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Re: [edk2] [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support

2018-01-30 Thread graeme . gregory

On Fri, Jan 26, 2018 at 04:00:37PM +0800, Ming Huang wrote:
> Add Processor Properties Topology Table, PPTT include
> Processor hierarchy node, Cache Type Structure and ID structure.
> 
> PPTT is needed for lscpu command to show socket information correctly.
> https://bugs.linaro.org/show_bug.cgi?id=3206
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang <huangmin...@huawei.com>
> Signed-off-by: Heyi Guo <heyi@linaro.org>
> ---

Code looks sane enough to me, but I cant give an indepth review of the
PPTT bit.


Reviewed-by: Graeme Gregory <gra...@xora.org.uk>


>  Platform/Hisilicon/D05/D05.dsc |   1 +
>  Platform/Hisilicon/D05/D05.fdf |   1 +
>  Silicon/Hisilicon/Hi1616/Pptt/Pptt.c   | 540 
>  Silicon/Hisilicon/Hi1616/Pptt/Pptt.h   |  88 
>  Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf |  48 ++
>  5 files changed, 678 insertions(+)
> 
> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
> index 77a89fd..710339c 100644
> --- a/Platform/Hisilicon/D05/D05.dsc
> +++ b/Platform/Hisilicon/D05/D05.dsc
> @@ -506,6 +506,7 @@
>MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
>  
>Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
> +  Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
>Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>  
>#
> diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
> index 78ab0c8..97de4d2 100644
> --- a/Platform/Hisilicon/D05/D05.fdf
> +++ b/Platform/Hisilicon/D05/D05.fdf
> @@ -241,6 +241,7 @@ READ_LOCK_STATUS   = TRUE
>INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
>  
>INF RuleOverride=ACPITABLE 
> Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
> +  INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
>INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>  
>#
> diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c 
> b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
> new file mode 100644
> index 000..71c456c
> --- /dev/null
> +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
> @@ -0,0 +1,540 @@
> +/** @file
> +*
> +*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +*  Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +*  This program and the accompanying materials
> +*  are licensed and made available under the terms and conditions of the BSD 
> License
> +*  which accompanies this distribution.  The full text of the license may be 
> found at
> +*  http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> IMPLIED.
> +*
> +*  Based on the files under Platform/ARM/JunoPkg/AcpiTables/
> +*
> +**/
> +
> +#include "Pptt.h"
> +
> +EFI_ACPI_TABLE_PROTOCOL   *mAcpiTableProtocol = NULL;
> +EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol   = NULL;
> +
> +EFI_ACPI_DESCRIPTION_HEADER mPpttHeader =
> +  ARM_ACPI_HEADER (
> +EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
> +EFI_ACPI_DESCRIPTION_HEADER,
> +EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
> +  );
> +
> +EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] =
> +{
> +  {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, 0, 0, 0, 0, 0, 0}
> +};
> +
> +EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO];
> +
> +
> +STATIC
> +VOID
> +InitCacheInfo (
> +  VOID
> +  )
> +{
> +  UINT8Index;
> +  EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
> +  CSSELR_DATA  CsselrData;
> +  CCSIDR_DATA  CcsidrData;
> +
> +  for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
> +CsselrData.Data = 0;
> +CcsidrData.Data = 0;
> +SetMem (
> +  ,
> +  sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
> +  0
> +  );
> +
> +if (Index == 0) { //L1I
> +  CsselrData.Bits.InD = 1;
> +  CsselrData.Bits.Level = 0;
> +  Type1Attributes.CacheType  = 1;
> +} else if (Index == 1) {
> +  Type1Attributes.CacheType  = 0;
> +  CsselrData.Bits.Level = Index - 1;
> +} else {
> +  Type1Attributes.CacheType  = 2;
> +  CsselrData.Bits.Level = Index - 1;
> +}
> +
> +CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
> +
> +if (CcsidrData.Bits.Wa == 1) {
> +  Type1Attributes.AllocationType  = PPTT_TYPE1_ALLOCATION_WRITE;
&

Re: [edk2] [PATCH edk2-platforms v2 01/15] Hisilicon/D05: Move Madt definition to head file

2018-01-30 Thread graeme . gregory

On Fri, Jan 26, 2018 at 04:00:36PM +0800, Ming Huang wrote:
> Move definition of Madt struct to head file, so PPTT driver
> can include it.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang <huangmin...@huawei.com>
> Signed-off-by: Heyi Guo <heyi@linaro.org>
> ---
Looks sane to me

Reviewed-by: Graeme Gregory <gra...@xora.org.uk>

>  Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h | 30 
> +++-
>  Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc  | 23 +--
>  2 files changed, 30 insertions(+), 23 deletions(-)
> 
> diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h 
> b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
> index 808219a..ad73aa2 100644
> --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
> +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
> @@ -1,7 +1,7 @@
>  /** @file
>  *
>  *  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
> -*  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
> +*  Copyright (c) 2015-2018, Hisilicon Limited. All rights reserved.
>  *  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
>  *
>  *  This program and the accompanying materials
> @@ -20,6 +20,8 @@
>  #ifndef _HI1610_PLATFORM_H_
>  #define _HI1610_PLATFORM_H_
>  
> +#include 
> +
>  //
>  // ACPI table information used to initialize tables.
>  //
> @@ -44,5 +46,31 @@
>}
>  
>  #define HI1616_WATCHDOG_COUNT  2
> +#define HI1616_GIC_STRUCTURE_COUNT  64
> +
> +#define HI1616_MPID_TA_BASE  0x1
> +#define HI1616_MPID_TB_BASE  0x3
> +#define HI1616_MPID_TA_2_BASE  0x5
> +#define HI1616_MPID_TB_2_BASE  0x7
> +
> +// Differs from Juno, we have another affinity level beyond cluster and core
> +#define PLATFORM_GET_MPID_TA(ClusterId, CoreId)   (HI1616_MPID_TA_BASE | 
> ((ClusterId) << 8) | (CoreId))
> +#define PLATFORM_GET_MPID_TB(ClusterId, CoreId)   (HI1616_MPID_TB_BASE | 
> ((ClusterId) << 8) | (CoreId))
> +#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId)   (HI1616_MPID_TA_2_BASE | 
> ((ClusterId) << 8) | (CoreId))
> +#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId)   (HI1616_MPID_TB_2_BASE | 
> ((ClusterId) << 8) | (CoreId))
> +
> +//
> +// Multiple APIC Description Table
> +//
> +#pragma pack (1)
> +
> +typedef struct {
> +  EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
> +  EFI_ACPI_6_1_GIC_STRUCTURE
> GicInterfaces[HI1616_GIC_STRUCTURE_COUNT];
> +  EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
> +  EFI_ACPI_6_1_GIC_ITS_STRUCTUREGicITS[8];
> +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
> +
> +#pragma pack ()
>  
>  #endif
> diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc 
> b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
> index 169ee72..54605a6 100644
> --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
> +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
> @@ -2,7 +2,7 @@
>  *  Multiple APIC Description Table (MADT)
>  *
>  *  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
> -*  Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved.
> +*  Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved.
>  *  Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved.
>  *
>  *  This program and the accompanying materials
> @@ -27,27 +27,6 @@
>  #include 
>  #include "Hi1616Platform.h"
>  
> -// Differs from Juno, we have another affinity level beyond cluster and core
> -// 0x2 is only for socket 0
> -#define PLATFORM_GET_MPID_TA(ClusterId, CoreId)   (0x1 | ((ClusterId) << 
> 8) | (CoreId))
> -#define PLATFORM_GET_MPID_TB(ClusterId, CoreId)   (0x3 | ((ClusterId) << 
> 8) | (CoreId))
> -#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId)   (0x5 | ((ClusterId) 
> << 8) | (CoreId))
> -#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId)   (0x7 | ((ClusterId) 
> << 8) | (CoreId))
> -
> -//
> -// Multiple APIC Description Table
> -//
> -#pragma pack (1)
> -
> -typedef struct {
> -  EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
> -  EFI_ACPI_6_1_GIC_STRUCTUREGicInterfaces[64];
> -  EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
> -  EFI_ACPI_6_1_GIC_ITS_STRUCTURE  GicITS[8];
> -} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
> -
> -#pragma pack ()
> -
>  EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
>{
>  ARM_ACPI_HEADER (
> -- 
> 1.9.1
> 


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Re: [edk2] [PATCH edk2-platforms v1 01/14] Hisilicon/D05: Add PPTT support

2018-01-24 Thread graeme . gregory

On Mon, Jan 22, 2018 at 01:53:18PM +, Leif Lindholm wrote:
> Detailed commit description, please.
> 
> Graeme - any comments on ACPIness?
> 
I think Jeremy probably gave it a much more in depth review than I can
below.

Once he is happy Ill be happy.

Graeme

> On Thu, Jan 18, 2018 at 11:01:30PM +0800, Ming Huang wrote:
> > From: Jason Zhang 
> > 
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Jason Zhang 
> > Signed-off-by: Ming Huang 
> > Signed-off-by: Heyi Guo 
> > ---
> >  Platform/Hisilicon/D05/D05.dsc  |   1 +
> >  Platform/Hisilicon/D05/D05.fdf  |   1 +
> >  Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h |  27 ++
> >  Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc  |  31 +-
> >  Silicon/Hisilicon/Hi1616/Pptt/Pptt.c| 447 
> > 
> >  Silicon/Hisilicon/Hi1616/Pptt/Pptt.h| 142 +++
> >  Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf  |  55 +++
> >  7 files changed, 677 insertions(+), 27 deletions(-)
> > 
> > diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
> > index 77a89fd..710339c 100644
> > --- a/Platform/Hisilicon/D05/D05.dsc
> > +++ b/Platform/Hisilicon/D05/D05.dsc
> > @@ -506,6 +506,7 @@
> >MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
> >  
> >Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
> > +  Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
> >Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
> >  
> >#
> > diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
> > index 78ab0c8..97de4d2 100644
> > --- a/Platform/Hisilicon/D05/D05.fdf
> > +++ b/Platform/Hisilicon/D05/D05.fdf
> > @@ -241,6 +241,7 @@ READ_LOCK_STATUS   = TRUE
> >INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
> >  
> >INF RuleOverride=ACPITABLE 
> > Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
> > +  INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
> >INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
> >  
> >#
> > diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h 
> > b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
> > index 808219a..f1927e8 100644
> > --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
> > +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
> 
> As far as I can tell, all of the changes to this file (and the
> resulting counterpart in
> Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc) are
> non-functional.
> 
> Please break these changes out as a separate patch.
> This is good cleanup, but unrelated to the stated change.
> 
> > @@ -19,6 +19,7 @@
> >  
> >  #ifndef _HI1610_PLATFORM_H_
> >  #define _HI1610_PLATFORM_H_
> > +#include 
> >  
> >  //
> >  // ACPI table information used to initialize tables.
> > @@ -44,5 +45,31 @@
> >}
> >  
> >  #define HI1616_WATCHDOG_COUNT  2
> > +#define HI1616_GIC_STRUCTURE_COUNT  64
> > +
> > +#define HI1616_MPID_TA_BASE  0x1
> > +#define HI1616_MPID_TB_BASE  0x3
> > +#define HI1616_MPID_TA_2_BASE  0x5
> > +#define HI1616_MPID_TB_2_BASE  0x7
> > +
> > +// Differs from Juno, we have another affinity level beyond cluster and 
> > core
> > +#define PLATFORM_GET_MPID_TA(ClusterId, CoreId)   (HI1616_MPID_TA_BASE | 
> > ((ClusterId) << 8) | (CoreId))
> > +#define PLATFORM_GET_MPID_TB(ClusterId, CoreId)   (HI1616_MPID_TB_BASE | 
> > ((ClusterId) << 8) | (CoreId))
> > +#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId)   (HI1616_MPID_TA_2_BASE 
> > | ((ClusterId) << 8) | (CoreId))
> > +#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId)   (HI1616_MPID_TB_2_BASE 
> > | ((ClusterId) << 8) | (CoreId))
> > +
> > +//
> > +// Multiple APIC Description Table
> > +//
> > +#pragma pack (1)
> > +
> > +typedef struct {
> > +  EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
> > +  EFI_ACPI_6_1_GIC_STRUCTURE
> > GicInterfaces[HI1616_GIC_STRUCTURE_COUNT];
> > +  EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
> > +  EFI_ACPI_6_1_GIC_ITS_STRUCTUREGicITS[8];
> > +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
> > +
> > +#pragma pack ()
> >  
> >  #endif
> > diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc 
> > b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
> > index 169ee72..33dca03 100644
> > --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
> > +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
> > @@ -1,9 +1,9 @@
> >  /** @file
> >  *  Multiple APIC Description Table (MADT)
> >  *
> > -*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
> > -*  Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved.
> > -*  Copyright (c) 2015 - 2016, Linaro Limited.

Re: [edk2] [PATCH edk2-platforms v3 12/27] Silicon/SynQuacer: add ACPI support

2017-11-01 Thread graeme . gregory

I see nothing wrong with the ACPI in this patch, but I question the
sanity of exposing ACPI on this SoC where it seems to be not suited.

Given the comment in the commit message would an alternative OS like
windows actually work with this PCIe setup?

Graeme

On Tue, Oct 31, 2017 at 10:52:03AM +, Ard Biesheuvel wrote:
> Enable ACPI support for the SynQuacerEvalBoard platform: add descriptions
> of the CPUs, the GIC, the serial port, the timers and the PCIe RCs,
> including the MSI routing via the GICv3 ITS.
> 
> Note that PCIe support is limited to a single bus per RC. Anything beyond
> that is unsupported due to a limitation in the hardware that makes it
> impossible to expose the PCIe RCs in a fully ECAM compliant manner.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 
> ---
>  Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc |  15 +
>  Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf |  14 +
>  Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl   | 294 
> 
>  Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h  |  58 
>  Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf|  62 +
>  Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl  | 167 
> +++
>  Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc |  89 ++
>  Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc |  98 +++
>  Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 164 
> +++
>  Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc | 152 ++
>  Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc |  63 +
>  Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc | 127 +
>  12 files changed, 1303 insertions(+)
> 
> diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc 
> b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
> index f8579e5739b5..02db912562bd 100644
> --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
> +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
> @@ -529,3 +529,18 @@ [Components.common]
>  
>DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
>}
> +
> +  #
> +  # ACPI support
> +  #
> +  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
> +
> +  #NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
> +
> +
> +  # support ACPI v5.0 or later
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
> +  }
> +  MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
> +  Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf
> +  
> MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
> diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf 
> b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
> index 3e1af577371a..2935f19139b6 100644
> --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
> +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
> @@ -198,6 +198,14 @@ [FV.FvMain]
>INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf
>INF Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
>  
> +  #
> +  # ACPI support
> +  #
> +  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
> +  INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
> +  INF RuleOverride = ACPITABLE 
> Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf
> +  INF 
> MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
> +
>  [FV.FVMAIN_PEI]
>  FvAlignment= 16
>  ERASE_POLARITY = 1
> @@ -354,3 +362,9 @@ [Rule.Common.UEFI_APPLICATION.BINARY]
>  UISTRING="$(MODULE_NAME)" Optional
>  VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
>}
> +
> +[Rule.Common.USER_DEFINED.ACPITABLE]
> +  FILE FREEFORM = $(NAMED_GUID) {
> +RAW ACPI   |.acpi
> +RAW ASL|.aml
> +  }
> diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl 
> b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
> new file mode 100644
> index ..fb845d2c107e
> --- /dev/null
> +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
> @@ -0,0 +1,294 @@
> +/** @file
> +  Secondary System Description Table (SSDT) for SynQuacer PCIe RCs
> +
> +  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
> +  Copyright (c) 2017, Linaro Ltd. All rights reserved.
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD 
> License
> +  which accompanies this distribution.  The full text of the license may be 
> found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS

Re: [edk2] [PATCH 0/2] Add FPDT Acpi table

2017-10-09 Thread Graeme Gregory

On 22 September 2017 at 17:18,  <evan.ll...@arm.com> wrote:
> From: EvanLloyd <evan.ll...@arm.com>
>
>
> Paired patches for edk2 and edk2-platforms that add an FPDT
> acpi table.
> This is useful for monitoring firmware performance, etc.
>
>From ACPI on ARM point of view this looks fine to me.

Reviewed-by: Graeme Gregory <graeme.greg...@linaro.org>

>
> Alexei Fedorov (1):
>   ArmPlatformPkg: Store initial timer value
>
>  ArmPlatformPkg/PrePi/PeiMPCore.inf  |  3 ++-
>  ArmPlatformPkg/PrePi/PeiUniCore.inf |  3 ++-
>  ArmPlatformPkg/PrePi/PrePi.c| 10 +-
>  3 files changed, 13 insertions(+), 3 deletions(-)
>
> See https://github.com/EvanLloyd/tianocore/tree/164_FPDT_v1
>
> Alexei Fedorov (1):
>   ARM/JunoPkg: Add support for FPDT table.
>
>  Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc | 9 -
>  Platform/ARM/JunoPkg/ArmJuno.dsc | 9 +
>  Platform/ARM/JunoPkg/ArmJuno.fdf | 6 ++
>  3 files changed, 23 insertions(+), 1 deletion(-)
>
> See https://github.com/EvanLloyd/edk2-platforms/tree/164_FPDT_v1
>
> --
> Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")
>
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Re: [edk2] [PATCH edk2-platforms v3 00/11] Update D03/D05 binary for edk2 update and bug fix.

2017-09-21 Thread graeme . gregory

All ACPI changes apart from the small comment I had on I2C one

Reviewed-by: Graeme Gregory <graeme.greg...@linaro.org>

On Thu, Sep 21, 2017 at 06:59:39PM +0800, Heyi Guo wrote:
> Code can also be found in github:
> https://github.com/hisilicon/OpenPlatformPkg.git
> branch: rp-1710-platforms-v3rp-1710-osi-v3
> 
> Note: If occurs BIOS boot hang up issue, please revert below commit to fix:
>   "2f03dc8"
> 
> Chenhui Sun (1):
>   Hisilicon/D03: Disable the function of PerfTuning
> 
> Heyi Guo (4):
>   Hisilicon/D05: Modify dsc and fdf file
>   Hisilicon/D03: Modify dsc and fdf file
>   Hisilicon: Fix the drivers use the same GUID issue
>   Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase
> 
> Ming Huang (4):
>   Hisilicon D03/D05: get firmware version from FIRMWARE_VER
>   D05/ACPI: Disable D05 SAS0 and SAS2
>   D05/ACPI: Modify I2C device
>   Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device.
> 
> huangming (2):
>   Hisilicon/D05/Pcie: fix bug of size definition
>   D05/PCIe: Modify PcieRegionBase of secondary chip
> 
>  Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf  
> |  2 +-
>  Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf 
> |  2 +-
>  Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf
> |  2 +-
>  Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf  
> |  2 +-
>  Platform/Hisilicon/D03/D03.dsc  
> | 13 ++-
>  Platform/Hisilicon/D03/D03.fdf  
> |  5 +-
>  Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf
> |  2 +-
>  Platform/Hisilicon/D05/D05.dsc  
> | 83 +
>  Platform/Hisilicon/D05/D05.fdf  
> |  4 +-
>  Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf   
> |  2 +-
>  Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf  
> |  2 +-
>  Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
> |  2 +-
>  Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c  
> | 38 
>  Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h  
> |  7 ++
>  Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
> | 94 +++-
>  Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
> |  2 +-
>  Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf   
> |  2 +-
>  Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl  
> | 20 +
>  Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl  
> |  8 +-
>  Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl  
> | 10 +++
>  Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf 
> |  2 +-
>  Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf   
> |  2 +-
>  Silicon/Hisilicon/Library/I2CLib/I2CLib.inf 
> |  2 +-
>  Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf  
> |  2 +-
>  24 files changed, 205 insertions(+), 105 deletions(-)
> 
> -- 
> 1.9.1
> 


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Re: [edk2] [PATCH edk2-platforms v1 00/38] Upload for D06 platform

Re: [edk2] [PATCH edk2-platforms v2 0/7] SynQuacer ACPI support

Re: [edk2] [PATCH edk2-platforms v3 13/15] Hisilicon/D05/ACPI: Add ITS PXM

Re: [edk2] [PATCH edk2-platforms v2 14/15] Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM

Re: [edk2] [PATCH edk2-platforms v2 13/15] Hisilicon/D05/ACPI: Add ITS PXM

Re: [edk2] [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support

Re: [edk2] [PATCH edk2-platforms v2 01/15] Hisilicon/D05: Move Madt definition to head file

Re: [edk2] [PATCH edk2-platforms v1 01/14] Hisilicon/D05: Add PPTT support

Re: [edk2] [PATCH edk2-platforms v3 12/27] Silicon/SynQuacer: add ACPI support

Re: [edk2] [PATCH 0/2] Add FPDT Acpi table

Re: [edk2] [PATCH edk2-platforms v3 00/11] Update D03/D05 binary for edk2 update and bug fix.

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