subject:"\[edk2\] \[Patch\] UefiCpuPkg\/Include\: Add VMX MSR register structures"

Re: [edk2] [Patch] UefiCpuPkg/Include: Add VMX MSR register structures

2016-11-30 Thread Fan, Jeff

Reviewed-by: Jeff Fan 

-Original Message-
From: Kinney, Michael D 
Sent: Wednesday, November 30, 2016 3:29 PM
To: edk2-devel@lists.01.org
Cc: Yao, Jiewen; Fan, Jeff; Tian, Feng
Subject: [Patch] UefiCpuPkg/Include: Add VMX MSR register structures

Add MSR_IA32_VMX_BASIC_REGISTER and IA32_VMX_MISC_REGISTER
structures with the bit fields for these two MSRs.   Also
add MSEG_HEADER structure whose base address is in the MsegBase field of 
MSR_IA32_SMM_MONITOR_CTL_REGISTER.

Cc: Jiewen Yao 
Cc: Jeff Fan 
Cc: Feng Tian 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 224 -
 1 file changed, 219 insertions(+), 5 deletions(-)

diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h 
b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index 7de1c4b..a7a221d 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -19,6 +19,14 @@
   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
   December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.
 
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, 
+ Volume 3,  December 2015, Appendix A VMX Capability Reporting Facility, 
Section A.1.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, 
+ Volume 3,  December 2015, Appendix A VMX Capability Reporting Facility, 
Section A.6.
+
 **/
 
 #ifndef __ARCHITECTURAL_MSR_H__
@@ -411,7 +419,7 @@ typedef union {
 
 
 /**
-  SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1. CPUID.01H: ECX[6] =
+  SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: 
+ ECX[6] =
   1.
 
   @param  ECX  MSR_IA32_SMM_MONITOR_CTL (0x009B) @@ -471,6 +479,25 @@ 
typedef union {
   UINT64  Uint64;
 } MSR_IA32_SMM_MONITOR_CTL_REGISTER;
 
+/**
+  MSEG header that is located at the physical address specified by the 
+MsegBase
+  field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.
+**/
+typedef struct {
+  UINT32  MsegHeaderRevision;
+  UINT32  MonitorFeatures;
+  UINT32  GdtrLimit;
+  UINT32  GdtrBaseOffset;
+  UINT32  CsSelector;
+  UINT32  EipOffset;
+  UINT32  EspOffset;
+  UINT32  Cr3Offset;
+  //
+  // Pad header so total size is 2KB
+  //
+  UINT8   Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
+} MSEG_HEADER;
+
 
 /**
   Base address of the logical processor's SMRAM image (RO, SMM only). If @@ 
-3681,14 +3708,119 @@ typedef union {
 
   Example usage
   @code
-  UINT64  Msr;
+  MSR_IA32_VMX_BASIC_REGISTER  Msr;
 
-  Msr = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
   @endcode
   @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.
 **/
 #define MSR_IA32_VMX_BASIC   0x0480
 
+/**
+  MSR information returned for MSR index #MSR_IA32_VMX_BASIC **/ 
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bits 30:0] VMCS revision identifier used by the processor.  Processors
+/// that use the same VMCS revision identifier use the same size for VMCS
+/// regions (see subsequent item on bits 44:32).
+///
+/// @note Earlier versions of this manual specified that the VMCS revision
+/// identifier was a 32-bit field in bits 31:0 of this MSR. For all
+/// processors produced prior to this change, bit 31 of this MSR was read
+/// as 0.
+///
+UINT32  VmcsRevisonId:31;
+UINT32  MustBeZero:1;
+///
+/// [Bit 44:32] Reports the number of bytes that software should allocate
+/// for the VMXON region and any VMCS region.  It is a value greater than
+/// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).
+///
+UINT32  VmcsSize:13;
+UINT32  Reserved1:3;
+///
+/// [Bit 48] Indicates the width of the physical addresses that may be used
+/// for the VMXON region, each VMCS, and data structures referenced by
+/// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX
+/// transitions).  If the bit is 0, these addresses are limited to the
+/// processor's physical-address width.  If the bit is 1, these addresses
+/// are limited to 32 bits. This bit is always 0 for processors that
+/// support Intel 64 architecture.
+///
+/// @note On processors that support Intel 64 architecture, the pointer
+/// must not set bits beyond the processor's physical address width.
+///
+UINT32  VmcsAddressWidth:1;
+///
+/// [Bit 49] If bit 49 is read as 1, the logical processor supports the
+/// dual-monitor treatment of system-management interrupts and
+/// system-management mode. See Section 34.15 for details of this 
treatment.
+///
+UINT32  DualMonitor:1;
+///
+

[edk2] [Patch] UefiCpuPkg/Include: Add VMX MSR register structures

2016-11-29 Thread Michael Kinney

Add MSR_IA32_VMX_BASIC_REGISTER and IA32_VMX_MISC_REGISTER
structures with the bit fields for these two MSRs.   Also
add MSEG_HEADER structure whose base address is in the
MsegBase field of MSR_IA32_SMM_MONITOR_CTL_REGISTER.

Cc: Jiewen Yao 
Cc: Jeff Fan 
Cc: Feng Tian 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 224 -
 1 file changed, 219 insertions(+), 5 deletions(-)

diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h 
b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index 7de1c4b..a7a221d 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -19,6 +19,14 @@
   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
   December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.
 
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Appendix A VMX Capability Reporting Facility, Section A.1.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Appendix A VMX Capability Reporting Facility, Section A.6.
+
 **/
 
 #ifndef __ARCHITECTURAL_MSR_H__
@@ -411,7 +419,7 @@ typedef union {
 
 
 /**
-  SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1. CPUID.01H: ECX[6] =
+  SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] 
=
   1.
 
   @param  ECX  MSR_IA32_SMM_MONITOR_CTL (0x009B)
@@ -471,6 +479,25 @@ typedef union {
   UINT64  Uint64;
 } MSR_IA32_SMM_MONITOR_CTL_REGISTER;
 
+/**
+  MSEG header that is located at the physical address specified by the MsegBase
+  field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.
+**/
+typedef struct {
+  UINT32  MsegHeaderRevision;
+  UINT32  MonitorFeatures;
+  UINT32  GdtrLimit;
+  UINT32  GdtrBaseOffset;
+  UINT32  CsSelector;
+  UINT32  EipOffset;
+  UINT32  EspOffset;
+  UINT32  Cr3Offset;
+  //
+  // Pad header so total size is 2KB
+  //
+  UINT8   Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
+} MSEG_HEADER;
+
 
 /**
   Base address of the logical processor's SMRAM image (RO, SMM only). If
@@ -3681,14 +3708,119 @@ typedef union {
 
   Example usage
   @code
-  UINT64  Msr;
+  MSR_IA32_VMX_BASIC_REGISTER  Msr;
 
-  Msr = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
   @endcode
   @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.
 **/
 #define MSR_IA32_VMX_BASIC   0x0480
 
+/**
+  MSR information returned for MSR index #MSR_IA32_VMX_BASIC
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bits 30:0] VMCS revision identifier used by the processor.  Processors
+/// that use the same VMCS revision identifier use the same size for VMCS
+/// regions (see subsequent item on bits 44:32).
+///
+/// @note Earlier versions of this manual specified that the VMCS revision
+/// identifier was a 32-bit field in bits 31:0 of this MSR. For all
+/// processors produced prior to this change, bit 31 of this MSR was read
+/// as 0.
+///
+UINT32  VmcsRevisonId:31;
+UINT32  MustBeZero:1;
+///
+/// [Bit 44:32] Reports the number of bytes that software should allocate
+/// for the VMXON region and any VMCS region.  It is a value greater than
+/// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).
+///
+UINT32  VmcsSize:13;
+UINT32  Reserved1:3;
+///
+/// [Bit 48] Indicates the width of the physical addresses that may be used
+/// for the VMXON region, each VMCS, and data structures referenced by
+/// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX
+/// transitions).  If the bit is 0, these addresses are limited to the
+/// processor's physical-address width.  If the bit is 1, these addresses
+/// are limited to 32 bits. This bit is always 0 for processors that
+/// support Intel 64 architecture.
+///
+/// @note On processors that support Intel 64 architecture, the pointer
+/// must not set bits beyond the processor's physical address width.
+///
+UINT32  VmcsAddressWidth:1;
+///
+/// [Bit 49] If bit 49 is read as 1, the logical processor supports the
+/// dual-monitor treatment of system-management interrupts and
+/// system-management mode. See Section 34.15 for details of this 
treatment.
+///
+UINT32  DualMonitor:1;
+///
+/// [Bit 53:50] report the memory type that should be used for the VMCS,
+/// for data structures referenced by pointers in the VMCS (I/O bitmaps,
+/// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG
+/// header. If software needs to access these data

Re: [edk2] [Patch] UefiCpuPkg/Include: Add VMX MSR register structures

[edk2] [Patch] UefiCpuPkg/Include: Add VMX MSR register structures

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