Now that the AArch64 MMU code correctly identifies and handles
naturally aligned regions of more than 2 MB in size, it will happily
try to use block mappings at level 0 to map huge memory regions, such
as the single cacheable 1:1 mapping we use for Xen domU to map the
entire PA space. However,
On 2 October 2015 at 16:44, Leif Lindholm wrote:
> On Fri, Oct 02, 2015 at 02:50:35PM +0200, Ard Biesheuvel wrote:
>> Now that the AArch64 MMU code correctly identifies and handles
>> naturally aligned regions of more than 2 MB in size, it will happily
>> try to use
On Fri, Oct 02, 2015 at 02:50:35PM +0200, Ard Biesheuvel wrote:
> Now that the AArch64 MMU code correctly identifies and handles
> naturally aligned regions of more than 2 MB in size, it will happily
> try to use block mappings at level 0 to map huge memory regions, such
> as the single cacheable
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