Disable the RVCT size optimization that may put sections at an offset
that is not aligned to their own alignment, by adding the --no_legacyalign
switch to the RVCT linker command line. This is necessary since such sections
cannot be correctly converted into PE/COFF sections without padding them at
the front, which defeats the purpose of the optimization anyway.
With the optimization gone, we can also remove the special case for ARM in
GenFw that could result in corrupt PE/COFF images to be emitted. Instead,
sections whose base address is not aligned correctly are outright rejected.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
---
BaseTools/Conf/tools_def.template | 2 +-
BaseTools/Source/C/GenFw/Elf32Convert.c | 29 +++++---------------
2 files changed, 8 insertions(+), 23 deletions(-)
diff --git a/BaseTools/Conf/tools_def.template
b/BaseTools/Conf/tools_def.template
index aa2b6b1488c4..cf4914415e5f 100644
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -6609,7 +6609,7 @@ RELEASE_XCODE5_X64_CC_FLAGS = -target
x86_64-pc-win32-macho -c -Os -W
DEFINE RVCT_ALL_ASM_FLAGS = --diag_suppress=1786 --diag_error=warning --apcs
/interwork
DEFINE RVCT_ALL_CC_FLAGS = --c90 -c --no_autoinline --asm --gnu --apcs
/interwork --signed_chars --no_unaligned_access --split_sections --enum_is_int
--preinclude AutoGen.h --diag_suppress=186 --diag_warning 167
--diag_error=warning --diag_style=ide --protect_stack
-DEFINE RVCT_ALL_DLINK_FLAGS = --ro-base 0 --no_scanlib --reloc --no_exceptions
--datacompressor off --strict --symbols --diag_style=ide
+DEFINE RVCT_ALL_DLINK_FLAGS = --ro-base 0 --no_scanlib --reloc --no_exceptions
--datacompressor off --strict --symbols --diag_style=ide --no_legacyalign
####################################################################################
#
diff --git a/BaseTools/Source/C/GenFw/Elf32Convert.c
b/BaseTools/Source/C/GenFw/Elf32Convert.c
index 4b330a61669f..a7b077873b40 100644
--- a/BaseTools/Source/C/GenFw/Elf32Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf32Convert.c
@@ -340,12 +340,8 @@ ScanSections32 (
if ((shdr->sh_addr & (shdr->sh_addralign - 1)) == 0) {
// if the section address is aligned we must align PE/COFF
mCoffOffset = (mCoffOffset + shdr->sh_addralign - 1) &
~(shdr->sh_addralign - 1);
- } else if ((shdr->sh_addr % shdr->sh_addralign) != (mCoffOffset %
shdr->sh_addralign)) {
- // ARM RVCT tools have behavior outside of the ELF specification to
try
- // and make images smaller. If sh_addr is not aligned to
sh_addralign
- // then the section needs to preserve sh_addr MOD sh_addralign.
- // Normally doing nothing here works great.
- Error (NULL, 0, 3000, "Invalid", "Unsupported section alignment.");
+ } else {
+ Error (NULL, 0, 3000, "Invalid", "Section address not aligned to its
own alignment.");
}
}
@@ -375,10 +371,7 @@ ScanSections32 (
}
mDebugOffset = DebugRvaAlign(mCoffOffset);
-
- if (mEhdr->e_machine != EM_ARM) {
- mCoffOffset = CoffAlign(mCoffOffset);
- }
+ mCoffOffset = CoffAlign(mCoffOffset);
if (SectionCount > 1 && mOutImageType == FW_EFI_IMAGE) {
Warning (NULL, 0, 0, NULL, "Mulitple sections in %s are merged into 1 text
section. Source level debug might not work correctly.", mInImageName);
@@ -398,12 +391,8 @@ ScanSections32 (
if ((shdr->sh_addr & (shdr->sh_addralign - 1)) == 0) {
// if the section address is aligned we must align PE/COFF
mCoffOffset = (mCoffOffset + shdr->sh_addralign - 1) &
~(shdr->sh_addralign - 1);
- } else if ((shdr->sh_addr % shdr->sh_addralign) != (mCoffOffset %
shdr->sh_addralign)) {
- // ARM RVCT tools have behavior outside of the ELF specification to
try
- // and make images smaller. If sh_addr is not aligned to
sh_addralign
- // then the section needs to preserve sh_addr MOD sh_addralign.
- // Normally doing nothing here works great.
- Error (NULL, 0, 3000, "Invalid", "Unsupported section alignment.");
+ } else {
+ Error (NULL, 0, 3000, "Invalid", "Section address not aligned to its
own alignment.");
}
}
@@ -455,12 +444,8 @@ ScanSections32 (
if ((shdr->sh_addr & (shdr->sh_addralign - 1)) == 0) {
// if the section address is aligned we must align PE/COFF
mCoffOffset = (mCoffOffset + shdr->sh_addralign - 1) &
~(shdr->sh_addralign - 1);
- } else if ((shdr->sh_addr % shdr->sh_addralign) != (mCoffOffset %
shdr->sh_addralign)) {
- // ARM RVCT tools have behavior outside of the ELF specification to
try
- // and make images smaller. If sh_addr is not aligned to
sh_addralign
- // then the section needs to preserve sh_addr MOD sh_addralign.
- // Normally doing nothing here works great.
- Error (NULL, 0, 3000, "Invalid", "Unsupported section alignment.");
+ } else {
+ Error (NULL, 0, 3000, "Invalid", "Section address not aligned to its
own alignment.");
}
}
if (shdr->sh_size != 0) {
--
1.9.1
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