[edk2] [PATCH 2/2] IntelSiliconPkg/VtdPeiSample: Add premem support.

[Jiewen Yao]

Before memory is ready, this sample produces one VTd engine.
After memory and silicon is initialized, this sample produces
both IGD VTd engine and all-rest VTd engine by reinstall the
FV_INFO_PPI.

This update is to demonstrate how to support pre-mem VTd usage.

Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao 
---
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c 
  | 234 +---
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
 |   2 +-
 2 files changed, 202 insertions(+), 34 deletions(-)

diff --git 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
index 6267da7..921daef 100644
--- 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
+++ 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define R_SA_MCHBAR   (0x48)
 #define R_SA_GGC  (0x50)
@@ -33,6 +34,8 @@
 #define R_SA_MCHBAR_VTD1_OFFSET  0x5400  ///< HW UNIT for IGD
 #define R_SA_MCHBAR_VTD2_OFFSET  0x5410  ///< HW UNIT for all other - PEG, 
USB, SATA etc
 
+EFI_GUID gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 
0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}};
+
 typedef struct {
   EFI_ACPI_DMAR_HEADER DmarHeader;
   //
@@ -131,50 +134,190 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {
   
 };
 
+typedef struct {
+  EFI_ACPI_DMAR_HEADER DmarHeader;
+  //
+  // VTd engine 2 - all rest
+  //
+  EFI_ACPI_DMAR_DRHD_HEADERDrhd2;
+} MY_VTD_INFO_NO_IGD_PPI;
+
+MY_VTD_INFO_NO_IGD_PPI  mPlatformVTdNoIgdSample = {
+  { // DmarHeader
+{ // Header
+  EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,
+  sizeof(MY_VTD_INFO_PPI),
+  EFI_ACPI_DMAR_REVISION,
+},
+0x26, // HostAddressWidth
+  },
+
+  { // Drhd2
+{ // Header
+  EFI_ACPI_DMAR_TYPE_DRHD,
+  sizeof(EFI_ACPI_DMAR_DRHD_HEADER)
+},
+EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags
+0, // Reserved
+0, // SegmentNumber
+0xFED91000 // RegisterBaseAddress -- TO BE PATCHED
+  },
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDesc = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  ,
+  
+};
+
 /**
   Patch Graphic UMA address in RMRR and base address.
 **/
 VOID
-PatchDmar (
+InitDmar (
   VOID
   )
 {
   UINT32  MchBar;
-  UINT16  IgdMode;
-  UINT16  GttMode;
-  UINT32  IgdMemSize;
-  UINT32  GttMemSize;
-
-  ///
-  /// Calculate IGD memsize
-  ///
-  IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & 
B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;
-  if (IgdMode < 0xF0) {
-IgdMemSize = IgdMode * 32 * (1024) * (1024);
+
+  DEBUG ((DEBUG_INFO, "InitDmar\n"));
+
+  MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;
+  DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar));
+
+  PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED1 | BIT0);
+  DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar));
+
+  DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + 
R_SA_MCHBAR_VTD2_OFFSET) &~1)));
+  MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, 
(UINT32)mPlatformVTdSample.Drhd2.RegisterBaseAddress | 1);
+  DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + 
R_SA_MCHBAR_VTD2_OFFSET) &~1)));
+}
+
+/**
+  Patch Graphic UMA address in RMRR and base address.
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+PatchDmar (
+  VOID
+  )
+{
+  UINT32  MchBar;
+  UINT16  IgdMode;
+  UINT16  GttMode;
+  UINT32  IgdMemSize;
+  UINT32  GttMemSize;
+  MY_VTD_INFO_PPI *PlatformVTdSample;
+  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdInfoSampleDesc;
+  MY_VTD_INFO_NO_IGD_PPI  *PlatformVTdNoIgdSample;
+  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdNoIgdInfoSampleDesc;
+
+  DEBUG ((DEBUG_INFO, "PatchDmar\n"));
+
+  if (PciRead16 (PCI_LIB_ADDRESS(0, 2, 0, 0)) != 0x) {
+PlatformVTdSample = AllocateCopyPool (sizeof(MY_VTD_INFO_PPI), 
);
+ASSERT(PlatformVTdSample != NULL);
+PlatformVTdInfoSampleDesc = AllocateCopyPool 
(sizeof(EFI_PEI_PPI_DESCRIPTOR), );
+ASSERT(PlatformVTdInfoSampleDesc != NULL);
+PlatformVTdInfoSampleDesc->Ppi = PlatformVTdSample;
+
+///
+/// Calculate IGD memsize
+///
+IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & 
B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;
+if (IgdMode < 0xF0) {
+  IgdMemSize = IgdMode * 32 * (1024) * (1024);
+} else {
+  IgdMemSize = 4 * (IgdMode - 0xF0 + 1) * (1024) * (1024);
+}
+
+///
+/// Calculate GTT mem size
+///
+

[edk2] [PATCH 2/2] IntelSiliconPkg/VtdPeiSample: Add premem support.

[Jiewen Yao]

Before memory is ready, this sample produces one VTd engine.
After memory and silicon is initialized, this sample produces
both IGD VTd engine and all-rest VTd engine by reinstall the
FV_INFO_PPI.

This update is to demonstrate how to support pre-mem VTd usage.

Cc: Zeng Star 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao 
---
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c 
  | 234 +---
 
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
 |   2 +-
 2 files changed, 202 insertions(+), 34 deletions(-)

diff --git 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
index 6267da7..921daef 100644
--- 
a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
+++ 
b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define R_SA_MCHBAR   (0x48)
 #define R_SA_GGC  (0x50)
@@ -33,6 +34,8 @@
 #define R_SA_MCHBAR_VTD1_OFFSET  0x5400  ///< HW UNIT for IGD
 #define R_SA_MCHBAR_VTD2_OFFSET  0x5410  ///< HW UNIT for all other - PEG, 
USB, SATA etc
 
+EFI_GUID gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 
0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}};
+
 typedef struct {
   EFI_ACPI_DMAR_HEADER DmarHeader;
   //
@@ -131,50 +134,190 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {
   
 };
 
+typedef struct {
+  EFI_ACPI_DMAR_HEADER DmarHeader;
+  //
+  // VTd engine 2 - all rest
+  //
+  EFI_ACPI_DMAR_DRHD_HEADERDrhd2;
+} MY_VTD_INFO_NO_IGD_PPI;
+
+MY_VTD_INFO_NO_IGD_PPI  mPlatformVTdNoIgdSample = {
+  { // DmarHeader
+{ // Header
+  EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,
+  sizeof(MY_VTD_INFO_PPI),
+  EFI_ACPI_DMAR_REVISION,
+},
+0x26, // HostAddressWidth
+  },
+
+  { // Drhd2
+{ // Header
+  EFI_ACPI_DMAR_TYPE_DRHD,
+  sizeof(EFI_ACPI_DMAR_DRHD_HEADER)
+},
+EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags
+0, // Reserved
+0, // SegmentNumber
+0xFED91000 // RegisterBaseAddress -- TO BE PATCHED
+  },
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDesc = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  ,
+  
+};
+
 /**
   Patch Graphic UMA address in RMRR and base address.
 **/
 VOID
-PatchDmar (
+InitDmar (
   VOID
   )
 {
   UINT32  MchBar;
-  UINT16  IgdMode;
-  UINT16  GttMode;
-  UINT32  IgdMemSize;
-  UINT32  GttMemSize;
-
-  ///
-  /// Calculate IGD memsize
-  ///
-  IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & 
B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;
-  if (IgdMode < 0xF0) {
-IgdMemSize = IgdMode * 32 * (1024) * (1024);
+
+  DEBUG ((DEBUG_INFO, "InitDmar\n"));
+
+  MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;
+  DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar));
+
+  PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED1 | BIT0);
+  DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar));
+
+  DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + 
R_SA_MCHBAR_VTD2_OFFSET) &~1)));
+  MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, 
(UINT32)mPlatformVTdSample.Drhd2.RegisterBaseAddress | 1);
+  DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + 
R_SA_MCHBAR_VTD2_OFFSET) &~1)));
+}
+
+/**
+  Patch Graphic UMA address in RMRR and base address.
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+PatchDmar (
+  VOID
+  )
+{
+  UINT32  MchBar;
+  UINT16  IgdMode;
+  UINT16  GttMode;
+  UINT32  IgdMemSize;
+  UINT32  GttMemSize;
+  MY_VTD_INFO_PPI *PlatformVTdSample;
+  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdInfoSampleDesc;
+  MY_VTD_INFO_NO_IGD_PPI  *PlatformVTdNoIgdSample;
+  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdNoIgdInfoSampleDesc;
+
+  DEBUG ((DEBUG_INFO, "PatchDmar\n"));
+
+  if (PciRead16 (PCI_LIB_ADDRESS(0, 2, 0, 0)) != 0x) {
+PlatformVTdSample = AllocateCopyPool (sizeof(MY_VTD_INFO_PPI), 
);
+ASSERT(PlatformVTdSample != NULL);
+PlatformVTdInfoSampleDesc = AllocateCopyPool 
(sizeof(EFI_PEI_PPI_DESCRIPTOR), );
+ASSERT(PlatformVTdInfoSampleDesc != NULL);
+PlatformVTdInfoSampleDesc->Ppi = PlatformVTdSample;
+
+///
+/// Calculate IGD memsize
+///
+IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & 
B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;
+if (IgdMode < 0xF0) {
+  IgdMemSize = IgdMode * 32 * (1024) * (1024);
+} else {
+  IgdMemSize = 4 * (IgdMode - 0xF0 + 1) * (1024) * (1024);
+}
+
+///
+/// Calculate GTT mem size
+///
+