Re: [edk2] [PATCH edk2-platforms 05/27] Silicon/NXP: Add UART library support for i.MX platforms
Hi Leif,
> -Original Message-
> From: Leif Lindholm
> Sent: Thursday, November 1, 2018 2:00 AM
> To: Chris Co
> Cc: edk2-devel@lists.01.org; Ard Biesheuvel ;
> Michael D Kinney
> Subject: Re: [PATCH edk2-platforms 05/27] Silicon/NXP: Add UART library
> support for i.MX platforms
>
> On Fri, Sep 21, 2018 at 08:25:56AM +, Chris Co wrote:
> > This adds support for interact with the UART controller on NXP i.MX
> > platforms.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Christopher Co
> > Cc: Ard Biesheuvel
> > Cc: Leif Lindholm
> > Cc: Michael D Kinney
> > ---
> > +
> > +**/
> > +RETURN_STATUS
> > +EFIAPI
> > +SerialPortInitialize (
> > + VOID
> > + )
> > +{
> > + MX6UART_REGISTERS *UartBase;
> > + UINT32 Ucr1;
>
> ... once we create variables to hold data from those registers, those
> variables
> should really be FullyCompliantCamelCase.
> But really, something like this could just be "Data" or "Value" or something
> like that. Or if you want a bit more, "ControlRegister".
>
> Not going to comment on each function, but the pattern repeats throughout
> the file.
>
Noted. I'll change variable names throughout all of the files.
Chris
___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
Re: [edk2] [PATCH edk2-platforms 05/27] Silicon/NXP: Add UART library support for i.MX platforms
On Fri, Sep 21, 2018 at 08:25:56AM +, Chris Co wrote:
> This adds support for interact with the UART controller on
> NXP i.MX platforms.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Christopher Co
> Cc: Ard Biesheuvel
> Cc: Leif Lindholm
> Cc: Michael D Kinney
> ---
> Silicon/NXP/iMXPlatformPkg/Include/iMXUart.h |
> 207 +
> Silicon/NXP/iMXPlatformPkg/Library/UartSerialPortLib/UartSerialPortLib.c |
> 243
> Silicon/NXP/iMXPlatformPkg/Library/UartSerialPortLib/UartSerialPortLib.inf |
> 41
> 3 files changed, 491 insertions(+)
>
> diff --git a/Silicon/NXP/iMXPlatformPkg/Include/iMXUart.h
> b/Silicon/NXP/iMXPlatformPkg/Include/iMXUart.h
> new file mode 100644
> index ..ddb61f59c656
> --- /dev/null
> +++ b/Silicon/NXP/iMXPlatformPkg/Include/iMXUart.h
> @@ -0,0 +1,207 @@
> +/** @file
> +*
> +* Copyright (c) 2018 Microsoft Corporation. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD
> License
> +* which accompanies this distribution. The full text of the license may be
> found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +*
> +**/
> +
> +#ifndef _IMXUART_H_
> +#define _IMXUART_H_
> +
> +// UART Receiver Register bit definitions
> +enum MX6UART_RXD {
> + MX6UART_RXD_RX_DATA_MASK = (0xff << 0),
> + MX6UART_RXD_PRERR = (1 << 10),
> + MX6UART_RXD_BRK = (1 << 11),
> + MX6UART_RXD_FRMERR =(1 << 12),
> + MX6UART_RXD_OVRRUN =(1 << 13),
> + MX6UART_RXD_ERR = (1 << 14),
> + MX6UART_RXD_CHARRDY = (1 << 15),
> +};
> +
> +// UART Control Register 1 bit definitions
> +enum MX6UART_UCR1 {
> + MX6UART_UCR1_UARTEN = (1 << 0),
> + MX6UART_UCR1_DOZE = (1 << 1),
> + MX6UART_UCR1_ATDMAEN = (1 << 2),
> + MX6UART_UCR1_TXDMAEN = (1 << 3),
> + MX6UART_UCR1_SNDBRK = (1 << 4),
> + MX6UART_UCR1_RTSDEN = (1 << 5),
> + MX6UART_UCR1_TXMPTYEN = (1 << 6),
> + MX6UART_UCR1_IREN = (1 << 7),
> + MX6UART_UCR1_RXDMAEN = (1 << 8),
> + MX6UART_UCR1_RRDYEN = (1 << 9),
> + MX6UART_UCR1_ICD_MASK = (3 << 10),
> + MX6UART_UCR1_ICD_4 =(0 << 10),
> + MX6UART_UCR1_ICD_8 =(1 << 10),
> + MX6UART_UCR1_ICD_16 = (2 << 10),
> + MX6UART_UCR1_ICD_32 = (3 << 10),
> + MX6UART_UCR1_IDEN = (1 << 12),
> + MX6UART_UCR1_TRDYEN = (1 << 13),
> + MX6UART_UCR1_ADBR = (1 << 14),
> + MX6UART_UCR1_ADEN = (1 << 15),
> +};
> +
> +// UART Control Register 2 bit definitions
> +enum MX6UART_UCR2 {
> + MX6UART_UCR2_SRST = (1 << 0),
> + MX6UART_UCR2_RXEN = (1 << 1),
> + MX6UART_UCR2_TXEN = (1 << 2),
> + MX6UART_UCR2_ATEN = (1 << 3),
> + MX6UART_UCR2_RTSEN =(1 << 4),
> + MX6UART_UCR2_WS = (1 << 5),
> + MX6UART_UCR2_STPB = (1 << 6),
> + MX6UART_UCR2_PROE = (1 << 7),
> + MX6UART_UCR2_PREN = (1 << 8),
> + MX6UART_UCR2_RTEC_MASK =(3 << 9),
> + MX6UART_UCR2_RTEC_RISING = (0 << 9),
> + MX6UART_UCR2_RTEC_FALLING = (1 << 9),
> + MX6UART_UCR2_RTEC_BOTH =(2 << 9),
> + MX6UART_UCR2_ESCEN =(1 << 11),
> + MX6UART_UCR2_CTS = (1 << 12),
> + MX6UART_UCR2_CTSC = (1 << 13),
> + MX6UART_UCR2_IRTS = (1 << 14),
> + MX6UART_UCR2_ESCI = (1 << 15),
> +};
> +
> +// UART Control Register 3 bit definitions
> +enum MX6UART_UCR3 {
> + MX6UART_UCR3_ACIEN =(1 << 0),
> + MX6UART_UCR3_INVT = (1 << 1),
> + MX6UART_UCR3_RXDMUXSEL =(1 << 2),
> + MX6UART_UCR3_DTRDEN = (1 << 3),
> + MX6UART_UCR3_AWAKEN = (1 << 4),
> + MX6UART_UCR3_AIRINTEN = (1 << 5),
> + MX6UART_UCR3_RXDSEN = (1 << 6),
> + MX6UART_UCR3_ADNIMP = (1 << 7),
> + MX6UART_UCR3_RI = (1 << 8),
> + MX6UART_UCR3_DCD = (1 << 9),
> + MX6UART_UCR3_DSR = (1 << 10),
> + MX6UART_UCR3_FRAERREN = (1 << 11),
> + MX6UART_UCR3_PARERREN = (1 << 12),
> + MX6UART_UCR3_DTREN =(1 << 13),
> + MX6UART_UCR3_DPEC_MASK =(3 << 14),
> + MX6UART_UCR3_DPEC_RISING = (0 << 14),
> + MX6UART_UCR3_DPEC_FALLING = (1 << 14),
> + MX6UART_UCR3_DPEC_BOTH =(2 << 14),
> +};
> +
> +// UART Control Register 4 bit definitions
> +enum MX6UART_UCR4 {
> + MX6UART_UCR4_DREN = (1 << 0),
> + MX6UART_UCR4_OREN = (1 << 1),
> + MX6UART_UCR4_BKEN = (1 << 2),
> +
[edk2] [PATCH edk2-platforms 05/27] Silicon/NXP: Add UART library support for i.MX platforms
This adds support for interact with the UART controller on
NXP i.MX platforms.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Christopher Co
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Michael D Kinney
---
Silicon/NXP/iMXPlatformPkg/Include/iMXUart.h |
207 +
Silicon/NXP/iMXPlatformPkg/Library/UartSerialPortLib/UartSerialPortLib.c |
243
Silicon/NXP/iMXPlatformPkg/Library/UartSerialPortLib/UartSerialPortLib.inf |
41
3 files changed, 491 insertions(+)
diff --git a/Silicon/NXP/iMXPlatformPkg/Include/iMXUart.h
b/Silicon/NXP/iMXPlatformPkg/Include/iMXUart.h
new file mode 100644
index ..ddb61f59c656
--- /dev/null
+++ b/Silicon/NXP/iMXPlatformPkg/Include/iMXUart.h
@@ -0,0 +1,207 @@
+/** @file
+*
+* Copyright (c) 2018 Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD
License
+* which accompanies this distribution. The full text of the license may be
found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
IMPLIED.
+*
+**/
+
+#ifndef _IMXUART_H_
+#define _IMXUART_H_
+
+// UART Receiver Register bit definitions
+enum MX6UART_RXD {
+ MX6UART_RXD_RX_DATA_MASK = (0xff << 0),
+ MX6UART_RXD_PRERR = (1 << 10),
+ MX6UART_RXD_BRK = (1 << 11),
+ MX6UART_RXD_FRMERR =(1 << 12),
+ MX6UART_RXD_OVRRUN =(1 << 13),
+ MX6UART_RXD_ERR = (1 << 14),
+ MX6UART_RXD_CHARRDY = (1 << 15),
+};
+
+// UART Control Register 1 bit definitions
+enum MX6UART_UCR1 {
+ MX6UART_UCR1_UARTEN = (1 << 0),
+ MX6UART_UCR1_DOZE = (1 << 1),
+ MX6UART_UCR1_ATDMAEN = (1 << 2),
+ MX6UART_UCR1_TXDMAEN = (1 << 3),
+ MX6UART_UCR1_SNDBRK = (1 << 4),
+ MX6UART_UCR1_RTSDEN = (1 << 5),
+ MX6UART_UCR1_TXMPTYEN = (1 << 6),
+ MX6UART_UCR1_IREN = (1 << 7),
+ MX6UART_UCR1_RXDMAEN = (1 << 8),
+ MX6UART_UCR1_RRDYEN = (1 << 9),
+ MX6UART_UCR1_ICD_MASK = (3 << 10),
+ MX6UART_UCR1_ICD_4 =(0 << 10),
+ MX6UART_UCR1_ICD_8 =(1 << 10),
+ MX6UART_UCR1_ICD_16 = (2 << 10),
+ MX6UART_UCR1_ICD_32 = (3 << 10),
+ MX6UART_UCR1_IDEN = (1 << 12),
+ MX6UART_UCR1_TRDYEN = (1 << 13),
+ MX6UART_UCR1_ADBR = (1 << 14),
+ MX6UART_UCR1_ADEN = (1 << 15),
+};
+
+// UART Control Register 2 bit definitions
+enum MX6UART_UCR2 {
+ MX6UART_UCR2_SRST = (1 << 0),
+ MX6UART_UCR2_RXEN = (1 << 1),
+ MX6UART_UCR2_TXEN = (1 << 2),
+ MX6UART_UCR2_ATEN = (1 << 3),
+ MX6UART_UCR2_RTSEN =(1 << 4),
+ MX6UART_UCR2_WS = (1 << 5),
+ MX6UART_UCR2_STPB = (1 << 6),
+ MX6UART_UCR2_PROE = (1 << 7),
+ MX6UART_UCR2_PREN = (1 << 8),
+ MX6UART_UCR2_RTEC_MASK =(3 << 9),
+ MX6UART_UCR2_RTEC_RISING = (0 << 9),
+ MX6UART_UCR2_RTEC_FALLING = (1 << 9),
+ MX6UART_UCR2_RTEC_BOTH =(2 << 9),
+ MX6UART_UCR2_ESCEN =(1 << 11),
+ MX6UART_UCR2_CTS = (1 << 12),
+ MX6UART_UCR2_CTSC = (1 << 13),
+ MX6UART_UCR2_IRTS = (1 << 14),
+ MX6UART_UCR2_ESCI = (1 << 15),
+};
+
+// UART Control Register 3 bit definitions
+enum MX6UART_UCR3 {
+ MX6UART_UCR3_ACIEN =(1 << 0),
+ MX6UART_UCR3_INVT = (1 << 1),
+ MX6UART_UCR3_RXDMUXSEL =(1 << 2),
+ MX6UART_UCR3_DTRDEN = (1 << 3),
+ MX6UART_UCR3_AWAKEN = (1 << 4),
+ MX6UART_UCR3_AIRINTEN = (1 << 5),
+ MX6UART_UCR3_RXDSEN = (1 << 6),
+ MX6UART_UCR3_ADNIMP = (1 << 7),
+ MX6UART_UCR3_RI = (1 << 8),
+ MX6UART_UCR3_DCD = (1 << 9),
+ MX6UART_UCR3_DSR = (1 << 10),
+ MX6UART_UCR3_FRAERREN = (1 << 11),
+ MX6UART_UCR3_PARERREN = (1 << 12),
+ MX6UART_UCR3_DTREN =(1 << 13),
+ MX6UART_UCR3_DPEC_MASK =(3 << 14),
+ MX6UART_UCR3_DPEC_RISING = (0 << 14),
+ MX6UART_UCR3_DPEC_FALLING = (1 << 14),
+ MX6UART_UCR3_DPEC_BOTH =(2 << 14),
+};
+
+// UART Control Register 4 bit definitions
+enum MX6UART_UCR4 {
+ MX6UART_UCR4_DREN = (1 << 0),
+ MX6UART_UCR4_OREN = (1 << 1),
+ MX6UART_UCR4_BKEN = (1 << 2),
+ MX6UART_UCR4_TCEN = (1 << 3),
+ MX6UART_UCR4_LPBYP =(1 << 4),
+ MX6UART_UCR4_IRSC = (1 << 5),
+ MX6UART_UCR4_IDDMAEN = (1 << 6),
+ MX6UART_UCR4_WKEN = (1 << 7),
+ MX6UART_UCR4_ENIRI =(1 << 8),
+ MX6UART_UCR4_INVR = (1 << 9),
+
