Re: [edk2] [PATCH edk2-platforms 19/27] Silicon/NXP: Add i.MX6 ACPI tables
On Tue, 8 Jan 2019 at 22:43, Chris Co wrote:
>
> Hi Ard,
>
> > -Original Message-
> > From: Ard Biesheuvel
> > Sent: Monday, December 17, 2018 3:14 AM
> > To: Chris Co
> > Cc: edk2-devel@lists.01.org; Leif Lindholm ;
> > Michael
> > D Kinney
> > Subject: Re: [PATCH edk2-platforms 19/27] Silicon/NXP: Add i.MX6 ACPI tables
> >
> > On Fri, 21 Sep 2018 at 10:26, Chris Co
> > wrote:
> > >
> > > +// PL310 L2 Cache Controller Resource Group
> > > +#define CSRT_PL310_MINIMUM_VERSION 1
> > > +#define CSRT_PL310_VERSION_2 2
> > > +#define CSRT_PL310_RAW_PROTOCOL 0
> > > +#define CSRT_PL310_SMC_PROTOCOL 1
> > > +
> > > +// We use PSCI_CPU_ON to turn on the L2 cache, with special value
> > > +// 0x0010 for the Core ID. PSCI sees this core ID and knows
> > > +// this is an L2 cache operation, then looks at R2 for the
> > > +// operation to perform.
> > > +#define PSCI_FID_CPU_ON0x8403
> > > +#define L2CACHE_SMC_R1 0x0010
> > > +#define L2CACHE_OP_ENABLE 1
> > > +#define L2CACHE_OP_DISABLE 2
> > > +#define L2CACHE_OP_ENABLE_WRITEBACK3
> > > +#define L2CACHE_OP_DISABLE_WRITEBACK 4
> > > +#define L2CACHE_OP_ENABLE_WFLZ 5
> > > +
> >
> > Who defined this protocol? Where is the opposite side implemented?
> >
> > Overloading architected PSCI calls to manage platform specific pieces
> > is really a no-go.
> >
>
> Since my initial patch set submission, we have updated this code to use the
> standardized protocol instead of overloading PSCI_CPU_ON. It will be in the
> V2 patch set.
>
> // PL310 L2 Cache Controller Resource Group
> #define CSRT_PL310_MINIMUM_VERSION 1
> #define CSRT_PL310_VERSION_2 2
> #define CSRT_PL310_RAW_PROTOCOL 0
> #define CSRT_PL310_SMC_PROTOCOL 1
>
> #define SMC_CALL_VAL(owner, funcid) \
> (0x8000 | (((owner) & 0x3F) << 24) | ((funcid) & 0x))
>
> #define SMC_OWNER_SIP 2
> #define IMX_SMC_PL310_ENABLESMC_CALL_VAL(SMC_OWNER_SIP, 1)
> #define IMX_SMC_PL310_DISABLE SMC_CALL_VAL(SMC_OWNER_SIP, 2)
> #define IMX_SMC_PL310_ENABLE_WRITEBACK SMC_CALL_VAL(SMC_OWNER_SIP, 3)
> #define IMX_SMC_PL310_DISABLE_WRITEBACK SMC_CALL_VAL(SMC_OWNER_SIP, 4)
> #define IMX_SMC_PL310_ENABLE_WFLZ SMC_CALL_VAL(SMC_OWNER_SIP, 5)
>
Excellent!
> > > +// Debug Port 2 table
> > > +EFI_ACPI_5_0_DEBUG_PORT_2_TABLE Dbg2 = {
> >
> > STATIC
> >
> > > + {
> > > +// Header
> > > +{
> > > + EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE, // Signature
> > "DBG2"
> > > + sizeof (EFI_ACPI_5_0_DEBUG_PORT_2_TABLE), // Length
> > > + EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION, // Revision
> > > + EFI_ACPI_5_0_UNDEFINED,// Checksum -
> > > updated at
> > runtime
> > > + EFI_ACPI_OEM_ID, // OEM ID[6]
> > > + EFI_ACPI_OEM_TABLE_ID, // OEM Table ID
> > > + EFI_ACPI_OEM_REVISION, // OEM Revision
> > > + EFI_ACPI_CREATOR_ID, // Creator ID
> > > + EFI_ACPI_CREATOR_REVISION // Creator Revision
> > > +},
> > > +sizeof (EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_HEADER), //
> > OffsetDbgDeviceinfo
> > > +1, //
> > > NumberDbgDeviceInfo
> > > + },
> > > + {
> > > +// Uart
> > > +{
> > > + // DeviceInfo
> > > + EFI_ACPI_RESERVED_BYTE, // Revision
> > > + sizeof (DEBUG_DEVICE_INFO_UART),// Length
> > > + 1, //
> > > NumberofGenericAddressRegisters
> > > + UART_NAME_SPACE_STRING_LENGTH, //
> > NameSpaceStringLength
> > > + OFFSET_OF (DEBUG_DEVICE_INFO_UART, NameSpaceString),//
> > NameSpaceStringOffset
> > > + 0, //
> > > OemDataLength
> > > + EFI_ACPI_RESERVED_WORD, //
> > > OemDataOffset
> > > + DBG2_TYPE_SERIAL, // PortType
> > > + DBG_PORT_SUBTYPE_IMX6, //
> > > PortSubtype 000Ch
> >
> > Is this subtype defined in a published version of the SPCR/DBG2 specs?
> >
>
> Just checked and the IMX6 subtype is not present in the latest DBG2 spec.
> I'll work on getting it added. Does the subtype need to be in the published
> DBG2 spec before the patch can be accepted upstream?
>
Preferably, yes.
> Note: The definition is present in our WDK headers but I'm guessing that is
> not sufficient...
>
> //
> // ACPI debug device port types. The bottom 15 bits of these values should
> // match the BCDE_DEBUGGER_TYPE values that are defined in the header
> // minkernel\published\base\bcdtypes.w
> //
>
> #define
Re: [edk2] [PATCH edk2-platforms 19/27] Silicon/NXP: Add i.MX6 ACPI tables
Hi Ard,
> -Original Message-
> From: Ard Biesheuvel
> Sent: Monday, December 17, 2018 3:14 AM
> To: Chris Co
> Cc: edk2-devel@lists.01.org; Leif Lindholm ; Michael
> D Kinney
> Subject: Re: [PATCH edk2-platforms 19/27] Silicon/NXP: Add i.MX6 ACPI tables
>
> On Fri, 21 Sep 2018 at 10:26, Chris Co
> wrote:
> >
> > +// PL310 L2 Cache Controller Resource Group
> > +#define CSRT_PL310_MINIMUM_VERSION 1
> > +#define CSRT_PL310_VERSION_2 2
> > +#define CSRT_PL310_RAW_PROTOCOL 0
> > +#define CSRT_PL310_SMC_PROTOCOL 1
> > +
> > +// We use PSCI_CPU_ON to turn on the L2 cache, with special value
> > +// 0x0010 for the Core ID. PSCI sees this core ID and knows
> > +// this is an L2 cache operation, then looks at R2 for the
> > +// operation to perform.
> > +#define PSCI_FID_CPU_ON0x8403
> > +#define L2CACHE_SMC_R1 0x0010
> > +#define L2CACHE_OP_ENABLE 1
> > +#define L2CACHE_OP_DISABLE 2
> > +#define L2CACHE_OP_ENABLE_WRITEBACK3
> > +#define L2CACHE_OP_DISABLE_WRITEBACK 4
> > +#define L2CACHE_OP_ENABLE_WFLZ 5
> > +
>
> Who defined this protocol? Where is the opposite side implemented?
>
> Overloading architected PSCI calls to manage platform specific pieces
> is really a no-go.
>
Since my initial patch set submission, we have updated this code to use the
standardized protocol instead of overloading PSCI_CPU_ON. It will be in the V2
patch set.
// PL310 L2 Cache Controller Resource Group
#define CSRT_PL310_MINIMUM_VERSION 1
#define CSRT_PL310_VERSION_2 2
#define CSRT_PL310_RAW_PROTOCOL 0
#define CSRT_PL310_SMC_PROTOCOL 1
#define SMC_CALL_VAL(owner, funcid) \
(0x8000 | (((owner) & 0x3F) << 24) | ((funcid) & 0x))
#define SMC_OWNER_SIP 2
#define IMX_SMC_PL310_ENABLESMC_CALL_VAL(SMC_OWNER_SIP, 1)
#define IMX_SMC_PL310_DISABLE SMC_CALL_VAL(SMC_OWNER_SIP, 2)
#define IMX_SMC_PL310_ENABLE_WRITEBACK SMC_CALL_VAL(SMC_OWNER_SIP, 3)
#define IMX_SMC_PL310_DISABLE_WRITEBACK SMC_CALL_VAL(SMC_OWNER_SIP, 4)
#define IMX_SMC_PL310_ENABLE_WFLZ SMC_CALL_VAL(SMC_OWNER_SIP, 5)
> > +// Debug Port 2 table
> > +EFI_ACPI_5_0_DEBUG_PORT_2_TABLE Dbg2 = {
>
> STATIC
>
> > + {
> > +// Header
> > +{
> > + EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE, // Signature
> "DBG2"
> > + sizeof (EFI_ACPI_5_0_DEBUG_PORT_2_TABLE), // Length
> > + EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION, // Revision
> > + EFI_ACPI_5_0_UNDEFINED,// Checksum - updated
> > at
> runtime
> > + EFI_ACPI_OEM_ID, // OEM ID[6]
> > + EFI_ACPI_OEM_TABLE_ID, // OEM Table ID
> > + EFI_ACPI_OEM_REVISION, // OEM Revision
> > + EFI_ACPI_CREATOR_ID, // Creator ID
> > + EFI_ACPI_CREATOR_REVISION // Creator Revision
> > +},
> > +sizeof (EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_HEADER), //
> OffsetDbgDeviceinfo
> > +1, // NumberDbgDeviceInfo
> > + },
> > + {
> > +// Uart
> > +{
> > + // DeviceInfo
> > + EFI_ACPI_RESERVED_BYTE, // Revision
> > + sizeof (DEBUG_DEVICE_INFO_UART),// Length
> > + 1, //
> > NumberofGenericAddressRegisters
> > + UART_NAME_SPACE_STRING_LENGTH, //
> NameSpaceStringLength
> > + OFFSET_OF (DEBUG_DEVICE_INFO_UART, NameSpaceString),//
> NameSpaceStringOffset
> > + 0, //
> > OemDataLength
> > + EFI_ACPI_RESERVED_WORD, //
> > OemDataOffset
> > + DBG2_TYPE_SERIAL, // PortType
> > + DBG_PORT_SUBTYPE_IMX6, //
> > PortSubtype 000Ch
>
> Is this subtype defined in a published version of the SPCR/DBG2 specs?
>
Just checked and the IMX6 subtype is not present in the latest DBG2 spec. I'll
work on getting it added. Does the subtype need to be in the published DBG2
spec before the patch can be accepted upstream?
Note: The definition is present in our WDK headers but I'm guessing that is not
sufficient...
//
// ACPI debug device port types. The bottom 15 bits of these values should
// match the BCDE_DEBUGGER_TYPE values that are defined in the header
// minkernel\published\base\bcdtypes.w
//
#define DEBUG_DEVICE_PORT_SERIAL 0x8000
#define DEBUG_DEVICE_PORT_1394 0x8001
#define DEBUG_DEVICE_PORT_USB 0x8002
#define DEBUG_DEVICE_PORT_NET 0x8003
#define DEBUG_DEVICE_PORT_LOCAL 0x8004
#define DEBUG_DEVICE_SERIAL_LEGACY_16550 0x0
#define DEBUG_DEVICE_SERIAL_GEN_16550 0x1
#define DEBUG_DEVICE_SERIAL_SPI_MAX311XE 0x2
Re: [edk2] [PATCH edk2-platforms 19/27] Silicon/NXP: Add i.MX6 ACPI tables
On Fri, 21 Sep 2018 at 10:26, Chris Co wrote:
>
> This adds baseline ACPI table support for booting Windows on
> NXP i.MX6 SoCs. Platforms may override these tables as necessary.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Christopher Co
> Cc: Ard Biesheuvel
> Cc: Leif Lindholm
> Cc: Michael D Kinney
> ---
> Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc | 408
> Silicon/NXP/iMX6Pkg/AcpiTables/Dbg2.aslc | 142 +++
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Common.h | 106 +
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Enet.asl | 106 +
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Gfx.asl | 74
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Gpio.asl | 55 +++
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-I2c.asl | 67
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-PCIe.asl | 298 ++
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Platform.asl | 106 +
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Pwm.asl | 85
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Sdhc.asl | 133 +++
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Spi.asl | 103 +
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-TrEE.asl | 33 ++
> Silicon/NXP/iMX6Pkg/AcpiTables/Fadt.aslc | 60 +++
> Silicon/NXP/iMX6Pkg/AcpiTables/Madt.aslc | 120 ++
> Silicon/NXP/iMX6Pkg/AcpiTables/Mcfg.aslc | 92 +
> Silicon/NXP/iMX6Pkg/AcpiTables/Spcr.aslc | 95 +
> Silicon/NXP/iMX6Pkg/AcpiTables/Tpm2.aslc | 53 +++
> 18 files changed, 2136 insertions(+)
>
> diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc
> b/Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc
> new file mode 100644
> index ..82c2420a2b7e
> --- /dev/null
> +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc
> @@ -0,0 +1,408 @@
> +/** @file
> +*
> +* Copyright (c) 2018 Microsoft Corporation. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD
> License
> +* which accompanies this distribution. The full text of the license may be
> found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +*
> +**/
> +
> +#include "../Include/Platform.h"
> +#include "../Include/iMX6.h"
> +
Please don't use relative includes. Instead, make sure all packages
you depend on are included in the .inf, and make sure the .dec files
of those packages accurately describe the paths of all include files
they expose.
> +#pragma pack(push, iMX6Csrt, 1)
> +
> +// Timer Resource Group
> +// Each timer consumes 4K of address space.
> +#define TIMER_ADDRES_SIZE 0x1000
> +#define TIMER_CAP_ALWAYS_ON 0x0001 // Timer is always ON.
> +#define TIMER_CAP_UP_COUNTER0x0002 // Up counter vs. down counter (0)
> +#define TIMER_CAP_READABLE 0x0004 // Counter has a software
> interface.
> +#define TIMER_CAP_PERIODIC 0x0008 // Can generate periodic
> interrupts.
> +#define TIMER_CAP_DRIVES_IRQ0x0010 // Timer interrupt drives a
> physical IRQ.
> +#define TIMER_CAP_ONE_SHOT 0x0020 // Counter can generate one-shot
> interrupts
> +
> +// Timer source clock codes
> +typedef enum {
> + GPT_CLOCK_NONE= 0,
> + GPT_CLOCK_PERIPHERAL = 1,
> + GPT_CLOCK_HI_FREQ = 2,
> + GPT_CLOCK_EXT = 3,
> + GPT_CLOCK_LOW_FREQ= 4,
> +#if defined(CPU_IMX6DQ) || defined (CPU_IMX6DQP)
> + GPT_CLOCK_OSC_DIV_8 = 5,
> + GPT_CLOCK_OSC = 7,
> +#elif (defined(CPU_IMX6SDL) || defined(CPU_IMX6SX))
> + GPT_CLOCK_OSC = 5,
> +#else
> +#error iMX6 CPU Type Not Defined (Preprocessor Flag)
> +#endif
> +} GPT_SOURCE_CLOCK;
> +
> +// EPIT timer source clock codes
> +typedef enum {
> + EPIT_CLOCK_NONE= 0,
> + EPIT_CLOCK_PERIPHERAL = 1,
> + EPIT_CLOCK_HI_FREQ = 2,
> + EPIT_CLOCK_LOW_FREQ= 3,
> +} EPIT_SOURCE_CLOCK;
> +
> +// Timer descriptor
> +typedef struct {
> + EFI_ACPI_5_0_CSRT_RESOURCE_DESCRIPTOR_HEADER Header;
> + UINT32 Capabilities;
> + UINT32 Width;
> + UINT32 Source;
> + UINT32 Frequency;
> + UINT32 FrequencyScale;
> + UINT32 BaseAddress;
> + UINT32 Size;
> + UINT32 Interrupt;
> + UINT32 ChipType;
> +} RD_TIMER;
> +
> +// Resource Group Shared Info
> +typedef struct {
> + UINT16 RevMajor;
> + UINT16 RevMinor;
> + UINT32 ChipType;
> +} RG_PLATFORM_INFORMATION;
> +
> +// Timer group descriptor
> +typedef struct {
> + EFI_ACPI_5_0_CSRT_RESOURCE_GROUP_HEADER Header;
> + RG_PLATFORM_INFORMATION PlatformInfo;
> +#if defined(CPU_IMX6SDL)
> + RD_TIMER Timers[3];
> +#else
> + RD_TIMER Timers[4];
> +#endif
> +} RG_TIMER;
> +
> +// PL310 L2 Cache Controller Resource Group
> +#define CSRT_PL310_MINIMUM_VERSION 1
> +#define CSRT_PL310_VERSION_2 2
> +#define CSRT_PL310_RAW_PROTOCOL 0
> +#define CSRT_PL310_SMC_PROTOCOL 1
Re: [edk2] [PATCH edk2-platforms 19/27] Silicon/NXP: Add i.MX6 ACPI tables
On Fri, Sep 21, 2018 at 08:26:12AM +, Chris Co wrote:
> This adds baseline ACPI table support for booting Windows on
> NXP i.MX6 SoCs. Platforms may override these tables as necessary.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Christopher Co
> Cc: Ard Biesheuvel
> Cc: Leif Lindholm
> Cc: Michael D Kinney
> ---
> Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc | 408
> Silicon/NXP/iMX6Pkg/AcpiTables/Dbg2.aslc | 142 +++
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Common.h | 106 +
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Enet.asl | 106 +
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Gfx.asl | 74
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Gpio.asl | 55 +++
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-I2c.asl | 67
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-PCIe.asl | 298 ++
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Platform.asl | 106 +
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Pwm.asl | 85
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Sdhc.asl | 133 +++
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Spi.asl | 103 +
> Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-TrEE.asl | 33 ++
> Silicon/NXP/iMX6Pkg/AcpiTables/Fadt.aslc | 60 +++
> Silicon/NXP/iMX6Pkg/AcpiTables/Madt.aslc | 120 ++
> Silicon/NXP/iMX6Pkg/AcpiTables/Mcfg.aslc | 92 +
> Silicon/NXP/iMX6Pkg/AcpiTables/Spcr.aslc | 95 +
> Silicon/NXP/iMX6Pkg/AcpiTables/Tpm2.aslc | 53 +++
> 18 files changed, 2136 insertions(+)
Shouldn't there be a .inf in this patch as well?
Oh, no, this is used as an include directory, and ... hmm.
This gets a bit grotty later.
Ard, could you suggest a better way of laying this out?
>
> diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc
> b/Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc
> new file mode 100644
> index ..82c2420a2b7e
> --- /dev/null
> +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc
> @@ -0,0 +1,408 @@
> +/** @file
> +*
> +* Copyright (c) 2018 Microsoft Corporation. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD
> License
> +* which accompanies this distribution. The full text of the license may be
> found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +*
> +**/
> +
> +#include "../Include/Platform.h"
> +#include "../Include/iMX6.h"
#include
#include
should just work here, since any user must declare use of
Silicon/NXP/iMX6Pkg/iMX6Pkg.dec anyway, and that puts the package
Include in the include path.
> +
> +#pragma pack(push, iMX6Csrt, 1)
> +
> +// Timer Resource Group
> +// Each timer consumes 4K of address space.
> +#define TIMER_ADDRES_SIZE 0x1000
> +#define TIMER_CAP_ALWAYS_ON 0x0001 // Timer is always ON.
> +#define TIMER_CAP_UP_COUNTER0x0002 // Up counter vs. down counter (0)
> +#define TIMER_CAP_READABLE 0x0004 // Counter has a software
> interface.
> +#define TIMER_CAP_PERIODIC 0x0008 // Can generate periodic
> interrupts.
> +#define TIMER_CAP_DRIVES_IRQ0x0010 // Timer interrupt drives a
> physical IRQ.
> +#define TIMER_CAP_ONE_SHOT 0x0020 // Counter can generate one-shot
> interrupts
> +
> +// Timer source clock codes
> +typedef enum {
> + GPT_CLOCK_NONE= 0,
> + GPT_CLOCK_PERIPHERAL = 1,
> + GPT_CLOCK_HI_FREQ = 2,
> + GPT_CLOCK_EXT = 3,
> + GPT_CLOCK_LOW_FREQ= 4,
> +#if defined(CPU_IMX6DQ) || defined (CPU_IMX6DQP)
> + GPT_CLOCK_OSC_DIV_8 = 5,
> + GPT_CLOCK_OSC = 7,
> +#elif (defined(CPU_IMX6SDL) || defined(CPU_IMX6SX))
> + GPT_CLOCK_OSC = 5,
> +#else
> +#error iMX6 CPU Type Not Defined (Preprocessor Flag)
> +#endif
> +} GPT_SOURCE_CLOCK;
> +
> +// EPIT timer source clock codes
> +typedef enum {
> + EPIT_CLOCK_NONE= 0,
> + EPIT_CLOCK_PERIPHERAL = 1,
> + EPIT_CLOCK_HI_FREQ = 2,
> + EPIT_CLOCK_LOW_FREQ= 3,
> +} EPIT_SOURCE_CLOCK;
> +
> +// Timer descriptor
> +typedef struct {
> + EFI_ACPI_5_0_CSRT_RESOURCE_DESCRIPTOR_HEADER Header;
> + UINT32 Capabilities;
> + UINT32 Width;
> + UINT32 Source;
> + UINT32 Frequency;
> + UINT32 FrequencyScale;
> + UINT32 BaseAddress;
> + UINT32 Size;
> + UINT32 Interrupt;
> + UINT32 ChipType;
> +} RD_TIMER;
> +
> +// Resource Group Shared Info
> +typedef struct {
> + UINT16 RevMajor;
> + UINT16 RevMinor;
> + UINT32 ChipType;
> +} RG_PLATFORM_INFORMATION;
> +
> +// Timer group descriptor
> +typedef struct {
> + EFI_ACPI_5_0_CSRT_RESOURCE_GROUP_HEADER Header;
> + RG_PLATFORM_INFORMATION PlatformInfo;
> +#if defined(CPU_IMX6SDL)
> + RD_TIMER Timers[3];
> +#else
> + RD_TIMER Timers[4];
> +#endif
> +} RG_TIMER;
> +
> +// PL310 L2 Cache Controller Resource Group
>
[edk2] [PATCH edk2-platforms 19/27] Silicon/NXP: Add i.MX6 ACPI tables
This adds baseline ACPI table support for booting Windows on
NXP i.MX6 SoCs. Platforms may override these tables as necessary.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Christopher Co
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Michael D Kinney
---
Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc | 408
Silicon/NXP/iMX6Pkg/AcpiTables/Dbg2.aslc | 142 +++
Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Common.h | 106 +
Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Enet.asl | 106 +
Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Gfx.asl | 74
Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Gpio.asl | 55 +++
Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-I2c.asl | 67
Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-PCIe.asl | 298 ++
Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Platform.asl | 106 +
Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Pwm.asl | 85
Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Sdhc.asl | 133 +++
Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Spi.asl | 103 +
Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-TrEE.asl | 33 ++
Silicon/NXP/iMX6Pkg/AcpiTables/Fadt.aslc | 60 +++
Silicon/NXP/iMX6Pkg/AcpiTables/Madt.aslc | 120 ++
Silicon/NXP/iMX6Pkg/AcpiTables/Mcfg.aslc | 92 +
Silicon/NXP/iMX6Pkg/AcpiTables/Spcr.aslc | 95 +
Silicon/NXP/iMX6Pkg/AcpiTables/Tpm2.aslc | 53 +++
18 files changed, 2136 insertions(+)
diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc
b/Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc
new file mode 100644
index ..82c2420a2b7e
--- /dev/null
+++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc
@@ -0,0 +1,408 @@
+/** @file
+*
+* Copyright (c) 2018 Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD
License
+* which accompanies this distribution. The full text of the license may be
found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
IMPLIED.
+*
+**/
+
+#include "../Include/Platform.h"
+#include "../Include/iMX6.h"
+
+#pragma pack(push, iMX6Csrt, 1)
+
+// Timer Resource Group
+// Each timer consumes 4K of address space.
+#define TIMER_ADDRES_SIZE 0x1000
+#define TIMER_CAP_ALWAYS_ON 0x0001 // Timer is always ON.
+#define TIMER_CAP_UP_COUNTER0x0002 // Up counter vs. down counter (0)
+#define TIMER_CAP_READABLE 0x0004 // Counter has a software interface.
+#define TIMER_CAP_PERIODIC 0x0008 // Can generate periodic interrupts.
+#define TIMER_CAP_DRIVES_IRQ0x0010 // Timer interrupt drives a
physical IRQ.
+#define TIMER_CAP_ONE_SHOT 0x0020 // Counter can generate one-shot
interrupts
+
+// Timer source clock codes
+typedef enum {
+ GPT_CLOCK_NONE= 0,
+ GPT_CLOCK_PERIPHERAL = 1,
+ GPT_CLOCK_HI_FREQ = 2,
+ GPT_CLOCK_EXT = 3,
+ GPT_CLOCK_LOW_FREQ= 4,
+#if defined(CPU_IMX6DQ) || defined (CPU_IMX6DQP)
+ GPT_CLOCK_OSC_DIV_8 = 5,
+ GPT_CLOCK_OSC = 7,
+#elif (defined(CPU_IMX6SDL) || defined(CPU_IMX6SX))
+ GPT_CLOCK_OSC = 5,
+#else
+#error iMX6 CPU Type Not Defined (Preprocessor Flag)
+#endif
+} GPT_SOURCE_CLOCK;
+
+// EPIT timer source clock codes
+typedef enum {
+ EPIT_CLOCK_NONE= 0,
+ EPIT_CLOCK_PERIPHERAL = 1,
+ EPIT_CLOCK_HI_FREQ = 2,
+ EPIT_CLOCK_LOW_FREQ= 3,
+} EPIT_SOURCE_CLOCK;
+
+// Timer descriptor
+typedef struct {
+ EFI_ACPI_5_0_CSRT_RESOURCE_DESCRIPTOR_HEADER Header;
+ UINT32 Capabilities;
+ UINT32 Width;
+ UINT32 Source;
+ UINT32 Frequency;
+ UINT32 FrequencyScale;
+ UINT32 BaseAddress;
+ UINT32 Size;
+ UINT32 Interrupt;
+ UINT32 ChipType;
+} RD_TIMER;
+
+// Resource Group Shared Info
+typedef struct {
+ UINT16 RevMajor;
+ UINT16 RevMinor;
+ UINT32 ChipType;
+} RG_PLATFORM_INFORMATION;
+
+// Timer group descriptor
+typedef struct {
+ EFI_ACPI_5_0_CSRT_RESOURCE_GROUP_HEADER Header;
+ RG_PLATFORM_INFORMATION PlatformInfo;
+#if defined(CPU_IMX6SDL)
+ RD_TIMER Timers[3];
+#else
+ RD_TIMER Timers[4];
+#endif
+} RG_TIMER;
+
+// PL310 L2 Cache Controller Resource Group
+#define CSRT_PL310_MINIMUM_VERSION 1
+#define CSRT_PL310_VERSION_2 2
+#define CSRT_PL310_RAW_PROTOCOL 0
+#define CSRT_PL310_SMC_PROTOCOL 1
+
+// We use PSCI_CPU_ON to turn on the L2 cache, with special value
+// 0x0010 for the Core ID. PSCI sees this core ID and knows
+// this is an L2 cache operation, then looks at R2 for the
+// operation to perform.
+#define PSCI_FID_CPU_ON0x8403
+#define L2CACHE_SMC_R1 0x0010
+#define L2CACHE_OP_ENABLE 1
+#define L2CACHE_OP_DISABLE 2
+#define L2CACHE_OP_ENABLE_WRITEBACK3
+#define L2CACHE_OP_DISABLE_WRITEBACK 4
