Re: [edk2] [PATCH v3 1/1] ArmPkg/TimerDxe: Add ISB for timer compare value reload

On 15 March 2018 at 07:17, Heyi Guo wrote: > If timer interrupt is level sensitive, reloading timer compare > register has a side effect of clearing GIC pending status, so a "ISB" > is needed to make sure this instruction is executed before enabling > CPU IRQ, or else we may get spurious timer int

[edk2] [PATCH v3 1/1] ArmPkg/TimerDxe: Add ISB for timer compare value reload

If timer interrupt is level sensitive, reloading timer compare register has a side effect of clearing GIC pending status, so a "ISB" is needed to make sure this instruction is executed before enabling CPU IRQ, or else we may get spurious timer interrupts. Contributed-under: TianoCore Contribution