Idtr might be changed inside of FSP. 32bit FSP only knows the <4G address.
If IDTR.Base is >4G, FSP can not handle. So we need save/restore IDTR here.
Interrupt is already disabled here, so it is safety to update IDTR.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen....@intel.com>
Cc: "Ma, Maurice" <maurice...@intel.com>
Cc: "Rangarajan, Ravi P" <ravi.p.rangara...@intel.com>
Cc: "Mudusuru, Giri P" <giri.p.mudus...@intel.com>
Cc: "Chan, Amy" <amy.c...@intel.com>
---
.../Library/BaseFspApiLib/X64/DispatchExecute.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/IntelFspWrapperPkg/Library/BaseFspApiLib/X64/DispatchExecute.c
b/IntelFspWrapperPkg/Library/BaseFspApiLib/X64/DispatchExecute.c
index e2f4422..360327e 100644
--- a/IntelFspWrapperPkg/Library/BaseFspApiLib/X64/DispatchExecute.c
+++ b/IntelFspWrapperPkg/Library/BaseFspApiLib/X64/DispatchExecute.c
@@ -89,6 +89,18 @@ Execute32BitCode (
IN UINT64 Param1
)
{
- return AsmExecute32BitCode (Function, Param1, 0, &mGdt);
+ EFI_STATUS Status;
+ IA32_DESCRIPTOR Idtr;
+
+ //
+ // Idtr might be changed inside of FSP. 32bit FSP only knows the <4G address.
+ // If IDTR.Base is >4G, FSP can not handle. So we need save/restore IDTR
here for X64 only.
+ // Interrupt is already disabled here, so it is safety to update IDTR.
+ //
+ AsmReadIdtr (&Idtr);
+ Status = AsmExecute32BitCode (Function, Param1, 0, &mGdt);
+ AsmWriteIdtr (&Idtr);
+
+ return Status;
}
--
1.9.5.msysgit.0
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