Rename the variable to "gPatchSmiCr3" so that its association with PatchInstructionX86() is clear from the declaration, change its type to UINT8, and patch it with PatchInstructionX86(). This lets us remove the binary (DB) encoding of some instructions in "SmiEntry.nasm".
Cc: Eric Dong <eric.d...@intel.com> Cc: Jiewen Yao <jiewen....@intel.com> Cc: Liming Gao <liming....@intel.com> Cc: Michael D Kinney <michael.d.kin...@intel.com> Cc: Ruiyu Ni <ruiyu...@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <ler...@redhat.com> --- UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 4 ++-- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 6 +++--- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c index 73253016060d..c61963403477 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c @@ -107,7 +107,7 @@ typedef struct { /// extern UINT8 gPatchSmbase; extern UINT8 gPatchSmiStack; -extern UINT32 gSmiCr3; +extern UINT8 gPatchSmiCr3; extern volatile UINT8 gcSmiHandlerTemplate[]; extern CONST UINT16 gcSmiHandlerSize; @@ -719,7 +719,7 @@ InstallSmiHandler ( // CpuSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN)); PatchInstructionX86 (&gPatchSmiStack, CpuSmiStack, 4); - gSmiCr3 = Cr3; + PatchInstructionX86 (&gPatchSmiCr3, Cr3, 4); PatchInstructionX86 (&gPatchSmbase, SmBase, 4); gSmiHandlerIdtr.Base = IdtBase; gSmiHandlerIdtr.Limit = (UINT16)(IdtSize - 1); diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm index 0ea3c1e4498d..0023cb328d6a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -44,7 +44,7 @@ extern ASM_PFX(CpuSmmDebugExit) global ASM_PFX(gcSmiHandlerTemplate) global ASM_PFX(gcSmiHandlerSize) -global ASM_PFX(gSmiCr3) +global ASM_PFX(gPatchSmiCr3) global ASM_PFX(gPatchSmiStack) global ASM_PFX(gPatchSmbase) global ASM_PFX(mXdSupported) @@ -93,8 +93,8 @@ ASM_PFX(gPatchSmiStack): jmp ProtFlatMode ProtFlatMode: - DB 0xb8 ; mov eax, imm32 -ASM_PFX(gSmiCr3): DD 0 + mov eax, strict dword 0 ; source operand will be patched +ASM_PFX(gPatchSmiCr3): mov cr3, eax ; ; Need to test for CR4 specific bit support diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm index 9cfa8e7fc8f4..9971ae6f064a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -56,7 +56,7 @@ extern ASM_PFX(CpuSmmDebugExit) global ASM_PFX(gPatchSmbase) global ASM_PFX(mXdSupported) global ASM_PFX(gPatchSmiStack) -global ASM_PFX(gSmiCr3) +global ASM_PFX(gPatchSmiCr3) global ASM_PFX(gcSmiHandlerTemplate) global ASM_PFX(gcSmiHandlerSize) @@ -102,8 +102,8 @@ ASM_PFX(gPatchSmiStack): BITS 64 ProtFlatMode: - DB 0xb8 ; mov eax, offset gSmiCr3 -ASM_PFX(gSmiCr3): DD 0 + mov eax, strict dword 0 ; source operand will be patched +ASM_PFX(gPatchSmiCr3): mov cr3, rax mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3 mov cr4, rax ; in PreModifyMtrrs() to flush TLB. -- 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
