Re: [edk2] [PATCH edk2-platforms v3 02/15] Hisilicon/D05: Add PPTT support
On Fri, Feb 02, 2018 at 08:05:30PM +0800, Heyi Guo wrote:
> Add Processor Properties Topology Table, PPTT include
> Processor hierarchy node, Cache Type Structure and ID structure.
>
> PPTT is needed for lscpu command to show socket information correctly.
> https://bugs.linaro.org/show_bug.cgi?id=3206
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang
> Signed-off-by: Heyi Guo
> Reviewed-by: Ard Biesheuvel
> Reviewed-by: Graeme Gregory
> Reveiwed-by: Jeremy Linton
So long as this is updated to work with whatever version of the patch
that goes into edk2:
Reviewed-by: Leif Lindholm
> ---
> Platform/Hisilicon/D05/D05.dsc | 1 +
> Platform/Hisilicon/D05/D05.fdf | 1 +
> Silicon/Hisilicon/Hi1616/Pptt/Pptt.c | 529
> Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 67 +++
> Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf | 48 ++
> 5 files changed, 646 insertions(+)
>
> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
> index 77a89fd..710339c 100644
> --- a/Platform/Hisilicon/D05/D05.dsc
> +++ b/Platform/Hisilicon/D05/D05.dsc
> @@ -506,6 +506,7 @@
>MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
>
>Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
> + Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
>Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>
>#
> diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
> index 78ab0c8..97de4d2 100644
> --- a/Platform/Hisilicon/D05/D05.fdf
> +++ b/Platform/Hisilicon/D05/D05.fdf
> @@ -241,6 +241,7 @@ READ_LOCK_STATUS = TRUE
>INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
>
>INF RuleOverride=ACPITABLE
> Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
> + INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
>INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>
>#
> diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
> b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
> new file mode 100644
> index 000..9ce2b32
> --- /dev/null
> +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
> @@ -0,0 +1,529 @@
> +/** @file
> +*
> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD
> License
> +* which accompanies this distribution. The full text of the license may be
> found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +*
> +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
> +*
> +**/
> +
> +#include "Pptt.h"
> +
> +EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol = NULL;
> +EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol = NULL;
> +
> +EFI_ACPI_DESCRIPTION_HEADER mPpttHeader =
> + ARM_ACPI_HEADER (
> +EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
> +EFI_ACPI_DESCRIPTION_HEADER,
> +EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
> + );
> +
> +EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] =
> +{
> + {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, PPTT_VENDOR_ID, 0, 0,
> 0, 0, 0}
> +};
> +
> +EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO];
> +
> +
> +STATIC
> +VOID
> +InitCacheInfo (
> + VOID
> + )
> +{
> + UINT8Index;
> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
> + CSSELR_DATA CsselrData;
> + CCSIDR_DATA CcsidrData;
> +
> + for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
> +CsselrData.Data = 0;
> +CcsidrData.Data = 0;
> +SetMem (
> + &Type1Attributes,
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
> + 0
> + );
> +
> +if (Index == 0) { //L1I
> + CsselrData.Bits.InD = 1;
> + CsselrData.Bits.Level = 0;
> + Type1Attributes.CacheType = 1;
> +} else if (Index == 1) {
> + Type1Attributes.CacheType = 0;
> + CsselrData.Bits.Level = Index - 1;
> +} else {
> + Type1Attributes.CacheType = 2;
> + CsselrData.Bits.Level = Index - 1;
> +}
> +
> +CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
> +
> +if (CcsidrData.Bits.Wa == 1) {
> + Type1Attributes.AllocationType =
> EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE;
> + if (CcsidrData.Bits.Ra == 1) {
> +Type1Attributes.AllocationType =
> EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE;
> + }
> +}
> +
> +if (CcsidrData.Bits.Wt == 1) {
> + Type1Attributes.WritePolicy = 1;
> +}
> +DEBUG ((DEBUG_INFO,
> +"[Acpi PPTT] Level = %x!CcsidrData = %x!
[edk2] [PATCH edk2-platforms v3 02/15] Hisilicon/D05: Add PPTT support
Add Processor Properties Topology Table, PPTT include
Processor hierarchy node, Cache Type Structure and ID structure.
PPTT is needed for lscpu command to show socket information correctly.
https://bugs.linaro.org/show_bug.cgi?id=3206
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
Reviewed-by: Ard Biesheuvel
Reviewed-by: Graeme Gregory
Reveiwed-by: Jeremy Linton
---
Platform/Hisilicon/D05/D05.dsc | 1 +
Platform/Hisilicon/D05/D05.fdf | 1 +
Silicon/Hisilicon/Hi1616/Pptt/Pptt.c | 529
Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 67 +++
Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf | 48 ++
5 files changed, 646 insertions(+)
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 77a89fd..710339c 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -506,6 +506,7 @@
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
+ Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
#
diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index 78ab0c8..97de4d2 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -241,6 +241,7 @@ READ_LOCK_STATUS = TRUE
INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
INF RuleOverride=ACPITABLE
Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
+ INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
#
diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
new file mode 100644
index 000..9ce2b32
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
@@ -0,0 +1,529 @@
+/** @file
+*
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD
License
+* which accompanies this distribution. The full text of the license may be
found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
IMPLIED.
+*
+* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
+*
+**/
+
+#include "Pptt.h"
+
+EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol = NULL;
+EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol = NULL;
+
+EFI_ACPI_DESCRIPTION_HEADER mPpttHeader =
+ ARM_ACPI_HEADER (
+EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+EFI_ACPI_DESCRIPTION_HEADER,
+EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ );
+
+EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] =
+{
+ {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, PPTT_VENDOR_ID, 0, 0,
0, 0, 0}
+};
+
+EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO];
+
+
+STATIC
+VOID
+InitCacheInfo (
+ VOID
+ )
+{
+ UINT8Index;
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
+ CSSELR_DATA CsselrData;
+ CCSIDR_DATA CcsidrData;
+
+ for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
+CsselrData.Data = 0;
+CcsidrData.Data = 0;
+SetMem (
+ &Type1Attributes,
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
+ 0
+ );
+
+if (Index == 0) { //L1I
+ CsselrData.Bits.InD = 1;
+ CsselrData.Bits.Level = 0;
+ Type1Attributes.CacheType = 1;
+} else if (Index == 1) {
+ Type1Attributes.CacheType = 0;
+ CsselrData.Bits.Level = Index - 1;
+} else {
+ Type1Attributes.CacheType = 2;
+ CsselrData.Bits.Level = Index - 1;
+}
+
+CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
+
+if (CcsidrData.Bits.Wa == 1) {
+ Type1Attributes.AllocationType =
EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE;
+ if (CcsidrData.Bits.Ra == 1) {
+Type1Attributes.AllocationType =
EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE;
+ }
+}
+
+if (CcsidrData.Bits.Wt == 1) {
+ Type1Attributes.WritePolicy = 1;
+}
+DEBUG ((DEBUG_INFO,
+"[Acpi PPTT] Level = %x!CcsidrData = %x!\n",
+CsselrData.Bits.Level,
+CcsidrData.Data));
+
+mPpttCacheType1[Index].Type = EFI_ACPI_6_2_PPTT_TYPE_CACHE;
+mPpttCacheType1[Index].Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE);
+mPpttCacheType1[Index].Reserved[0] = 0;
+mPpttCacheType1[Index].Reserved[1] = 0;
+mPpttCacheType1[Index].Flags.SizePropertyValid = EFI_ACPI_6_2_PPTT_VALID;
+mPpttCacheType1[Index].Flags.NumberOfSetsValid = EFI_ACPI_6_2_PPTT
