Re: [edk2] [PATCH edk2-platforms] Silicon/Socionext/SynQuacer: update PHY reference clock rate
On 19 April 2018 at 17:38, Leif Lindholm wrote: > On Mon, Apr 16, 2018 at 01:00:58PM +0200, Ard Biesheuvel wrote: >> As reported by Kojima-san, the PHY reference clock value we use in our >> ACPI and DT descriptions is out of sync with the hardware. Replace >> 125 MHz with 250 MHz throughout. >> >> Cc: Masahisa Kojima >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel > > Reviewed-by: Leif Lindholm > Thanks Pushed as 6c816b0e4175 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
Re: [edk2] [PATCH edk2-platforms] Silicon/Socionext/SynQuacer: update PHY reference clock rate
On Mon, Apr 16, 2018 at 01:00:58PM +0200, Ard Biesheuvel wrote: > As reported by Kojima-san, the PHY reference clock value we use in our > ACPI and DT descriptions is out of sync with the hardware. Replace > 125 MHz with 250 MHz throughout. > > Cc: Masahisa Kojima > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm > --- > Kojima-san, > > Please confirm that the modification to ogma_config.h is correct. > > Thanks, > Ard. > > Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl >| 2 +- > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >| 4 ++-- > > Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > | 4 ++-- > 3 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > index b6f6c4360029..3f73c191d4d6 100644 > --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > @@ -162,7 +162,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", > "SYNQUACR", >Package (2) { "phy-channel", FixedPcdGet32 (PcdNetsecPhyAddress) }, >Package (2) { "max-speed", 1000 }, >Package (2) { "max-frame-size", 9000 }, > - Package (2) { "socionext,phy-clock-frequency", 12500 }, > + Package (2) { "socionext,phy-clock-frequency", 25000 }, > } >}) > } > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > index 6e93c6ae16a8..f6887329f6c7 100644 > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > @@ -420,9 +420,9 @@ > reg-shift = <2>; > }; > > -clk_netsec: refclk125mhz { > +clk_netsec: refclk250mhz { > compatible = "fixed-clock"; > -clock-frequency = <12500>; > +clock-frequency = <25000>; > #clock-cells = <0>; > }; > > diff --git > a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > > b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > index 1caf64e30623..f6ec9b30ec8e 100644 > --- > a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > +++ > b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > @@ -16,8 +16,8 @@ > #ifndef OGMA_CONFIG_H > #define OGMA_CONFIG_H > > -#define OGMA_CONFIG_CLK_HZ 12500UL > -#define OGMA_CONFIG_GMAC_CLK_HZ 12500UL > +#define OGMA_CONFIG_CLK_HZ 25000UL > +#define OGMA_CONFIG_GMAC_CLK_HZ 25000UL > #define OGMA_CONFIG_CHECK_CLK_SUPPLY > > #define OGMA_CONFIG_USE_READ_GMAC_STAT > -- > 2.17.0 > ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
Re: [edk2] [PATCH edk2-platforms] Silicon/Socionext/SynQuacer: update PHY reference clock rate
Hi Ard, Yes, please apply to all boards. Thank you. On 19 April 2018 at 20:15, Ard Biesheuvel wrote: > On 16 April 2018 at 13:25, Masahisa Kojima wrote: >> Hi Ard, >> >>> Please confirm that the modification to ogma_config.h is correct. >> >> Thank you very much for your update. >> We confirmed and your modification is correct. >> > > Thank you Masahisa > > Does this change apply to all boards? EVB, rev 0.1 etc? ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
Re: [edk2] [PATCH edk2-platforms] Silicon/Socionext/SynQuacer: update PHY reference clock rate
On 16 April 2018 at 13:25, Masahisa Kojima wrote: > Hi Ard, > >> Please confirm that the modification to ogma_config.h is correct. > > Thank you very much for your update. > We confirmed and your modification is correct. > Thank you Masahisa Does this change apply to all boards? EVB, rev 0.1 etc? ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
Re: [edk2] [PATCH edk2-platforms] Silicon/Socionext/SynQuacer: update PHY reference clock rate
Hi Ard, > Please confirm that the modification to ogma_config.h is correct. Thank you very much for your update. We confirmed and your modification is correct. Regards, Masahisa On 16 April 2018 at 20:00, Ard Biesheuvel wrote: > As reported by Kojima-san, the PHY reference clock value we use in our > ACPI and DT descriptions is out of sync with the hardware. Replace > 125 MHz with 250 MHz throughout. > > Cc: Masahisa Kojima > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > Kojima-san, > > Please confirm that the modification to ogma_config.h is correct. > > Thanks, > Ard. > > Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl >| 2 +- > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >| 4 ++-- > > Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > | 4 ++-- > 3 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > index b6f6c4360029..3f73c191d4d6 100644 > --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > @@ -162,7 +162,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", > "SYNQUACR", >Package (2) { "phy-channel", FixedPcdGet32 (PcdNetsecPhyAddress) }, >Package (2) { "max-speed", 1000 }, >Package (2) { "max-frame-size", 9000 }, > - Package (2) { "socionext,phy-clock-frequency", 12500 }, > + Package (2) { "socionext,phy-clock-frequency", 25000 }, > } >}) > } > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > index 6e93c6ae16a8..f6887329f6c7 100644 > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > @@ -420,9 +420,9 @@ > reg-shift = <2>; > }; > > -clk_netsec: refclk125mhz { > +clk_netsec: refclk250mhz { > compatible = "fixed-clock"; > -clock-frequency = <12500>; > +clock-frequency = <25000>; > #clock-cells = <0>; > }; > > diff --git > a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > > b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > index 1caf64e30623..f6ec9b30ec8e 100644 > --- > a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > +++ > b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > @@ -16,8 +16,8 @@ > #ifndef OGMA_CONFIG_H > #define OGMA_CONFIG_H > > -#define OGMA_CONFIG_CLK_HZ 12500UL > -#define OGMA_CONFIG_GMAC_CLK_HZ 12500UL > +#define OGMA_CONFIG_CLK_HZ 25000UL > +#define OGMA_CONFIG_GMAC_CLK_HZ 25000UL > #define OGMA_CONFIG_CHECK_CLK_SUPPLY > > #define OGMA_CONFIG_USE_READ_GMAC_STAT > -- > 2.17.0 > ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel