On Thu, Feb 08, 2018 at 10:18:12AM +, Ard Biesheuvel wrote:
> We already disable SDR104 support on the SynQuacer eMMC controller to
> work around the need for a special tuning quirk that is difficult to
> implement without modifying the generic driver, even in the presence
> of a SD/MMC override protocol designed to carry such quirks.
>
> Unfortunately, as it turns out, DDR50 does not work either with the
> particular 8 GB Kingston part that has been fitted on the rev0.2/0.3
> 96board samples. Since the mode UEFI drives the eMMC in is independent
> from what the OS chooses, and the fact that you would not use eMMC in
> the first place if performance was a major concern, let's just disable
> DDR50 as well, and fall back to SDR50 mode.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel
Reviewed-by: Leif Lindholm
> ---
> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c
> b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c
> index c40b30929d5d..6875dfe6b319 100644
> --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c
> +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c
> @@ -52,6 +52,7 @@
> #define SYNQUACER_CLOCK_CTRL_VAL 0xBC01
>
> #define SD_HC_CAP_SDR104 BIT33
> +#define SD_HC_CAP_DDR50 BIT34
>
> #define ESD_CONTROL_RESET_DELAY (20 * 1000)
> #define IO_CONTROL2_SETTLE_US 3000
> @@ -95,7 +96,7 @@ SynQuacerSdMmcCapability (
>// quirk that is difficult to support using the generic driver.
>//
>Capability = ReadUnaligned64 (SdMmcHcSlotCapability);
> - Capability &= ~(UINT64)SD_HC_CAP_SDR104;
> + Capability &= ~(UINT64)(SD_HC_CAP_SDR104 | SD_HC_CAP_DDR50);
>WriteUnaligned64 (SdMmcHcSlotCapability, Capability);
>
>return EFI_SUCCESS;
> --
> 2.11.0
>
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